TW519758B - Process integration method and its structure of I/O redistribution and passive device manufacture - Google Patents

Abstract

A process integration method and its structure of I/O redistribution and passive device manufacture are disclosed in the present invention. In the invention, passive devices such as resistors or capacitors are formed on the conduction region when performing I/O redistribution. According to the invented method, the sticking layer is manufactured by highly resistive material, such as TiW or TiN, and is connected between the conduction regions for use as a passive resistor. The formation of passive capacitor requires an extra deposition procedure, wherein a dielectric layer and a conduction layer are deposited in the conduction region on the pad. Therefore, the capacitor or the resistor can be formed on the conduction region when forming the conduction region by slightly changing the procedures of the conventional I/O redistribution process.

Description

V. Description of the invention (1) [Scope of the invention] The present invention relates to a method of resolving a problem, and is particularly relevant to the I / O redistribution system of integrated circuit pack chips. H-Coated Film Resistor or Thin Film Electronics Office DD > Integration Method for Passive Components as Thin Process and Its :: Redistribution and Passive Component Manufacturing [Background of the Invention] During the manufacturing of integrated circuit components, the chip Or it can be combined with other substrates (such as printing Lei Mu, Shikou Congren J: 士 入 古 彳 i 土 π _ 丨 brush circuit board), I. Most of the mouth-to-mouth methods are hunted by the wire bonding method. Frost Days (垃 η, n ^ wire Bonding Process) FUP Chip Attachmem Method achieves the online bonding method. Prepare one m # 曰 h L Metnocu Yuncheng. -r & / The ends of the multiple I / 0 bumps located on the Japanese-Japanese film can be connected to the dry pads on the substrate ^ ^ ^ 形成 to form a hairy lice; and the flip-chip bonding technology stands on the wafer The ends of the 1/0 bumps are made of solder (Sodler). 'The most commonly used solder is a high-solubility tin-lead alloy with a tin-lead composition percentage of 3% tin and lead 97%. During the bonding process, , The semiconductor wafer uses the self-alignment (Sel f_AHgment) effect of the solder bumps in the heavy-flow furnace so that each I / 0 contact on the semiconductor wafer can be accurately bonded to the pad of the substrate. Compared with the wire bonding method, the above-mentioned flip chip bonding technology has one of the biggest advantages. 'It can get a higher density of 丨 / 〇 and improve the reliability of the interconnects (Interconnects). At the same time, the wire bonding method is limited by 〖/ Ο The number of interconnects makes it impossible to make a high-density semiconductor element, so the flip-chip bonding technology is widely used to manufacture high-density semiconductor elements. However, there is a limiting factor when using flip-chip bonding technology, that is, a fine pitch (F 丨 n e p i t h) pad must be manufactured during the bonding process.

519758 V. Description of the invention (2) (Bonding Pads), for example, in the manufacture of high-density memory devices, a plurality of solder pads regularly arranged along the peripheral periphery (Per iphera 1) of the aforementioned device, the spacing of which is less than 1 0 0 // m, and in such a small space, it is difficult and expensive to dream of joining the solder bump (Solder Bump) to the substrate. In addition, the flip-chip bonding technology has several disadvantages, such as the slow filling speed of the primer during the coating process (Underfi 1 1); and, in response to the above-mentioned components with fine pitch I / 〇, The cost of using a high-depletion substrate is too expensive and so on. π & In order to solve the problem that the integrated circuit components and the substrate are difficult to bond due to the small pad pitch, before the solder bump is formed, the I / O pad redistribution process (I / O Pad RedistributiQn

Process), using a signal line (Slgnal Trace) to extend the 1/0 pads from the periphery of the component to the middle of the component, and arrange them in an area matrix (Area — Array) to increase the spacing of the I / 0 pads, The plan view is shown in "Figure VII". As shown in "Figure 1", a plurality of I / O pads 12 arranged in a peripheral matrix are first formed on the integrated circuit wafer, and the distance between the two 1/0 pads 12 is defined as X) is about 100. During the 1/0 pad redistribution process, a plurality of signal lines 14 are formed and extended to extend the peripheral moment arrangement = 1/0 pads 12 to 1/0 pads 16 arranged in a face matrix, that is, The female-k line 14 is connected to a pair of 丨 / 〇 = pads 12 and I / O pads 16 located at the center of the wafer, respectively; compared with the Gongchuan pads 12 arranged in a peripheral matrix The matrix-arranged 1/0 pads 16 have a larger pitch. For example, in this embodiment, the spacing between 丨 / 〇pads 6 is approximately

519758 Fifth, the description of the invention (3) is four times the pitch of the I / 〇 pad 12. Therefore, the density of the substrate can reduce the substrate's substrate. The substrate no longer requires a high process to bond the flip chip to a low-cost substrate. It can allow the use of traditional I / O redistribution process to make high-density integrated circuit components. I / O redistribution = two points, now in the manufacturing step. The process is redistributed by I / O. The process is a very heavy I / O pad, and a solder bump is formed on the I / O pad. // It is connected to other wafers or printed circuit boards with a large distance. Man, Α 1 uses this material to perform bump surgery. In addition, when using the above-mentioned epitaxial wafer; making ς :; advancing, flip-chip bonding, often includes a passive component (Passi ==: Road Microelectronics Γ This passive component can be a thin film resistor or thin film: p :: ent) to make passive electronic circuit components and / or bearer thunderbolts in the Papa circuit to improve and improve electrical properties. The use of Zhan Hongzi circuit components, [Objective and summary of the invention] and passive components ί: ί ϋ ::::: 1/0 redistribution process;! Month production such as resistors or electrical parts redistribution and passive Yuan, Taiji (hln Fllm ReS1Stor) or capacitor (capacit0r). Yuan Zhu ^ Ming another purpose is to provide a kind of 1/0 redistribution and passive (H .: J process integration 'which includes deposition-an adhesive layer (Adhesion layer formed by high resistance value material L / g eS1StanCe Material) ) To make passive components. Page 6 519758 V. Description of the invention (4) The component provides-a kind of 1/0 redistribution and passive signals d ::; # The deposition-adhesion layer is included between the pads. And 4 attached layers are made of 1 ^, TiN or other high-resistance material components. ^^: Provides a 1/0 redistribution and passive product-about 5 by the technology of Gaoyouba Sputtering). _ ~ 5. The adhesion layer formed by the second layer has a large thickness: there are: ^ another /; focus: on, / for-a kind of integrated circuit element, which has a layer, this high-resistance second resistor. Our + layer is "behind the bluff line, as a passive electricity ^ The final purpose of the invention is to provide an integrated circuit with several redistribution systems through 1/0 redistribution", among which The two tops of the aforementioned integrated circuit element row—bottom electrode ("Bottom Electrode", "Erbede, 仏 虎 元 #: 2" disclosed in the present invention—a kind of 1/0 redistribution and passive and right = shirt red shift The manufacturing method includes at least: providing a substrate having at least two conductive pads; forming a protective layer to cover the pads, and providing the pads B Spread electrical contacts, each forming a contact window on the Keshu pad to expose the

Page 7 519758 V. Description of the invention (5) Two solder pads; deposit an adhesive layer on top of the solder pad and the protective layer; Wetting layer (also known as tin layer) on the adhesive Layer, top, F, coating a first photoresist layer on the wet layer, and define the first photoresist layer j to expose the conductive area (conductive trace) to be formed on the pad; And forming a conductive area; removing the first photoresist layer; coating a second photoresist layer to cover the area between the conductive areas; etching the area of the adhesion layer and the wet layer not covered by the conductive area and the second photoresist ; Remove the second photoresist layer; and etch the wetting layer between the conductive areas so that the retained adhesion layer acts as a resistor between the conductive areas or the conductive area as a formed valley One of the basic electrodes (Base Electrode). ‘The above-mentioned adhesive layer may be made of the following materials, such as T 丨 W, τ 丨 n,

Tl 'ClV Ta2N' W2N 'TaAl, Tan, TaSl or Polysilicon is deposited, and can be achieved by sputtering, and its thickness is between 50nm ~ 50〇nn] . The wet layer and the conductive layer ^ are made of copper metal or other highly conductive metals; the money engraving process used to remove the adhesion layer and the wet layer is-wet money engraving; at the same time, the manufacturing method further includes The following steps: After etching (After EtcMng) points = wet = 1/0 between pads, definition and remaining adhesion layer to form a passive resistor with a pre-ghost degree and appearance, which is used to achieve high ^ And the predetermined appearance of the value may be a serpentine shape. ! / 二 According to the description of Λ / producing steps ’The present invention also discloses a method for re-dressing through -0, V includes ... a plurality of pads formed on a page of two components; at least two

^ 19758 V. Description of the invention (6) A signal line made of conductive metal is used to contact and connect to the bonding pad, and a high-resistance material layer deposited on top of the aforementioned component is used to provide at least two Electrical connection between two signal wires. It: 丄 The above elements further include a plurality of 丨 / 〇I / O arranged in a face matrix. Lanes ^ § The two ends of the line are connected to the I / Oi arranged in a peripheral matrix, respectively: dry pad and face 1 / () pads arranged in a matrix, made of one of other highly conductive materials; at the same time: made of dagger, copper, or formed pads, or formed with-'二 = τ Above the mat. The adhesive layer consists of a two-inch g resistor with a high resistance and a wet resistor. In addition, the integrated circuit described above is only formed to serve as a dielectric layer that allows a plurality of solder pads to be buried in seven of them and further includes a dielectric layer for gas insulation. In this integrated circuit element 2, to provide electrodeposition between the pads on top of the dielectric layer to form: In the structure, a high-resistance value material layer is disclosed although the above is a kind of breaking resistor . Manufacturing method of integrated manufacturing system 'value / 〇 reallocation and passive component system I / O reallocation and passive capacitor system ~ $ This method can also be applied to, its manufacturing steps include at least ... to provide ~ I process integration A manufacturing method, a plate; forming a first dielectric layer to cover the electrical insulation between at least two conductive pads; describing at least the pads, and providing the aforementioned solder to expose the at least two pads Deposition II: a top of a contact window is formed on each of the pads; a wet layer is deposited on the top of the adhesive pad and the first dielectric brow layer on the wet layer, and the top of the first photoresist is defined; coating A first light / intermediate area / conducting area; a deposition—a second—conducting to expose the photoresist layer to be formed on the pad; a first—a metal layer and forming a conductive first resistance is electrical. "Secret private shovel, said to cover the conductive area between the first) 丄 9758 V. Description of the invention (7) domains; engraved adhesion layer and thirsty screen enemies 1, all 莒 + r A · # —", ,] Layer is removed in the area not covered by the conductive area and the second photoresist layer. Zeng + ren A, a special resistive layer, depositing and defining a second dielectric layer to set up a conductive metal layer, and a Miao, ancient one soil; 2 /, the conductive metal layer is not completely covered by electricity Eyebrow and complex contact area: deposit and define a second conductive metal layer on top of the second dielectric acoustic moss I, where the first conductive metal and the second metal are absolutely What? MF +. Ries? ^, Xiangguan Qi Ding ', and provides the contact of the first conductive metal. = Brother: Electrical contact between conductive metal layers. # ϋ ϋ # A Μ In the preferred embodiment disclosed in the present invention, the adhesive layer is made of a material with high resistance; and the second conductive metal layer is the second conductive metal layer. It is formed by copper or its electric metal layer-the bottom is formed and the first conductive Ti is defined. The second conductive metal is defined to form a top electrode and is used as a passive capacitor. . In order to make the above-mentioned taste of the present invention more obvious, the following particulars—comparisons, features, and advantages—are explained in more detail below. An example of a car garden, and with the accompanying drawings, [Detailed description of the invention] In the present invention, the method of integration of the letter + + τ. ^ And the method of making:]: Type 1 2 Redistribution and passive components At the same time, the manufacturing process is performed in two. On the passive element # π,,,,,, and / / which are redistributed, a moving element such as a film resistor or a film capacitor is formed. The following describes the advantages of replacing people: First, = There are no steps that can be added for the following reasons: 1/0 redistributing process and increasing passive components "σ passive resistance; ^ two zones Λ At the same time, the entire high-resistance material sinker is also formed on the conductive area: (or f mover); Second, the degree and appearance of the spoon can be adjusted to control the subsequent formation of electricity.

519758 V. Description of the invention (8) Resistance value of the resistor ^ In the present invention, the conventional I / 0 redistribution process is used to make small changes in the method of forming signal lines, so as to facilitate the formation of signal lines, Can make film capacitors or film capacitors. The method is: before forming a signal line, first use a sputtering method to apply a high resistance value material, such as TiW, TiN, Ti, (: r, Ta2N2, W2N, TaAl, TaTi, TaSi, or P〇1 ysi 1 ic ο An adhesive layer made of one of the materials such as ne is deposited on top of the protective layer of the pads arranged in a peripheral matrix, and this adhesive layer is defined by photolithography technology to achieve the desired width and appearance. In the present invention In the disclosed method, a copper trace is used as the bottom electrode of the capacitor, a dielectric layer is deposited on top of the bottom electrode, and the dielectric layer is defined by photolithography to form a capacitor dielectric ( Capacitor Dielectric). The bottom end of the bottom electrode is not covered by the dielectric layer, which allows the bottom electrode to form an electrical connection with the outside world. A top electrode is then deposited and a second conductive layer is defined on top of the dielectric layer. Although the above The copper region is used as the bottom electrode, but other highly conductive metals can be used instead of the copper region. In the following description, only a preferred embodiment is used to describe the I / 0 re-disclosure disclosed in the present invention. The manufacturing method and structure of the integrated process of matching and manufacturing passive components, in which the manufacturing flow chart accompanying the formation of passive resistors in the I / 0 redistribution process is shown in "Figure 2A ~ 2F", forming a passive resistor The form can be as shown in "Figures 3A and 3B"; and the schematic sectional view accompanying the formation of a passive capacitor is shown in "Figure 4". First, please refer to "Figures 2A to 2F", which is disclosed in the present invention Of

HI HI Page 11 519758 V. Description of the invention (9) A cross-sectional view of the manufacturing process of integrated circuit components (passive resistors). As shown in FIG. 2A, the integrated circuit element 20 is fabricated on a silicon substrate 22. When making, it must be formed :): dry pad 24. The formation of the bonding pad 24 is firstly performed by a metal deposition process = aluminum or a conductive metal thereof, and then is defined by a photolithography technique. After the pads 24 are formed, a protective layer (Pa / Sslvation Layer) 28 made of an insulating material, such as an oxide, a nitride, or an organic material, is deposited on top of the pads 24 to protect the pads 24. . The protective layer 28 is formed, and then the photolithography technology is used to open the view of the protective layer 28 to be electrically connected, so that the top surface 34 of the bonding pad 24 is exposed. Next, a sputtering process is applied to the top surface 3 4 of the solder pad 24 > an adhesive layer 3 0 is deposited on the top surface of the solder pad 24, and this adhesive layer 3 can be passed through the top surface 34 of the solder pad. An electrical connection between the pads 24 is provided. Finally, a wetting layer 38, or tin layer, may be deposited to facilitate subsequent metal deposition. Among them, the wet layer 38 can be made of copper or other highly conductive metals. " In the preferred embodiment, the above-mentioned adhesive layer 30 may be a material having a high resistance value, such as TiW, TiN, Ti, Cr, Ta2N, W2N, TaAl, TaTi, or * P〇lysUl \ 〇ne. Once made, the effect of its electrical connection is better. In addition, the thickness of the adhesion layer 30 deposited by the sputtering deposition process is approximately 5011111 to 50011111, and preferably 1001111] to 30011111. Next, the first photoresist layer 46 is used to define the conductive area, that is, the first photoresist layer 46 'is first coated, and then the conductive area is patterned, as shown in FIG. 2B. Next, a conductive metal is deposited to form the copper regions 40 and 42. Then, the first photoresist layer 46 is removed to allow the copper regions 40 and 42 to be formed.

Page 12 519758 V. Description of the invention (10), as shown in "Figure 2C". In addition, the copper regions 40 and 42 can also be made by depositing other highly conductive metals. Then, the part that starts to make passive resistors, please refer to "# 2D 图". The passive resistor 50 can be designed as the copper area 40 and the copper area, that is, the shape and the characteristics of the shape, length, width, and material, which are pre-decorated in the "Figure 2A". In the figure, the area where the passive resistor 50 is deposited is defined as the second sub-substrate, and the wet layer 38 and the adhesive layer 3 covered by the second photoresist layer 52. d: The process of 3 ° wet layer 38 and adhesive layer can be made by wet method ::, and it is shown in "Figure 2E". The production of the device 50 is like the "wet layer 38 on 20, that is, the passive resistance is completed. # 彳 a * 丨 ⑻ 弟 2F 图" is not available. The moisturizing layer 38 is removed by a t-etching process. 0%, the technology of the area = ϊ = the technology disclosed can obtain the resistance formed on the conductive plate. π 0, the resistance value of the passive resistor 50 is smaller than that of the PC variable adhesion layer 30. On: The resistance value of the above passive resistor can be adjusted by changing the degree of the passive resistor. As shown in "Figure 3A", the straight line shape 5 6. The shape can be either the region 40 connected to the copper region 40 and the copper region 42 and the copper region 42, or as shown in the figure 3B. It is shown as a serpentine shape 66 connected to the largest guard J of the present invention. And the process can form a guide ^, as long as the conventional I / 〇 redistribution system, hair area is also changed, while also forming a resistor or capacitor to conduct electricity

Page 13 519758 V. Description of the invention (ii) '' — — 1 — -—— The process can form a conductive region and also form a resistor or capacitor between the regions', which can shorten the process steps. Push-'4th f ", # is an enlarged cross-sectional cross-sectional view of the passive state 70 formed on the conductive region while the I / O redistribution process is being performed according to the technology disclosed in the present invention. As shown in the "Figure 4" on the top of the road element 20, a copper area 40 is formed: a shell-electric pattern is screen-printed on the copper area 4. In order to form a bottom process = two parts, a dielectric sound 72 having a thickness of about 50 nm to 500 nm is deposited, and the dielectric layer 72 is defined by a photolithography process to form a sub-LT " ^ ileleCtriC) 74 ^ Only in June, the dagger field was used as an electrode connection, so that the subsequent process will send the developer in the final step, and the dielectric layer 72 will be used to accumulate the electrode. It is made of copper, for example, and then processed by photolithography to: Guangji-the second conductive layer (so far as this step, it has been thinned in the copper base. To the above, the passive state 70 of the capacitor 70 is manufactured. 76 (can be referred to as the first guide σ 卩 edge of the copper area 40 of the bottom electrical dielectric thickness ^ Through the above description, the present invention redistributes the resulting solder pad ^ on ^ ^ There are two parts, namely: a number of strict structure; the top surface of the piece; at least two signal lines, contact = on the integrated circuit pad, and a layer of high resistance material materials are connected by touch. Each soldering top is used to provide the deposition between integrated circuit components among signal lines. The arrangement of the solder pads can be S = ί. Μ Peripheral matrix arrangement or the surface. Page 14 519758 V. Description of the invention (12) Matrix arrangement. As for the material of each component of the integrated circuit element, since it has been mentioned in the above detailed description, it will not be repeated here. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit it. The present invention, anyone skilled in the art, Within the spirit and scope of the present invention, some modifications and retouching can be made. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

519758 on page 15 Brief description of the drawing Figure 1 is a schematic plan view of a traditional high-density integrated circuit component after a 1 / 〇 redistribution process; _ Figure 2A, which shows that the integrated circuit element of the present invention has An enlarged cross-sectional view of a solder pad, a protective layer, an adhesive layer, and a wetting layer; FIG. 2B, which shows' depositing a first photoresist layer on the integrated circuit element of FIG. 2A, and defining that the exposed layer is to be conductive. Enlarged cross-sectional cross-sectional view of the area; FIG. 2C shows an enlarged cross-sectional view of the right on the integrated circuit element of FIG. 2B to form the conductive area and remove the first photoresist layer; FIG. 2D "Cross-sectional view of a second photoresist layer deposited on the integrated circuit element of Fig. 2C" Figure 2E, shown on the integrated circuit element of "Fig. 2D", removed between the conductive regions A magnified cross-sectional view of the second photoresist layer and the wetting layer; FIG. 2F, which is shown on the integrated circuit element of the “picture 2E”, 'remove the adhesive layer and the wetting layer from the outer area of the electric region, and Adhesive layer between conductive areas can be used as An enlarged cross-sectional view of a passive resistor; FIG. 3A 'shows an enlarged cross-sectional view of the integrated circuit element of the present invention having two conductive regions and a 1-pitch resistor; FIG. 3' shows an integrated body of the present invention Circuit element I has two conductive areas and a serpentine shape, n Figure 4. g—enlarged cross-sectional view of a broken resistor; and 彳 ^^ 动 " ^ 4 发明 发明The integrated circuit element has an enlarged cross-sectional cross-sectional view of a rabbit container formed in a guide.

Page 16 519758 Page 17 Schematic description 10 Integrated circuit chip 12 Solder pad 14 Signal line 16 Solder pad 20 Integrated circuit element 22 Silicon substrate 24 Solder pad 28 Protective layer 30 Adhesive layer 34 Top surface 38 Wet layer 40 Copper Area 42 Copper area 46 First photoresistive layer 50 Passive resistor 52 Second photoresistive layer 56 Linear shape 60 Passive resistor 66 Gentle shape 70 Passive capacitor 72 Dielectric layer 74 Capacitor dielectric 76 Bottom electrode 80 Top electrode

519758

Page 18

Claims (1)

519758 VI. Application Patent Scope 1. A process integration method for I / 0 redistribution and passive component fabrication, including the following steps: providing a substrate with at least two conductive pads; forming a protective layer to cover the two pads To provide an electrical barrier between the two pads; forming a contact window on each of the at least two pads to expose the at least two pads; and depositing an adhesion layer on the two pads and the protective layer Depositing a wet layer on top of the adhesion layer; coating a first photoresist layer on the wet layer, and defining the first photoresist layer to expose at least two to be formed on the two pads A range of conductive regions; depositing a conductive metal and forming the at least two conductive regions; removing the first photoresist layer; coating a second photoresist layer to cover a region between the at least two conductive regions; etching Areas where the adhesion layer and the wetting layer are not covered by the at least two conductive areas and the second photoresist layer; removing the second photoresist layer; and " I etched between the conductive areas Wet layer 'to make sure The adhesion layer is left as a resistor of the at least two conductive sections or the at least two conductive sections are used as a basic electrode of a formed capacitor. 2. The process integration method of I / O redistribution and passive component manufacturing as described in item 1 of the scope of patent application, wherein the adhesion layer is made of tungsten titanium (T i W), nitrogen Page 19, 519758 VI. Application scope Patented titanium (TiN), titanium (Ti), chromium (Cr), tantalum nitride (Ta2N), ditungsten nitride (W2N), aluminum button (TaAl), titanium button ( TaTi), TaSi and Polysilicon are deposited. 3. The process integration method of I / O redistribution and passive component manufacturing as described in item 1 of the scope of patent application, wherein the deposition of the adhesion layer can be achieved by sputtering 'and its thickness is about 50nm ~ 500nm. 4 · The I / O redistribution and passive clothing integration method described in item 1 of the scope of the patent application, wherein the wet layer is deposited by copper. 5 · The method of I / O redistribution and passive component manufacturing as described in item 1 of the scope of patent application, wherein the conductive area is made of copper. 6. The process integration method of redistribution and passive component manufacturing as described in item 1 of the scope of patent application, wherein the step of removing the adhesion layer and the wet layer is performed using a wet etching process. 7. The process integration method of I / O redistribution and passive component manufacturing as described in item 1 of the scope of patent application, wherein the step of removing the wet layer is a dry etching process. Shenyue's patent scope 苐 1 of the I / 〇 redistribution and passive component system = integration method, which further includes the following steps: after the wet layer is located between »= ^ electrical area, patterning (patterning ) And an etcher station with a layer to form-passive resistors with / predetermined width and appearance are made as follows: 17 in the scope of item 8 redistribution and passive component potential 10-^ /, redistribution via an I / O Integrated Electricity of Solder Pads Formed by Process 519758 The circuit component structure claimed in the May patent includes a plurality of solder pads formed on the top surface of the integrated circuit component; at least two signal lines formed of a conductive metal for contacting and connecting the plurality of solder pads; and- A layer of high-resistance material 'deposited on top of the integrated circuit element is used to provide an electrical connection between the at least two signal lines. 1 1 · An integrated circuit element having a pad formed by a redistribution process as described in item 1 of the scope of the patent application, wherein the plurality of pads are arranged in a surface matrix and a peripheral matrix, The combination of the two methods is arranged. 1 2 · An integrated circuit element having a pad formed by a redistribution process as described in item 丨 0 of the patent application scope, wherein the at least two signal lines are respectively connected to the peripheral matrix array; [/ 〇 Pads and I / O pads arranged in face moment. The integrated circuit element having the solder pad formed by the I / O redistribution of Guangshen as described in item 10 of the patent claim, wherein the at least two signal wires are made of copper. . The scope of the patent claims stated in item 10 has a redistribution via an I / 〇 The integrated circuit element of the formed solder pad, wherein the at least two signal lines are formed above the plurality of solder pads made of aluminum. σ • 2 states that the integrated circuit element having a pad formed by a redistribution of an I / 0 as described in item 10 of the patent scope, wherein the at least two signals, the spring system is formed in the plurality of cells having a Above the adhesive layer and a wetting layer. 519758 VI. Application scope of patents-1 p • Integrated circuit components with solder pads formed through a 丨 / 〇 re-division process as described in item 丨 5 of the scope of application for patents, where the adhesive layer is 7 It is formed by a material with a 17-local resistance value and is used as a passive resistor. • Integrated circuit elements with solder pads distributed through a fiJ ^ ^ _ as described in the scope of the application for patent, which includes Λ electric 屛,-human right has a dielectric layer can be The plurality of bonding pads are buried therein, the compound Zhao _ and Nimaru τ to provide electrical insulation between the 18 bonding pads. • Application for the integrated circuit element with a strong and smooth structure as described in item 7 of the patent scope, where the height is high; weight: two adapters 7 are deposited on top of the dielectric layer to form a passive resistance material 19'-T / A soil. The process of redistribution and passive capacitor fabrication is integrated into the following steps: Method 0, providing a substrate with at least two conductive pads; + M forming a first dielectric layer to cover Electrical insulation between the two soldering heats, P; entrusting the small A f to form a contact on each of the at least two pads, depositing an adhesive layer on the two pads and the first interface Office, child layer = accumulate a wet layer on top of the adhesive layer · Hongsi applies a first photoresist layer to the wet layer °, 廿-the inner resist layer to expose the to-be-formed + Λ / sub The range of the conductive area of ours; to) to two of the two pads; self-explanatory reading department 1 519758 Scope of patent application Depositing a first conductive metal layer and forming the at least two conductive layers to remove the first photoresist layer; coating a second photoresist layer to cover an area of the at least two conductive areas; and etching the adhesion layer and The wet layer; the free layer is not covered by the at least two conductive impurities and the second photoresist layer; and the first photoresist layer is removed, and a second dielectric layer is deposited and defined to cover The first conductive gold layer 'and leaving the first conductive metal layer with an uncovered junction area; depositing and defining a second conductive metal layer on top of the second dielectric reed, wherein the second conductive metal The layer is insulated from the first conductive metal layer; and provides electrical contact between the contact area of the first conductive metal layer and the second conductive metal layer. '2 〇 · The process integration method of I / 〇 redistribution and passive capacitor production as described in item 19 of the scope of patent application, wherein the adhesion layer is made of tungsten (TiW), titanium nitride (TiN), titanium (Ti), chromium (Cr), tantalum nitride (Ta2N), ditungsten nitride (W2N), aluminum button (TaAl), titanium tantalum (TaTi), silicide button (TaSi), and polycrystalline silicon (Polys i 1 icon) Choose one of them. 2 1 · The process integration method of 1 / 〇 redistribution and passive electrical device manufacturing as described in item 19 of the scope of patent application, wherein the first conductive metal layer and the second conductive metal layer are made of copper. 519758 Page 24