TW519682B - Method of preventing peeling of shallow trench isolation layer on wafer - Google Patents

Abstract

This invention provides a method of preventing peeling of a shallow trench isolation layer on a wafer suitable to be used for a high temperature furnace. The high temperature furnace has a wafer cassette, with a plural number of positions, installed to carry wafers. The method comprises the following steps: loading at least one monitor wafer into at least the first position of the wafer cassette; loading at least one wafer into the second position of the wafer cassette, in which there is a shallow trench isolation structure on the wafer and the deposited layer on the back side of the monitor wafer is the same as that of the wafer; performing a high temperature treatment on the wafer cassette carrying the monitor wafer and the wafer in the high temperature furnace.

Description

519682 V. Description of the Invention (l) Field of the Invention The present invention relates to a shallow trench isolation structure for a wafer, and in particular, a method for avoiding peeling of the shallow trench isolation layer on the outer edge of a wafer. f. Background of the Invention With the development of semiconductor integrated circuit manufacturing technology, components have been continuously reduced due to the increase in the degree of accumulation. Although the size of the components is reduced, each component in the chip must still be properly insulated or isolated to obtain the good properties of 70 crystals. This technology is generally called device isolation technology. Its main purpose is to form spacers between components, and to minimize the area of the spacers while ensuring good isolation. Free up more chip area to accommodate more components. Among various component isolation technologies, the current shallow low tfeneh isolation process is a semiconductor manufacturing technology that has received much attention recently because of its advantages such as small isolation area and maintaining flatness of the substrate after completion. Generally, the manufacturing method of a shallow trench isolation region is to form a shallow trench (sha 1 1 0 wtrench) in a specific region of a semiconductor substrate, and then fill an insulating material (such as an oxide layer) in the shallow trench to form a shallow trench. The technology of trench isolation regions has been widely used in the fabrication of semiconductor integrated circuits. And 'this shallow trench spacer has also been successfully used to isolate semiconductor elements. However, in the actual manufacturing process, it was found that after the wafer is processed in the high-temperature furnace tube, the problem of spalling of the oxide in the shallow trench isolation layer in the outer edge region of the wafer occurs. Participate

0503-7159TWf; TSMC200M002; Peggy.ptd Page 4 :) 丄

drop. "The shallow trench isolation structure of the domain 14 often has an oxide layer. The shallow trench separation is easy to occur in a vertical furnace. When it is set up automatically, it is generally uncoated and it is found that it usually adopts vertical quartz furnace tubes. For the purpose of loading wafer wafers, it is usually set by a robotic arm, and the π-structure oxide layer is peeled off. After continuous inspection, the roundness is processed by the high temperature furnace tube. At present, the high temperature furnace tube official design (vertical type). A vertical boat with vertical reaction is placed at vertical high temperature to carry multiple wafers. $ Process or the operation of an automatic robotic arm, at a fixed position in the boat to detect # (m〇nit〇r

Wafer. The size of this type of control wafer is the same as that of a bare wafer with any coating material on the same batch of wafers. It is only used as an automatic reference point or calibration point, or an automated process test. The peeling is usually related to the temperature gradient of the wafer surface in the f-tube and the gas flow pattern. The wafer under the prosecution wafer is often different from other wafers and wafers, which causes the wafer under the Shou Shuanghuan wafer to be easily nitrided by the nitrogen gas passing through it (anneaHng) temperature ( nitridize)

Peeling of the isolation layer. As a result, in the same batch of wafers, the wafer yield under the prosecution wafer is low. Brief Description of the Invention In order to solve the problem of peeling off the shallow trench isolation layer on the outer edge of the wafer, an object of the present invention is to provide a method for avoiding the peeling of the shallow trench isolation layer.

0503-7159TWf; TSMC200M002; Peggy.ptd Page 5 519682 V. Description of the invention (3) One method, applicable to high temperature furnace officials, can prevent the shallow trench isolation layer from peeling off at the edge of the wafer after high temperature furnace tube processing. problem. The method for avoiding the stripping of the shallow trench isolation layer of the wafer according to the present invention is applicable to a high-temperature furnace. A wafer boat having a plurality of positions for carrying a wafer is set in the temperature-stabilizing furnace tube. The method includes the following steps: At least a first position in the wafer boat is loaded with at least one control chip; at least a second position in the wafer boat is loaded with at least one wafer, wherein the wafer has a shallow trench isolation structure, and the control wafer The backside coating is the same as the backside coating of the wafer; the wafer boat carrying the inspection sheet and the wafer is subjected to a high temperature treatment in the high temperature furnace tube. In the above method, the control chip may be a wafer die, and the back surface plating layer and the back surface plating layer of the wafer may be a silicon nitride (s) N coating. The boat can be installed in the high-temperature furnace tube in a vertical manner. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following detailed description is given in conjunction with the accompanying drawings: The drawings are briefly explained. FIG. 1 shows the occurrence of the conventional wafer shallow trench isolation layer peeling. Area schematic. Figures 2.A and 2B show the structure of the vertical high-temperature furnace tube. FIG. 3 is a flowchart of a method for avoiding stripping of a shallow trench isolation layer of a wafer according to an embodiment of the present invention. Figures 4A and 4B show a shallow trench isolation layer for the wafer below the blank wafer die and the wafer with a silicon nitride coating on the back as inspection sheets according to one embodiment of the present invention. Measure the thickness increase.

0503-7159TWf; TSMC2001-1002; Peggy.ptd 519682 V. Description of the invention (4) Symbol description 10 ~ wafer, 1 ~ 4 ~ shallow trench isolation structure peeling area; 20 ~ Nanwen furnace official, 22 ~ wafer; 2 4 ~ Crystal boat, 24A-^ 2 4 C ~ position of the prosecution sheet; 3 02 ~ 3 06: process steps; A ~ B ~ wafer. Example First, referring to Fig. 2A, a vertical high-temperature furnace tube structure will be described. In the quartz furnace tube 20, a vertical reaction wafer boat 24 is provided to carry a plurality of wafers 22. And in order to cooperate with the automated process or robotic arm ^ In addition to the wafer loading position in the wafer boat 24, it is usually used as a special ... to replace the general wafer with a monitor wafer, such as Zeng's sink Positions 24A, 24B, and 24C are respectively located at the lower three fixed positions of the vertical wafer boat 24 in the same position. See also 'The surface has finished the high-temperature furnace tube processing schedule. First, perform wafer matching with 20 high-temperature furnace tubes in the furnace tube. Next, the upper, middle, and third drawings of the backside plating and the wafer carried in the crystal are described in detail. According to the present invention, a wafer with a shallow trench isolation structure is formed. In the above-mentioned poor embodiment, the wafer is prevented from being isolated from the shallow trench. Step 3 2 in the layer separation 2 picture. Load plural numbers in the crystal boat 24. The square flow boat 24 is designed to carry multiple wafers. Depending on the high temperature, there are grooves inside, which can hold more than 150 pieces. It is planted in more than 150 pieces and placed in the center. Step 3 0 4 ·· The predetermined prosecution pieces in the crystal boat 2 4 are the same. In a better case, ^-crystal boat, will be set on the crystal boat a number of ^ to the Wen Yi tube, the righteousness, such as

〇503-7159TWf; TSMC2001-1002; Peggy.ptd 519682

The front and rear ends of the wafer boat 24A and 24C and the middle position 24β are used instead of ordinary wafers. The control film is usually used to monitor the high-temperature eight-year-old control film, and the tester who obtains the conditions of the internal tube f 20 of the furnace tube device 20 is used as the positioning film for the relevant information of the automation machine or for unloading. For general wafers, the following coatings are used: :: Solid coatings, such as silicon nitride (Si N) coatings. In the preferred embodiment, a wafer having the same backside plating as a general wafer can be used as the inspection wafer. For example, a blank wafer with the same thickness as the manufacturing wafer and a back surface with a thickness of 162; and a silicon nitride (SiN) coating is used as the inspection sheet. Then, step 30 6 is performed: the wafer boat 24 carrying the control sheet and the wafer is subjected to a high temperature treatment in the high temperature furnace tube 20. In the preferred embodiment, the high-temperature furnace tube is a vertical high-temperature furnace tube 20, and the wafer boat 24 is a vertical type for high-temperature processing. In an embodiment, a blank wafer die and a wafer with a silicon nitride (SiN) mineral layer with a thickness of 1625 Λ on the back are used as comparison sheets, and the wafers under the detection sheets are measured. The results of the shallow trench isolation layer are shown in Figure 4 and the first table. The first table is the control wafer. The thickness of the wafer is increased. It is a quasi deviation (STD)-a blank wafer die-3.71 1625A silicon ammonia (SiN) coated wafer-one " 2.90 0.30

519682 V. Description of the invention (6) In the fourth figure, it represents the wafer A and the thickness increase of the measured thickness of the separation layer. From the figure, the number on 0 is the shallow trench as the lower wafer A of the test piece. The circle on wafer A: the increase in the thickness of the wafer (13.65, 8 91, 5), uneven distribution, edge-like Value, it is clear that there is a shallow groove at the edge of the wafer. • The wafer B below the HI 7 can be seen as the uniformity of the control wafer.] Ding Yi can see the thickness of the entire wafer The distributions are all fairly uniform: (It can be seen from the top of the top of the middle that the back has a thickness of 1625 A of 22: the wafer is used as the inspection piece, and the shallow trench of the lower wafer is uniform, that is, the degree of predicate is uniform, and the wafer The thickness standard deviation (0.3) of the upper part is significantly smaller than that of a round die (3.71), which effectively avoids the problem of peeling off the shallow trench isolation layer. It will be carried in the wafer boat 24 and has the same back plating. When the prosecution sheet and the lower wafer are subjected to high temperature processing in the high temperature furnace tube 20, the back layer of the prosecution sheet is the same as that of other manufactured wafers. Therefore, the conditions on the back of the prosecution sheet are the same as those of other wafers. In tube 20, the micro-environmental conditions between adjacent prosecution pieces and wafers are the same as those of other wafers and between wafers. In order to greatly reduce the problem of peeling off the shallow trench isolation layer often occurring on the outer edge of the wafer under the inspection sheet, the advantage of the present invention is that the wafer boat is provided with inspection and control in the high-wave furnace tube in the most economical way. In the case of wafers, the problem of f-round shallow trench isolation layer peeling can be effectively improved. The invention can save the cost of purchasing additional inspection wafers and directly operate the same batch of wafers with the same backside plating directly.

519682 V. Description of Invention (7) It is used for prosecution film. In wafer manufacturing, in the same batch of wafers, the wafers with the same backside coating are quite easy to obtain. The economic benefits or the convenience of obtaining are better than purchasing additional control wafers, and can effectively improve the high-temperature process. The problem of wafer shallow trench isolation layer peeling. Although the present invention is disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

0503-7159TWf; TSMC2001-1002; Peggy.ptd page 10

Claims (1)

519682 6. Scope of patent application1. A method for avoiding the stripping of the shallow trench isolation layer of the wafer is applicable to a high temperature furnace tube. A high temperature furnace tube is provided with a wafer boat having a plurality of positions for carrying wafers. The method includes the following steps: : Loading at least one control sheet at at least a first position in the wafer boat; loading at least one wafer at at least a second position in the wafer boat, wherein the wafer has a shallow trench isolation structure, and the The back plating of the control wafer is the same as the back plating of the wafer; the wafer boat carrying the inspection wafer and the wafer is subjected to a high temperature treatment in the high temperature furnace tube. 2. The method for avoiding the stripping of the shallow trench isolation layer of the wafer according to item 1 of the scope of the patent application, wherein the backside plating of the controller and the backside plating of the wafer are silicon nitride (SiN). 3. The method for preventing stripping of the shallow trench isolation layer of the wafer according to item 2 of the scope of the patent application, wherein the control chip is a bare wafer with a silicon nitride (SiN) coating on the back. 4. The method for avoiding stripping of the shallow trench isolation layer of the wafer according to item 2 of the scope of the patent application, wherein the thickness of the silicon nitride (S i N) is 16 2 5 A. 5. The method for avoiding the stripping of the shallow trench isolation layer of the wafer according to item 1 of the scope of the patent application, wherein the wafer boat is arranged in the high temperature furnace tube in a vertical manner. A method for avoiding stripping of a shallow trench isolation layer of a wafer, in which at least one wafer is loaded into a position below the control piece. 0503-7159TWf; TSMC2001-1002; Peggy.ptd page 11