517335 五、發明說明（1) θ本發明係有關於一種應力釋放之圖案組合結構， ς有關於一種應力釋放之網狀圖案组合於密封式環圈的結 現今的半導體製程中，隨著元件尺寸縮小化的發 =鈥兩π件操作逮度的需求，具有低電阻常數和高電 =二屬，已逐漸被應用來作為金屬内連線的材Ϊ i可連線技術不僅可達到内連線的縮小化並 二3 =少％間延遲（RC delay)，同時也解決了銅金 ‘。的問題’因此已成為現今多重内連線主要的發展趨 所容、=電=二的發展下’在相同晶片面積 及超音波振盈，便=二=外在些微的應力 使0使付精么敏感的電路7〇件產生失效、 :或甚至造成積體電路基材龜裂或剝離 封式；nr問題，傳統上會在晶片四周圍 ί :為應力阻絕及達到防止水汽、雜質滲入= 、 圖所不，為習知技術中密封式環圈之上視圖 保件^切=12之内側，用來 阻絕的效果。纟第;Β°ηΐ4 ’做為應力、水汽及雜質 戴面示意圖，該密封習知技術中密封式環圈之橫 間是以介層洞插塞2。㈡為-堆叠式結構16 ’金屬層18 疋傳充的馆封式環圈還是有内應力過大的問題存 517335 五、發明說明（2) 在 p 對於外來的應力釋放效果還是無法達 ^ 且在隔絕水氣能力與整體堆疊結構強声A ^預設的結果 進。 愒5$度也需要再加強改 有鑑於此，為了解決上述問題，本發明主要 提供一種應力釋放之圖案組合結構，特別3 勺在於 力釋放之網狀圖案組合於密封式環圈的結g頁關於一種應 為獲致上述之目的，本發明提出一種 組合結構，設置於一半導體基底上， =力釋放之圖案 組合結構包括以下元件，一八邊形外侧密之圖案 第一堆疊式結構層，其中上述第—堆疊 ^:圈，為一 層第一金屬層和複數層之下層第一金屬屏、、、"3包括一上 一金屬層和上述複數層之下層第一金屬声 而上述上層第 數層之下層第-金屬層間包括至少二連c上述複 插塞；一八邊形内側密封式環圈，外要、、1又線形介層洞 環圈内部，為相對應於上述第一堆最 、c外側密封式 疊式結構層，其中上述第二堆疊式;層之一第二堆 金屬層和複數層之下層第二金屬層，°8匕括—上層第二 層和上述複數層之下層第二金屬^之上述上層第二金屬 τ層第二ΐ!層間包括至少-連i性複數層之 至少一不連續性之方形介層洞插夷形"層洞插塞和 ，設置於上述八邊形外側密封式^圈二角形網狀圖案結構 形網狀圖案結構，言免置於上述八邊开:個f角外園；多邊 頂角内圍，可以有效保護内部晶片^ 封式環圈四個 外來應力的破壞。 略設計元件區，避免 第6頁 〇503-6980Wf ： TSMC2001-0872 ； Jerry.ptd 517335 五、發明說明（3) 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖不說明： 第1 A圖係為習知技術中密封式環圈之上視圖。 第1 B圖係為習知技術中密封式環圈之橫截面示意圖。 第2 A圖係為本發明中密封式環圈之上視圖。 第2B圖係為本發明中密封式環圈之橫截面示意圖。 第3圖係為本發明中應力釋放之網狀圖案結構圖。 第4圖係為本發明中結合密封式環圈結構和應力釋放 之網狀圖案結構，而形成一種應力釋放之圖案組合結構示 意圖。 符號說明： 10〜方形密封式環圈； 12、24、64〜切割線； 14、22、62〜電路設計元件區； 1 6〜堆疊式結構； 1 8〜金屬層； 2 0〜介層洞插塞； 2 6〜外側密封式環圈； 2 8〜内側密封式環圈； 3 0〜第一堆疊式結構層； 32〜上層第一金屬層； 34〜複數層之下層第一金屬層； 3 6〜線形介層洞插塞； 3 8〜第二堆疊式結構層； 40〜上層第二金屬層； 42〜複數層之下層第二金屬層； 4 4〜方形介層洞插塞； 4 6〜第一方向銅金屬條；517335 V. Description of the invention (1) θ The present invention relates to a pattern combination structure of stress release, and a net pattern combination of stress release in a hermetically sealed ring structure in the current semiconductor manufacturing process. Reduced hair = "two-prong operation requirements, with low resistance constant and high electricity = two genus, has been gradually used as a material for metal interconnections. The reduction is reduced to 3 = less% RC delay, and copper-gold is also solved. The problem 'so it has become the main development trend of today's multiple interconnects, = the development of electricity = two' in the same chip area and ultrasonic vibration surplus, then = two = external slight stress to make 0 fine 70 sensitive parts of the circuit have failed, or even caused the integrated circuit substrate to crack or peel off; nr problem, traditionally will be around the wafer ί: to prevent stress and prevent water vapor and impurities from penetrating =, The figure does not show the inner side of the sealed ring in the conventional technology. The cut piece is cut to the inside of 12 to prevent the effect.纟 第; Β ° ηΐ4 ′ As a schematic diagram of the wearing surface of stress, water vapor and impurities, the sealing ring in the conventional sealing technology is a via hole plug 2. ㈡ 为 -stacked structure 16 'metal layer 18 疋 The filled-in museum-enclosed ring still has the problem of excessive internal stress 517335 V. Description of the invention (2) The external stress relief effect at p is still unachievable ^ and in The ability to isolate water and gas with the strong sound of the overall stacking structure A ^ preset results. In order to solve the above problems, the present invention mainly provides a pattern combination structure for stress release. In particular, three mesh spoon patterns for force release are combined in the sealing ring. In order to achieve the above-mentioned object, the present invention proposes a combined structure provided on a semiconductor substrate. The combined structure of a pattern of force release includes the following elements, a first stacked structure layer with a dense pattern on the outside of an octagon, wherein The first stack ^: circle is a layer of a first metal layer and a plurality of layers of a first metal screen below the first metal layer, and the "3" includes an upper metal layer and the first metal sound of the lower layer of the plurality of layers. The lower layer of the first layer-metal layer includes at least two of the above-mentioned multiple plugs; an octagonal inner sealed ring, the outer ring, the inner ring, and the linear interlayer hole ring correspond to the most of the first pile. , C outer sealed stack structure layer, in which the above-mentioned second stack type; one of the second stack of metal layers and a plurality of layers below the second metal layer, ° 8 dagger-the upper second layer and the above multiple layers The above-mentioned second upper metal layer of the lower second metal layer and the second upper layer of the second metal layer. The interlayer includes at least one discontinuity of at least one discontinuity in the square interlayer hole plugging " layer hole plug and The above-mentioned octagonal outer sealed ^ -circle pentagonal mesh pattern structure is a net-shaped pattern structure, which is free from the above-mentioned octagonal opening: an f-corner outer circle; a polygonal top corner inner periphery, which can effectively protect the inner chip ^ seal ring Circle the damage of four external stresses. Slightly design the component area, avoid page 6 503-6980Wf: TSMC2001-0872; Jerry.ptd 517335 V. Description of the invention (3) In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the following is specifically enumerated. The preferred embodiment and the accompanying drawings are described in detail as follows: Figures are not illustrated: Figure 1A is a top view of a sealed ring in the conventional technology. Figure 1B is a schematic cross-sectional view of a sealed ring in the conventional technology. Figure 2A is a top view of the sealed ring in the present invention. FIG. 2B is a schematic cross-sectional view of the sealed ring in the present invention. Fig. 3 is a structural diagram of a mesh pattern of stress release in the present invention. Fig. 4 is a schematic view showing the combination of a sealed ring structure and a stress-releasing pattern structure in the present invention to form a stress-releasing pattern combination structure. Explanation of symbols: 10 ~ square sealed ring; 12,24,64 ~ cutting line; 14,22,62 ~ circuit design element area; 16 ~ stacked structure; 18 ~ metal layer; 2 ~ via hole Plugs; 2 6 to outer sealed ring; 2 8 to inner sealed ring; 30 to first stacked structure layer; 32 to upper first metal layer; 34 to plural lower first metal layer; 3 6 ~ linear via plug; 3 8 ~ second stacked structure layer; 40 ~ upper second metal layer; 42 ~ plural layers below second metal layer; 4 4 ~ square via hole plug; 4 6 ~ first direction copper metal strip;
0503-6980TWf ； TSMC2001-0872 ； Jerry.ptd 第7頁 ϊ2方向銅金屬條；50〜方形區域，· "層洞銅金屬插栓； 八邊形外側密封式環圈； 八邊形内側密封式環圈； 三角形網狀圖案結構； 多邊形網狀圖案結構。 於-半ί 5 ί ί明’’先提出一種密封式環圈結構，設置 封式環ίΐίΐ ’上述密封式環圈結構包括：-外側密 圈以及一内側密封式環圈。 外側為本發明之密封式環圈之上視圖，- if冰~上述内側岔封式環圈28的寬产Μ焱I度約為 圖 如第2Β圖所示，為本發明之 ' :、 一外側密封式環圈26， 一f式J展圈之橫截面示音 中上述第一堆疊式結構層一堆®式結構層3〇，|0503-6980TWf; TSMC2001-0872; Jerry.ptd Page 7ϊ2 direction copper metal strip; 50 ~ square area, " layer hole copper metal plug; octagonal outer sealing ring; octagonal inner sealing Loops; triangle mesh pattern structure; polygon mesh pattern structure. Yu-Hain 5 ί Ming ’’ first proposed a sealed ring structure, which is provided with a sealed ring. The above sealed ring structure includes:-an outer ring and an inner ring. The outer side is a top view of the sealed ring of the present invention. -If ice ~ The wide production M 焱 I degree of the above inner branch sealed ring 28 is approximately as shown in Figure 2B. The above-mentioned first stacked structure layer in the cross section of the outer seal ring 26, an F-type J-show ring, and a stack of ®-type structure layers 30, |
Lti:層第一金屬層34，而上：上：ϊ 一ί屬層32和複 ，數層之下層第-金屬層34之間以』 金屬層以和上 第一金屬層34間包括至少一 上述複數層之ίγθ： 而上述上層第-金屬⑽與=;=介層洞插2層 胃之下層第-金屬層 517335 五、發明說明（5) 34之間是以一連 約為0 · 3 6微米， 一連續性之介層 插塞44所連結， 複數層之下層第 上述不連續性之 層第一金屬層34 3 4内之連續性之 洞插塞44其寬度 一内側密封 内部，為相對應 式結構層3 8，其 二金屬層4 0和複 二金屬層40和上 述複數層之下層 介層洞插塞3 6和 述上層第二金屬 間是以兩條連續 之方形介層洞插 插塞3 6是位於上 第二金屬層42之 塞36和上述不連 3 6微米’上述複 性之線形介層洞 續性之線形介 在上述複數層 洞插塞36和至 且上述連續性 —金屬層34的 方形介層洞插 的内端，在上 線形介層洞插 皆約為〇· 19微 式環圈28，設 於上述第一堆 中上述第二堆 數層之下層第 述複數層之下 層洞插基3 6所連結，且寬度 層34間是以 方形介層洞 是位於上述 準而成，而 複數層之下 之下層第一金屬 少一不 第二金 至少一 層40與 性之線 塞4 4所 述上層 間的兩 續性之 數層之 插塞36 屬層42 不連續 上述複 形介層 連結， 第二金 端5而 方形介 下層第 和至少 之介層 外端， 塞44則 述複數 塞3 6和 米V 置於上 疊式結 叠式結 二金屬 層第二 間包括 性之方 數層之 連續性之 洞插塞36 且上下對 位於上述 層之下層 不連續性 述外側密 構層3 0之 構層38包 層42，而 金屬層42 至少一連 形介層洞 下層第二 洞插塞3 6和至少 且上述連續性之 屬層40與上述複 上述連續性之線 層洞插塞44其寬 一金屬層4 2間是 一不連續性之方 第一金屬層 之方形介層 封式環圈2 6 一第二堆疊 括一上層第 上述上層第 之間以及上 續性之線形 插塞44，上 金屬層42之 ~不連續性 線形介層洞 數層之下層 形介層洞插 度皆約為0. 以兩條連續 形介層洞插Lti: layer first metal layer 34, and upper: upper: a metal layer 32 and a plurality of layers, between the first layer of the lower metal layer 34 and the metal layer 34 and the upper first metal layer 34 includes at least one Γθ of the above plural layers: and the above-mentioned first metal-metal and =; = interstitial hole insertion 2 layers below the gastric-first metal layer 517335 V. Description of the invention (5) 34 is a series of approximately 0 · 3 6 Micron, a continuous interposer plug 44 is connected, a plurality of lower layers, the above-mentioned discontinuity layer, the first metal layer 34 3 4 of the continuous hole plug 44 has a width, an inner side sealed inside, and a phase Corresponding structural layer 38, the two metal layers 40 and the multiple metal layers 40 and the above-mentioned lower interlayer via plug 36 and the upper second metal are inserted by two continuous square vias. The plug 36 is the plug 36 located on the upper second metal layer 42 and the above-mentioned non-connected 36 micrometers. The inner end of the square interposer hole insertion of the metal layer 34 in the upper linear interposer hole insertion is approximately 0.19 micro ring 2 8. It is located in the first pile above the second pile, the lower layer of the plurality of layers, and the lower layer of the plurality of layers of the hole inserting bases 36 are connected, and the width layer 34 is formed by the square interlayer holes located above, and The lower layer of the plurality of layers is the first metal less than one, the second gold is at least one layer 40 and the plug of sexual lines 4 4 the plug of the two layers of continuity between the upper layers 36 the layer 42 the discontinuous complex interlayer Connection, the second gold end 5 and the square lower intermediary first and at least the outer end of the interposer, the plug 44 describes the plural plug 36 and the meter V are placed on the upper layer of the stacked metal structure of the second metal layer Several layers of continuity hole plugs 36 are located above and below the above-mentioned layer discontinuity. The structure layer 38 cladding layer 42 of the outer dense layer 30 and the metal layer 42 have at least one continuous via hole. The plug 36 and at least the above-mentioned continuity of the layer 40 and the above-mentioned continuity line layer hole plug 44 have a width of one metal layer 4 and a square interposer of a discontinuous first metal layer. Enclosed ring 2 6 a second stack including an upper layer above the upper layer and Linear continuity of the plug 44, the lower number of layers ~ 42 linear discontinuities via hole formed on the metal layer via hole are inserted approximately 0.5 degrees in two consecutive shape interpolation vias
〇503-6980Tl/f ； TSMC2001-0872 ； Jerry.ptd 第9頁 517335 五、發明說明（6) 4 =連結’且上述連續性之線形介層洞插塞％是位於上 述=數層之:層第二金屬層42間的㈣，且上下對準而成 ^述連續性之線形介層洞插塞％和上述不連續性之方 ‘二：：插塞44其寬度皆約為〇.19微米，其中上述第-金 屬層和^二金屬層之材質皆為一銅金屬層。 f著在本發明中，再提出一種用於應力釋放之網狀圖 ^ °I °又置於一半導體基底上，上述應力釋放之圖案結 匕有，如第3圖所示，一銅金屬陣列區（未示於圖中 由複數平行於第一方向銅金屬條4 6和複數平行於第二 方向銅金屬條48所交錯形成，其中上述第一方向大體垂直 於上述第二方肖。複數之方形鑲嵌區（未示於圖中），由 上述平行於第$向銅金屬條46和上述平行於第二方向銅 金屬條48所交錯圍繞而成的複數方形區域5()，並於上述方 ，區域50内鎮嵌填滿低介電氧化物。複數之介層洞銅金屬 插栓52 i形成於上述平行於第—方向銅金屬侧和上述平 仃於第一方向銅金屬條48所交錯的接點處。 、、、口 a上述在封式環圈結構和上述應力釋放之網狀圖案 結構，而形成-種應力釋放之圖案組合結構，言免置於一半 導體基底Ji ’上述應力釋放之圖案組合結構包括有，如第 4圖所示，-八邊形外側密封式環圈54、一八邊形内側密 封式環圈56 ;三角形網狀圖案結構58以及 之内側:上述八邊形内側密封式環圈56，設置於上^外側 密封式ί衣圈54内部。上述三角形網狀圖案結構，設置於〇503-6980Tl / f; TSMC2001-0872; Jerry.ptd Page 9 517335 V. Description of the invention (6) 4 = connection 'and the continuity of the above-mentioned continuous linear via hole plug% is located in the above = several layers: layer ㈣ between the second metal layers 42 and aligned up and down ^ The continuity of the linear interposer hole plug% and the above discontinuity are two: the plug 44 has a width of about 0.19 microns The material of the first metal layer and the second metal layer is a copper metal layer. f. In the present invention, a mesh pattern for stress relief is proposed, and it is placed on a semiconductor substrate. The pattern of the stress relief is as shown in FIG. 3, which is a copper metal array. The area (not shown in the figure) is formed by a plurality of copper metal strips 46 parallel to the first direction and a plurality of copper metal strips 48 parallel to the second direction. The first direction is substantially perpendicular to the second square. The square mosaic area (not shown in the figure) is a plurality of square areas 5 () formed by the above-mentioned copper metal strips 46 parallel to the $ direction and the copper metal strips 48 parallel to the second direction. The area 50 is filled with low-dielectric oxide. A plurality of interposer copper metal plugs 52 i are formed on the copper metal side parallel to the first direction and the copper metal strip 48 intersected by the first direction copper metal strips. The contact points of the above, the above-mentioned closed ring structure and the above-mentioned stress-releasing mesh pattern structure form a pattern combination structure of stress-releasing, which can be placed on a semiconductor substrate Ji 'the above-mentioned stress-releasing The pattern combination structure includes As shown in Figure 4,-octagonal outer seal ring 54, one octagonal inner seal ring 56; triangular mesh pattern structure 58 and the inside: the octagonal inner seal ring 56, It is set inside the upper sealed outer garment ring 54. The above triangular mesh pattern structure is set in
517335 五、發明說明（7) 上述八邊形 形網狀圖案 四個頂角内 放之網狀圖 部晶片電路 有效率釋放 構強度有顯 本發明 本發明的範 精神和範圍 保護範圍當 外側密封 結構60， 圍，此結 案結構的 設計元件 外來的應 著的進步 雖以較佳 圍，任何 内，當可 視後附之 式環圈5 4的四個頂角外圍 設置於上述八邊形内側密 合上述密封式環圈結構和 應力釋放圖案組合’可以 區6 2，減少内應力過大的 力，且在隔絕水氣能力與 〇 實施例揭露如上，然其並 熟習此項技藝者，在不脫 做些許的更動與潤飾，因 申請專利m圍所卩定者為 °上述多邊 封式環圈5 6 上述應力釋 有效保護内 問題存在， 整體堆疊結 非用以限定; 離本發明之 此本發明之 準。517335 V. Description of the invention (7) The above-mentioned octagonal mesh pattern The four-corner corners of the mesh pattern portion of the wafer circuit effectively release the structural strength, which shows the spirit and scope of the present invention. Structure 60. The design elements of the closed structure should be improved from the outside. However, when seen inside, the four apex corners of the ring 5 4 are arranged on the inside of the octagon. In combination with the above-mentioned sealed ring structure and stress relief pattern combination, it is possible to reduce the force of excessive internal stress, and the ability to isolate water and gas is disclosed as above. However, those skilled in the art are familiar with this technology. Make a few changes and retouching, because the patent application m is determined by ° the above-mentioned multi-sided seal ring 5 6 the above stress relief effective protection problems exist, the overall stacking knot is not used to limit; from the present invention of this invention Standard.