CN1438696A - Pattern combination stucture of releasing stress force - Google Patents
Pattern combination stucture of releasing stress force Download PDFInfo
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- CN1438696A CN1438696A CN 02105012 CN02105012A CN1438696A CN 1438696 A CN1438696 A CN 1438696A CN 02105012 CN02105012 CN 02105012 CN 02105012 A CN02105012 A CN 02105012A CN 1438696 A CN1438696 A CN 1438696A
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- interlayer hole
- stress release
- hole connector
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Abstract
The combined structures comprises the sealed type annular ring structure and the pattern structure for releasing stress setup at the semiconductor substrate. The sealed type annular ring structure comprises the outside annular ring and the inside annular ring. The pattern structure for releasing stress comprises the triangular meshy pattern structure located at peripheries of the four apex angles of the outside annular ring as well as the polygonal meshy pattern structure located at inside of the four apex angles of the inside annular ring. The meshy pattern structure is the metal bar assembled area. The invention reduces internal stresses as well as isolates water vapor and impurity effectively so as to protect the chips inside.
Description
Technical field
The present invention relates to a kind of combinations of patterns structure of Stress Release, be used for the integrated circuit (IC) chip protection, particularly be combined in the structure of sealed type ring about a kind of net-like pattern of Stress Release.
Background technology
In the semiconductor manufacturing process now, along with the downsizing of size of components and the raising of assembly operation speed, have the copper metal of low resistance constant and high electron mobility impedance, be used to material gradually, replace aluminum metal manufacturing process flow in the past as metal interconnecting.Wherein cooperate inserted (damascene) intraconnections technology of copper metal that the intraconnections size is dwindled and also can reduce time of delay (RC delay), also solve simultaneously the problem that the copper metal etch is difficult for, therefore become multiple internal connecting lines main development tendency now.
Yet, development along with the size of components downsizing, the quantity of the identical circuit unit that chip area held increases rapidly, therefore, the vibration of external small stress or ultrasonic waves all can make accurate responsive circuit unit produce inefficacy, short circuit even causes the be full of cracks of integrated circuit base material or peel off.
In order to address the above problem; in the conventional art; once around chip, put a sealed type ring; with isolated stress and prevent the infiltration of steam, impurity, as Figure 1-1, be the vertical view of sealed type ring in the known techniques; it is a square sealed secondery ring 10; be centered around the inboard of line of cut 12,, and reach effect with stress, steam and isolated from contaminants with protection inside chip circuit design assembly district 14.Fig. 1-2 is the cross sectional representation of sealed type ring in the known techniques, and sealing formula ring is a nesting structural embedded control 16, is connected with interlayer hole connector 20 between the metal level 18.
But still there is the excessive problem of internal stress in traditional sealed type ring, also can't reach the result of predetermined design for external Stress Release effect, and in isolated aqueous vapor ability and the improvement also to be strengthened of whole stack architecture intensity.
Summary of the invention
Master's of the present invention purpose is to provide a kind of combinations of patterns structure of Stress Release, particularly is combined in the structure of sealed type ring about a kind of net-like pattern of Stress Release.It can reduce internal stress effectively, isolated aqueous vapor and impurity, protection inside chip.
For achieving the above object, the present invention proposes a kind of combinations of patterns structure of Stress Release, be used for the integrated circuit (IC) chip protection, it comprises a sealed type ring, characteristics are, sealing formula ring contains an outside sealed type ring and and is arranged at the inner inner seal formula of this outside sealed type ring ring, constitutes a sealed type toroidal ring structure; Also have the net-like pattern structure of a Stress Release to match with sealing formula toroidal ring structure, they are arranged on the semiconductor substrate jointly.
Said outside sealed type ring is one first nesting structural embedded control layer, this first nesting structural embedded control layer comprises lower floor's the first metal layer of a upper strata the first metal layer and several layers, and comprises at least one successional linear interlayer hole connector between this upper strata the first metal layer and this several layers lower floor the first metal layer and between this several layers lower floor the first metal layer;
Said inner seal formula ring, for corresponding to one second nesting structural embedded control layer of this first nesting structural embedded control layer, wherein this second nesting structural embedded control layer comprises a upper strata second metal level and several layers lower floor second metal level, and between lower floor's second metal level of this upper strata second metal level and this several layers and lower floor's second metal interlevel of this several layers comprise the square interlayer hole connector of at least one successional linear interlayer hole connector and at least one discontinuity;
The width of outside sealed type ring is about 1.1 microns; The width of inner seal formula ring is about 6.0 microns; The spacing of outside sealed type ring and described inner seal formula ring is about 2.5 microns; The material of the first metal layer and second metal level is all copper; Linked with a successional linear interlayer hole connector, and width is about 0.36 micron.
Be that square interlayer hole connector with a successional interlayer hole connector and at least one discontinuity is linked between said several layers lower floor the first metal layer, and this successional interlayer hole connector is positioned at the outer end of this several layers lower floor the first metal layer, and aim at up and down and form, the square interlayer hole connector of this discontinuity then is positioned at the inner of lower floor's the first metal layer of this several layers, and square its width of interlayer hole connector of this successional linear interlayer hole connector and this discontinuity all is about 0.19 micron.
Be that square interlayer hole connector with two successional linear interlayer hole connectors and at least one discontinuity is linked between said upper strata second metal level and above-mentioned several layers lower floor second metal level, and this successional linear interlayer hole connector is the two ends between this upper strata second metal level and this several layers lower floor second metal level, and the square interlayer hole connector of this successional linear interlayer hole connector and this discontinuity, its width all is about 0.36 micron.
Said several layers lower floor second metal interlevel is that the square interlayer hole connector with two successional linear interlayer hole connectors and at least one discontinuity is linked, and this successional linear interlayer hole connector is the two ends that are positioned at this several layers lower floor second metal interlevel, and aligning forms up and down, and square its width of interlayer hole connector of this successional linear interlayer hole connector and this discontinuity all is about 0.19 micron.
Said outside sealed type ring becomes octagon with inner seal formula ring.
The net-like pattern structure of said Stress Release comprises: the netted patterning of a triangle is arranged at this four drift angle peripheries of outside sealed type ring; One polygon net-like pattern structure is arranged in four drift angles of this inner seal formula ring and encloses.
The net-like pattern structure of said Stress Release, its net-like pattern structure are a bonding jumper assembly district, are parallel to the first direction bonding jumper and some second direction bonding jumpers that is parallel to are staggered to form by some, and wherein this first direction is substantially perpendicular to this second direction; Some square mosaic areas are parallel to first direction bonding jumper and this by this and are parallel to the second direction bonding jumper and are interlocked and center on the some square region that form, and inlay in this square region and fill up a dielectric materials; Some interlayer hole metal plugs are formed at this and are parallel to first direction bonding jumper and this and are parallel to the contact place that the second direction bonding jumper is interlocked.
Above-mentioned square mosaic area is foursquare mosaic area, and each length of side is about 1.5 microns; In the net-like pattern structure of Stress Release, the material of bonding jumper is for being copper; Low dielectric material is an oxide.
By the present invention, inside chip circuit design assembly district can be effectively protected, and excessive internal stress can be effectively reduced, discharge external stress, and can effectively completely cut off aqueous vapor and impurity, its whole stack architecture intensity also increases significantly.
Description of drawings
Fig. 1-1 is the vertical view of sealed type ring in the known techniques.
Fig. 1-2 is the cross sectional representation of sealed type ring in the known techniques.
Fig. 2-1 is the vertical view of sealed type ring among the present invention.
Fig. 2-2 is the cross sectional representation of sealed type ring among the present invention.
Fig. 3 is the net-like pattern structural representation of Stress Release among the present invention.
Fig. 4 is the combinations of patterns structural representation of Stress Release of the present invention.
Embodiment
For purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
At first in the present invention, propose a kind of sealed type toroidal ring structure, it is arranged on the semiconductor substrate, and sealing formula toroidal ring structure comprises: an outside sealed type ring and an inner seal formula ring.
Shown in Fig. 2-1; vertical view for sealed type ring of the present invention; one outside sealed type ring 26 and an inner seal formula ring 28; be centered around the inboard of line of cut 24; be used for protecting chip internal circuit design assembly district 22, as the isolated effect of stress, the width of this outside sealed type ring 26 is about 1.1 microns; the width of this inner seal formula ring 28 is about 6.0 microns, and outside sealed type ring 26 is about 2.5 microns with the spacing of inner seal formula ring 28.
Shown in Fig. 2-2, cross sectional representation for sealed type ring of the present invention, one outside sealed type ring 26, it is one first nesting structural embedded control layer 30, this first nesting structural embedded control layer 30 comprises a upper strata the first metal layer 32 and several layers lower floor the first metal layer 34, and between lower floor's the first metal layer 34 of this upper strata the first metal layer 32 and this several layers and 34 of lower floor's the first metal layers of this several layers comprise at least one successional linear interlayer hole connector 36, and linked with a successional linear interlayer hole connector 36, and width is about 0.36 micron, at 34 of lower floor's the first metal layers of above-mentioned several layers is that square interlayer hole connector 44 with a successional interlayer hole connector 36 and at least one discontinuity is linked, and above-mentioned successional interlayer hole connector 36 is positioned at the outer end of above-mentioned several layers lower floor the first metal layer 34, and aim at up and down and form, the square interlayer hole connector 44 of above-mentioned discontinuity then is positioned at the inner of lower floor's the first metal layer 34 of above-mentioned several layers, and square interlayer hole connector 44 its width of successional linear interlayer hole connector 36 in lower floor's the first metal layer 34 of above-mentioned several layers and discontinuity all are about 0.19 micron.
One inner seal formula ring 28, be arranged at sealed type ring 26 inside, the above-mentioned outside, for corresponding to one second nesting structural embedded control layer 38 of the above-mentioned first nesting structural embedded control layer 30, this second nesting structural embedded control layer 38 comprises a upper strata second metal level 40 and several layers lower floor second metal level 42, and between lower floor's second metal level 42 of above-mentioned upper strata second metal level 40 and above-mentioned several layers and 42 of lower floor's second metal levels of above-mentioned several layers comprise the square interlayer hole connector 44 of at least one successional linear interlayer hole connector 36 and at least one discontinuity, be that square interlayer hole connector 44 with two successional linear interlayer hole connectors 36 and at least one discontinuity is linked between above-mentioned upper strata second metal level 40 and above-mentioned several layers lower floor second metal level 42, and the two ends of above-mentioned successional linear interlayer hole connector 36 between lower floor's second metal level 42 of above-mentioned upper strata second metal level 40 and above-mentioned several layers, and square interlayer hole connector 44 its width of above-mentioned successional linear interlayer hole connector 36 and above-mentioned discontinuity all are about 0.36 micron, 42 of lower floor's second metal levels of above-mentioned several layers are that the square interlayer hole connector 44 with two successional linear interlayer hole connectors 36 and at least one discontinuity is linked, and above-mentioned successional linear interlayer hole connector 36 is the two ends that are positioned at 42 of lower floor's second metal levels of above-mentioned several layers, and aim at up and down and form, and the square interlayer hole connector 44 of above-mentioned successional linear interlayer hole connector 36 and above-mentioned discontinuity, its width all is about 0.19 micron, and the material of the wherein above-mentioned the first metal layer and second metal level is all copper.
Then in the present invention, reintroduce a kind of net-like pattern structure that is used for Stress Release, be arranged on the semiconductor substrate, the patterning of above-mentioned Stress Release includes, as shown in Figure 3, one bronze medal bonding jumper assembly district (not being shown among the figure) is staggered to form by some copper bonding jumper 46 and some copper bonding jumpers 48 that are parallel to second direction that are parallel to first direction, and wherein above-mentioned first direction is substantially perpendicular to above-mentioned second direction.Some square mosaic areas (not being shown among the figure), be parallel to first direction copper bonding jumper 46 and the above-mentioned second direction copper bonding jumper 48 that is parallel to is interlocked around some square region 50 of forming by above-mentioned, and in above-mentioned square region 50, inlay and fill up low dielectric oxide.Some interlayer hole copper metal plugs 52 are formed at and above-mentionedly are parallel to first direction copper bonding jumper 46 and above-mentionedly are parallel to the contact place that second direction copper bonding jumper 48 is interlocked.
Net-like pattern structure in conjunction with above-mentioned sealed type toroidal ring structure and above-mentioned Stress Release, and form a kind of combinations of patterns structure of Stress Release, be arranged on the semiconductor substrate, the combinations of patterns structure of above-mentioned Stress Release includes, as shown in Figure 4, octagon outside sealed type ring 54, an octagon inner seal formula ring 56, the netted patterning 58 of triangle and polygon net-like pattern structure 60.Above-mentioned octagon outside sealed type ring 54 is arranged at the inboard of line of cut 64.Above-mentioned octagon inner seal formula ring 56 is arranged at sealed type ring 54 inside, the above-mentioned outside.The netted patterning 58 of above-mentioned triangle is arranged at four drift angle peripheries of above-mentioned octagon outside sealed type ring 54.Above-mentioned polygon net-like pattern structure 60; be arranged in 56 4 drift angles of above-mentioned octagon inner seal formula ring and enclose; the Stress Release combinations of patterns of this net-like pattern structure in conjunction with above-mentioned sealed type toroidal ring structure and above-mentioned Stress Release; can effectively protect inside chip circuit design assembly district 62; reduce the excessive problem of internal stress; effectively discharge external stress, and can effectively completely cut off aqueous vapor, its whole stack architecture intensity also increases significantly.
Though the present invention discloses as above with preferred embodiment; but it is not to be used for limiting scope of the present invention; any those who familiarize themselves with the technology; without departing from the spirit and scope of the present invention; change and retouching when doing some, so the scope that claims defined that protection scope of the present invention should be looked present patent application is as the criterion.
Claims (16)
1. the combinations of patterns structure of a Stress Release, be used for the integrated circuit (IC) chip protection, it comprises a sealed type ring, it is characterized in that, sealing formula ring contains an outside sealed type ring and and is arranged at the inner inner seal formula of this outside sealed type ring ring, constitutes a sealed type toroidal ring structure; Also have the net-like pattern structure of a Stress Release to match with sealing formula toroidal ring structure, they are arranged on the semiconductor substrate jointly.
2. the combinations of patterns structure of Stress Release as claimed in claim 1 is characterized in that,
Described outside sealed type ring is one first nesting structural embedded control layer, this first nesting structural embedded control layer comprises lower floor's the first metal layer of a upper strata the first metal layer and several layers, and comprises at least one successional linear interlayer hole connector between this upper strata the first metal layer and this several layers lower floor the first metal layer and between this several layers lower floor the first metal layer;
Described inner seal formula ring, for corresponding to one second nesting structural embedded control layer of this first nesting structural embedded control layer, wherein this second nesting structural embedded control layer comprises a upper strata second metal level and several layers lower floor second metal level, and between lower floor's second metal level of this upper strata second metal level and this several layers and lower floor's second metal interlevel of this several layers comprise the square interlayer hole connector of at least one successional linear interlayer hole connector and at least one discontinuity.
3. the combinations of patterns structure of Stress Release as claimed in claim 1 or 2 is characterized in that, the width of described outside sealed type ring is about 1.1 microns.
4. the combinations of patterns structure of Stress Release as claimed in claim 1 or 2 is characterized in that, the width of described inner seal formula ring is about 6.0 microns.
5. the combinations of patterns structure of Stress Release as claimed in claim 1 or 2 is characterized in that, the spacing of described outside sealed type ring and described inner seal formula ring is about 2.5 microns.
6. the combinations of patterns structure of Stress Release as claimed in claim 2 is characterized in that, the material of the described the first metal layer and second metal level is all copper metal layer.
7. the combinations of patterns structure of Stress Release as claimed in claim 2 is characterized in that, linked with a successional linear interlayer hole connector between described upper strata the first metal layer and the described several layers lower floor the first metal layer, and width is about 0.36 micron.
8. the combinations of patterns structure of Stress Release as claimed in claim 2, it is characterized in that, be that square interlayer hole connector with a successional interlayer hole connector and at least one discontinuity is linked between described several layers lower floor the first metal layer, and this successional interlayer hole connector is positioned at the outer end of this several layers lower floor the first metal layer, and aim at up and down and form, the square interlayer hole connector of this discontinuity then is positioned at the inner of this several layers lower floor the first metal layer, and square its width of interlayer hole connector of this successional linear interlayer hole connector and this discontinuity all is about 0.19 micron.
9. the combinations of patterns structure of Stress Release as claimed in claim 1, it is characterized in that, be that square interlayer hole connector with two successional linear interlayer hole connectors and at least one discontinuity is linked between described upper strata second metal level and described several layers lower floor second metal level, and this successional linear interlayer hole connector is the two ends between this upper strata second metal level and this several layers lower floor second metal level, and the square interlayer hole connector of this successional linear interlayer hole connector and this discontinuity, its width all is about 0.36 micron.
10. the combinations of patterns structure of Stress Release as claimed in claim 2, it is characterized in that, described several layers lower floor second metal interlevel is that the square interlayer hole connector with two successional linear interlayer hole connectors and at least one discontinuity is linked, and this successional linear interlayer hole connector is the two ends that are positioned at lower floor's second metal interlevel of this several layers, and aligning forms up and down, and square its width of interlayer hole connector of this successional linear interlayer hole connector and this discontinuity all is about 0.19 micron.
11. the combinations of patterns structure of Stress Release as claimed in claim 1 is characterized in that, described outside sealed type ring becomes octagon with inner seal formula ring.
12. the combinations of patterns structure of Stress Release as claimed in claim 11 is characterized in that, the net-like pattern structure of described Stress Release comprises: the netted patterning of a triangle is arranged at this four drift angle peripheries of outside sealed type ring; One polygon net-like pattern structure is arranged in four drift angles of this inner seal formula ring and encloses.
13. combinations of patterns structure as claim 1 or 12 described Stress Release, it is characterized in that, the net-like pattern structure of described Stress Release, its net-like pattern structure is a bonding jumper assembly district, be parallel to the first direction bonding jumper and some second direction bonding jumpers that is parallel to are staggered to form by some, wherein this first direction is substantially perpendicular to this second direction; Some square mosaic areas are parallel to first direction bonding jumper and this by this and are parallel to the second direction bonding jumper and are interlocked and center on the some square region that form, and inlay in this square region and fill up a dielectric materials; Some interlayer hole metal plugs are formed at this and are parallel to first direction bonding jumper and this and are parallel to the contact place that the second direction bonding jumper is interlocked.
14. the combinations of patterns structure of Stress Release as claimed in claim 13 is characterized in that, described square mosaic area is foursquare mosaic area, and each length of side is about 1.5 microns.
15. the combinations of patterns structure of Stress Release as claimed in claim 13 is characterized in that, in the net-like pattern structure of described Stress Release, the material of bonding jumper is a copper.
16. the combinations of patterns structure of Stress Release as claimed in claim 13 is characterized in that, described dielectric materials is an oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105012 CN1212661C (en) | 2002-02-10 | 2002-02-10 | Pattern combination stucture of releasing stress force |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105012 CN1212661C (en) | 2002-02-10 | 2002-02-10 | Pattern combination stucture of releasing stress force |
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| CN1438696A true CN1438696A (en) | 2003-08-27 |
| CN1212661C CN1212661C (en) | 2005-07-27 |
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| CN 02105012 Expired - Lifetime CN1212661C (en) | 2002-02-10 | 2002-02-10 | Pattern combination stucture of releasing stress force |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438033C (en) * | 2005-10-11 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip and packaging and electronic installation comprising same |
| CN101047165B (en) * | 2006-03-29 | 2011-07-13 | 旺宏电子股份有限公司 | Overlay mark arrangement for reducing overlay shift |
| CN102983413A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN102983412A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN102983414A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN102983410A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array face and reflective array antenna |
| CN103378030A (en) * | 2012-04-18 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon-via structure |
| CN103579199A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Double seal ring |
| WO2014071866A1 (en) * | 2012-11-09 | 2014-05-15 | 深圳光启创新技术有限公司 | Reflective array surface and reflective array antenna |
| CN111446216A (en) * | 2019-01-16 | 2020-07-24 | 矽品精密工业股份有限公司 | Electronic package, manufacturing method thereof and substrate for packaging |
Families Citing this family (1)
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| KR20220020716A (en) | 2020-08-12 | 2022-02-21 | 삼성전자주식회사 | Interconnect structure and semiconductor chip including the same |
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2002
- 2002-02-10 CN CN 02105012 patent/CN1212661C/en not_active Expired - Lifetime
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438033C (en) * | 2005-10-11 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip and packaging and electronic installation comprising same |
| CN101047165B (en) * | 2006-03-29 | 2011-07-13 | 旺宏电子股份有限公司 | Overlay mark arrangement for reducing overlay shift |
| CN103378030A (en) * | 2012-04-18 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon-via structure |
| CN103378030B (en) * | 2012-04-18 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via structure |
| CN103579199B (en) * | 2012-07-31 | 2017-05-10 | 台湾积体电路制造股份有限公司 | Double seal ring |
| CN103579199A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Double seal ring |
| CN102983414A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN102983410A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array face and reflective array antenna |
| CN102983410B (en) * | 2012-11-09 | 2014-03-12 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN102983414B (en) * | 2012-11-09 | 2014-04-16 | 深圳光启创新技术有限公司 | Reflective plane of reflective array antenna |
| CN102983413B (en) * | 2012-11-09 | 2014-04-16 | 深圳光启创新技术有限公司 | Reflective plane of reflective array antenna |
| WO2014071866A1 (en) * | 2012-11-09 | 2014-05-15 | 深圳光启创新技术有限公司 | Reflective array surface and reflective array antenna |
| CN102983412A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| US9583839B2 (en) | 2012-11-09 | 2017-02-28 | Kuang-Chi Innovative Technology Ltd. | Reflective array surface and reflective array antenna |
| CN102983413A (en) * | 2012-11-09 | 2013-03-20 | 深圳光启创新技术有限公司 | Reflective array antenna |
| CN111446216A (en) * | 2019-01-16 | 2020-07-24 | 矽品精密工业股份有限公司 | Electronic package, manufacturing method thereof and substrate for packaging |
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| CN1212661C (en) | 2005-07-27 |
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Granted publication date: 20050727 |