TW516230B

TW516230B - Method of forming heterojunction bipolar transistor

Info

Publication number: TW516230B
Application number: TW90102495A
Authority: TW
Inventors: Jr-Jeng Liou; De-Yuan Wu
Original assignee: United Microelectronics Corp
Priority date: 2001-02-06
Filing date: 2001-02-06
Publication date: 2003-01-01

Abstract

A method of forming heterojunction bipolar transistor is disclosed. An insulation layer and a patterned silicon layer are formed on a silicon substrate. An oxide layer, an adhesion layer and an in-situ boron-doped polysilicon layer are successively formed on the insulation layer. A patterned oxide layer is again formed on the insulation layer to expose the adhesion layer and form an emitter window. The adhesion layer and the oxide layer in the emitter window and on the silicon layer are then removed. A SiGe layer is formed on the silicon layer and a spacer is formed on the sidewalls of the patterned oxide layer and on the SiGe layer. Finally, an in-situ phosphorous-doped polysilicon layer is formed on the silicon substrate as an emitter. Additionally, an insulation layer, a silicon layer, and a passivation layer are formed on a silicon substrate. The passivation layer and the silicon layer are then defined and a first spacer is formed on the sidewalls of the passivation layer and silicon layer. Next, an in-situ boron-doped polysilicon layer is formed on the insulation layer and a patterned oxide layer is formed on the polysilicon layer to expose the passivation layer and form an emitter window. After that, the passivation layer and the first spacer are removed and a SiGe layer is formed on the silicon substrate. A second spacer is formed on the sidewalls of the patterned oxide layer and on the SiGe layer. Finally, an in-situ phosphorous-doped polysilicon layer is formed on the silicon substrate as an emitter.

Description

經濟部智慧財產局員工消費合作社印製 516230 6978twf.doc/006 pj B7 五、發明說明（ί) 本發明是有關一種形成雙載子電晶體的方法，特別是有關於一種形成異質接合雙載子電晶體（Heterojunctnon Bipolar Transistor)的方法。雙載子連接電晶體（Bipolar Junction Transistor，簡稱 BJT)是一種同時利用電子和電洞（Hole)這兩種載子 (Carnes)來傳導電流的電子元件。B〗T的優點是處理速度快，通常用於高電件（High Power Devices)或是需要高速的邏輯電路。B〗T的結構是由兩個緊密的pn連接 (Junction)所組成的三接點（Three Terminal)元件。這二個接點分別稱爲射極（Emitter )、基極（Base )與集極 (Colkctor)。而異質接合雙載子電晶體是指利用異質接合形成的雙載子電晶體，其中「異質接合」是指利用兩種不同材料互相接合的技術。第1A圖至第1B圖是習知一種異質接合雙載子電晶體之製作流程剖面示意圖。請參照第1A圖，於矽基底100上依序形成一氧化層 103、一層摻雜硼多晶砍（in-Situ Boron-Doped Poly-Si， IBDP)層102與一層氧化矽層104，然後圖案化此IBDP 層102與一層氧化矽層1〇4，以形成一射極窗開口 1〇6暴露出矽基底100。由於直接於矽基底上形成異質接合雙載子電晶體，故射極、基極與集極藉由矽基底會產生較大的寄生電容。接著，請參照第1B圖，利用磊晶成長（Epitaxy)於暴露出的矽基底1〇〇表面形成一層鍺的矽化層（SiGe)108。 4 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 516230 6978twf.doc / 006 pj B7 V. Description of the invention (ί) The present invention relates to a method for forming a double-carrier transistor, in particular to a method for forming a heterojunction double-carrier Transistor (Heterojunctnon Bipolar Transistor) method. A bipolar junction transistor (BJT) is an electronic component that uses two types of carriers (Carnes), an electron and a hole, to conduct current. B〗 T has the advantage of fast processing speed. It is usually used for high power devices or logic circuits that require high speed. B〗 T's structure is a three terminal (Three Terminal) element composed of two tight pn junctions. These two contacts are called Emitter, Base and Colkctor. The heterojunction bipolar transistor refers to a bipolar transistor formed by using heterojunction. Among them, "heterojunction" refers to a technique in which two different materials are bonded to each other. Figures 1A to 1B are schematic cross-sectional views showing the manufacturing process of a conventional heterojunction bipolar transistor. Referring to FIG. 1A, an oxide layer 103, an in-Situ Boron-Doped Poly-Si (IBDP) layer 102, and a silicon oxide layer 104 are sequentially formed on the silicon substrate 100, and then patterned. The IBDP layer 102 and a silicon oxide layer 104 are formed to form an emitter window opening 106 to expose the silicon substrate 100. Since the heterojunction bipolar transistor is formed directly on the silicon substrate, the emitter, base, and collector generate large parasitic capacitances through the silicon substrate. Next, referring to FIG. 1B, an epitaxial growth (Epitaxy) is used to form a silicon silicide layer (SiGe) 108 on the exposed silicon substrate 100 surface. 4 This paper size is applicable to China National Standard (CNS) A4 (21 × 297 mm) (Please read the precautions on the back before filling this page)

516230 697 8twf. doc/006 pj B7 五、發明說明（么）最後，於矽基底100上形成一層摻雜磷多晶矽（In-Situ Phosphorous-Doped Poly-Si，IPDP)層 112，且覆蓋射極窗開口 106。之後的技術爲熟悉此技術者能輕易完成。因此，本發明提供一種形成異質接合雙載子電晶體的方法。此方法可以降低寄生電容與改善基極、急極、射極間平坦化時所造成的困難度。本發明提供一種形成異質接合雙載子電晶體的方法。此方法係在一矽基底上形成一絕緣層，然後於絕緣層上形成一層矽層，並定義此矽層。然後於絕緣層上依序形成一層氧化層與一層黏著層，然後於絕緣層上形成一層IBDP，隨後去除矽層上的IBDP。然後於絕緣層上再形成一層氧化層，並圖案化此氧化層以暴露出黏著層，形成一射極窗開口。接著去除射極窗開口內的黏著層與氧化層，然後利用磊晶成長於該矽層表面形成一 SiGe，並於該第二氧化層側壁與該SiGe上形成一間隙壁，最後於該基底上形成一 IPDP，作爲電晶體的射極。此外，本發明提供另一種形成異質接合雙載子電晶體的方法。此方法係在一矽基底上形成一絕緣層，然後於絕緣層上形成一層矽層，並於該矽層上形成一保護層。然後定義保護層與矽層，隨後於保護層與矽層側壁形成一間隙壁。接著於絕緣層上形成一 IBDP層，並去除該矽層上的 IBDP層。然後於IBDP層表面形成一氧化層，並圖案化此氧化層以暴露出保護層，形成一射極窗開口。隨後去除該保護層與該第一間隙壁，並於基底上形成一 S!Ge層。然 5 (請先閱讀背面之注意事項再填寫本頁) tr--------- 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 516230 6978twf. doc/006 pj __ B7 五、發明說明（>) 後去除部分SiGe層，以暴露出部分氧化層側壁。之後於氧化層側壁與S：iGe層表面形成一第二間隙壁。最後於基底上形成一 IPDP層做爲電晶體的射極。本發明利用SOI的技術形成異質接合雙載子電晶體，故射極、基極與集極不會如習知技術一樣藉由矽基底而產生較大的寄生電容。而且本發明所形成的射極、基極與集極因爲深度大致一樣，不會像習知技術中的射極、基極與集極一樣在深度上有差異，故較易於平坦化。此外本發明的基極較習知方式形成的層狀基極有更大之接合面積，因此可以提供更大的電流。爲讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：圖式之簡單說明：第1A圖至第1B圖是習知一種異質接合雙載子電晶體之製作流程剖面示意圖。；以及第2A圖至第2E圖是依照本發明一較佳實施例一種形成異質接合雙載子電晶體的方法流程剖面圖；第3A圖至第3F圖是依照本發明一較佳實施例一種形成異質接合雙載子電晶體的方法流程剖面圖；以及第4D圖至第4F圖是依照依照本發明一較佳實施例另一種形成異質接合雙載子電晶體的方法流程剖面圖。標記之簡單說明： 100，20，30 ··矽基底本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ，-裝 ----訂---------. 經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 516230 6978twf·doc/006 pj B7 五、發明說明（+) 200，300 :絕緣層 102，208，308 : IBDP 層 103，104，204，210，310 :氧化層 106，211，311 :射極窗開口 108 ， 212 ， 312 : SiGe 層 112 ， 216 ， 316 : IPDP 層 202，302，302a :矽層 206 :黏著層 214，304 i 314 :間隙壁 306，306a，306b :保護層 307 :凹槽第一實施例第2A圖至第2E圖是依照本發明一較佳實施例一種形成異質接合雙載子電晶體的方法流程剖面圖。請參照第2A圖，於一矽基底20上形成一層絕緣層 200，並在此絕緣層200上形成一層矽層並定義之，以形成作爲集極的矽層202。然後於絕緣層200上依序形成一層氧化層204與一層黏著層206，黏著層206的材質例如是氮化砂。因爲使用絕緣層上有砍（Silicon On Insulator， SOI)的技術，所以之後形成的射極、基極與集極不會如習知技術中的射極、基極與集極藉由矽基底而產生較大的寄生電容。然後，請參照第2B圖。於絕緣層200上形成一層摻雜硼多晶矽（In-situ Boron-Doped Poly-Si，IBDP) 208。再 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) w-裝 i_!!訂！丨！！ . 516230 697 8twf. doc/0 06 pj 一 B7 五、發明說明（g) 於絕緣層200上形成一層氧化層210。之後，請參照第2C圖，圖案化氧化層210以暴露出黏著層206，形成一射極窗開口 211。並去除矽層202表面的黏著層206與氧化層204。請參照第2D圖，利用磊晶成長（Epitaxy )於砂層202 表面形成一層鍺的矽化層（SiGe) 212作爲基極。由於作爲基極的SiGe層212是形成於矽層202表面，故可獲得較習知方式形成的基極更大之接合面積，以提供更大的電流。然後於氧化層210側壁與SiGe層212上形成間隙壁 214,其中間隙壁214是用來作爲之後形成集極的離子植入步驟（未繪出）之罩幕。最後，請參照第2E圖，於絕緣層200上形成一層摻雜磷多晶砂（In-situ Phosphorous-Doped Poly-Si，IPDP)層 216 做爲電晶體的射極。第二實施例第3A圖至第3F圖是依照本發明一較佳實施例一種形成異質接合雙載子電晶體的方法流程剖面圖。請參照第3A圖，於一矽基底30上形成一層絕緣層 300，於絕緣層300上形成一層矽層302，然後於矽層302 上形成一層保護層306,保護層306的材質例如是氮化矽。因爲使用SOI的技術，所以之後形成的射極、基極與集極不會如習知技術中的射極、基極與集極藉由矽基底而產生較大的寄生電容。然後，請參照第3B圖，定義保護層306與矽層302， 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---I---— 丨訂----- - ---· 經濟部智慧財產局員工消費合作社印製 516230 6978twf.doc/006 A7 _B7____ 五、發明說明（G ) 以形成作爲集極的砂層302a，並於保護層306a與砂層3〇2a 側壁形成一間隙壁304。間隙壁304的材質例如是氧化物。接著，請參照第3C圖，於絕緣層300上形成一層IBDP 層308。然後，於IBDP層308表面形成一層圖案化氧化層 310以暴露出保護層306a，形成一射極窗開口 311。接著，請參照第3D圖，去除保護層306與間隙壁304。然後’請參照第3E圖，利用嘉晶成長於射極窗開口 311內形成一 SiGe層312並覆蓋矽層302a，且暴露出部分氧化層310的側壁。由於作爲基極的SiGe層312覆蓋於矽層302a表面，故可獲得較習知方式形成的基極更大之接合面積，以提供更大的電流。接著，於氧化層310側壁與 SiGe層312表面形成另一間隙壁314，其中間隙壁314是用來作爲之後形成集極的離子植入步驟（未繪出）之罩幕。最後，請參照第3F圖，於絕緣層300上形成一層ipDp 層316做爲電晶體的射極。第4D圖至第4F圖是依照依照本發明一較佳實施例另一種形成異質接合雙載子電晶體的方法流程剖面圖。其中在第4D圖之前的方法流程圖，請參照第3A圖至第3C圖。然後，請參照第4D圖，圖案化保護層306a，以暴露出部分矽層302a，然後以圖案化的保護層3〇6b爲罩幕，對矽層302a進行蝕刻，以形成一凹槽307。因此於本實施例中有較大的接觸面積。然後’請參照第4E圖，去除圖案化的保護層306b與間隙壁304’並利用磊晶成長於射極窗開口 hi內形成一 9 (請先閱讀背面之注意事項再填寫本頁) ----訂------------^1-· 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 516230 6978twf. doc/00 6 pj _ B7 五、發明說明（^)516230 697 8twf. Doc / 006 pj B7 V. Description of the invention (?) Finally, an In-Situ Phosphorous-Doped Poly-Si (IPDP) layer 112 is formed on the silicon substrate 100 and covers the emitter window Opening 106. Subsequent techniques can be easily completed by those familiar with this technique. Therefore, the present invention provides a method for forming a heterojunction bipolar transistor. This method can reduce the difficulty caused by parasitic capacitance and improve the planarization between the base, acute, and emitter. The invention provides a method for forming a heterojunction bipolar transistor. This method forms an insulating layer on a silicon substrate, and then forms a silicon layer on the insulating layer, and defines the silicon layer. Then, an oxide layer and an adhesive layer are sequentially formed on the insulating layer, then an IBDP is formed on the insulating layer, and then the IBDP on the silicon layer is removed. An oxide layer is then formed on the insulating layer, and the oxide layer is patterned to expose the adhesive layer, forming an emitter window opening. Next, the adhesive layer and the oxide layer in the emitter window opening are removed, and then epitaxial growth is used to form a SiGe on the surface of the silicon layer, and a gap wall is formed on the side wall of the second oxide layer and the SiGe, and finally on the substrate An IPDP is formed as the emitter of the transistor. In addition, the present invention provides another method for forming a heterojunction bipolar transistor. This method involves forming an insulating layer on a silicon substrate, then forming a silicon layer on the insulating layer, and forming a protective layer on the silicon layer. Then define the protective layer and the silicon layer, and then form a gap wall between the protective layer and the sidewall of the silicon layer. Then, an IBDP layer is formed on the insulating layer, and the IBDP layer on the silicon layer is removed. An oxide layer is then formed on the surface of the IBDP layer, and the oxide layer is patterned to expose the protective layer to form an emitter window opening. Then, the protective layer and the first spacer are removed, and an S! Ge layer is formed on the substrate. Ran 5 (Please read the notes on the back before filling this page) tr --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) 516230 6978twf. Doc / 006 pj __ B7 V. Description of the invention (>) After removing a part of the SiGe layer, a part of the sidewall of the oxide layer is exposed. A second gap wall is then formed on the sidewall of the oxide layer and the surface of the S: iGe layer. Finally, an IPDP layer is formed on the substrate as the emitter of the transistor. The invention uses the technology of SOI to form a heterojunction bipolar transistor, so the emitter, base, and collector do not generate large parasitic capacitance through the silicon substrate as in the conventional technology. Moreover, the emitter, base, and collector formed by the present invention have the same depth, so they do not have the same depth difference as the emitter, base, and collector in the conventional technology, so they are easier to flatten. In addition, the base of the present invention has a larger bonding area than the layered base formed in the conventional manner, and thus can provide a larger current. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to FIG. 1B is a schematic cross-sectional view of a conventional manufacturing process of a heterojunction bipolar transistor. ; And FIGS. 2A to 2E are cross-sectional views of a method for forming a heterojunction bipolar transistor according to a preferred embodiment of the present invention; and FIGS. 3A to 3F are a kind of preferred embodiment according to the present invention. A cross-sectional view of a method for forming a heterojunction bipolar transistor; and FIGS. 4D to 4F are cross-sectional views of another method for forming a heterojunction bipolar transistor according to a preferred embodiment of the present invention. Simple description of the mark: 100, 20, 30 ·· Silicone substrate This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) ---- Order ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 516230 6978twf · doc / 006 pj B7 V. Description of the Invention 200, 300: insulating layers 102, 208, 308: IBDP layers 103, 104, 204, 210, 310: oxide layers 106, 211, 311: emitter window openings 108, 212, 312: SiGe layers 112, 216, 316: IPDP layers 202, 302, 302a: silicon layer 206: adhesive layer 214, 304 i 314: spacers 306, 306a, 306b: protective layer 307: grooves First Embodiment Figures 2A to 2E are according to the present invention. A preferred embodiment is a flow sectional view of a method for forming a heterojunction bipolar transistor. Referring to FIG. 2A, an insulating layer 200 is formed on a silicon substrate 20, and a silicon layer is formed on the insulating layer 200 and defined to form a silicon layer 202 as a collector. Then, an oxide layer 204 and an adhesive layer 206 are sequentially formed on the insulating layer 200. The material of the adhesive layer 206 is, for example, nitrided sand. Because Silicon On Insulator (SOI) technology is used, the emitters, bases, and collectors formed later will not be formed by the silicon substrate as the emitters, bases, and collectors in the conventional technology. Generates large parasitic capacitance. Then, refer to Figure 2B. A layer of In-situ Boron-Doped Poly-Si (IBDP) 208 is formed on the insulating layer 200. 7 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) w-install i_ !! Order!丨! !! 516230 697 8twf. Doc / 0 06 pj A B7 V. Description of the invention (g) An oxide layer 210 is formed on the insulating layer 200. After that, referring to FIG. 2C, the oxide layer 210 is patterned to expose the adhesive layer 206, and an emitter window opening 211 is formed. And the adhesive layer 206 and the oxide layer 204 on the surface of the silicon layer 202 are removed. Referring to FIG. 2D, epitaxial growth (Epitaxy) is used to form a silicon silicide layer (SiGe) 212 on the surface of the sand layer 202 as a base. Since the SiGe layer 212 as the base is formed on the surface of the silicon layer 202, a larger bonding area can be obtained than a conventionally formed base to provide a larger current. Then, a spacer 214 is formed on the sidewall of the oxide layer 210 and the SiGe layer 212. The spacer 214 is used as a mask for an ion implantation step (not shown) for forming a collector later. Finally, referring to FIG. 2E, an In-situ Phosphorous-Doped Poly-Si (IPDP) layer 216 is formed on the insulating layer 200 as an emitter of the transistor. Second Embodiment FIGS. 3A to 3F are cross-sectional views of a method for forming a heterojunction bipolar transistor according to a preferred embodiment of the present invention. Referring to FIG. 3A, an insulating layer 300 is formed on a silicon substrate 30, a silicon layer 302 is formed on the insulating layer 300, and then a protective layer 306 is formed on the silicon layer 302. The material of the protective layer 306 is, for example, nitride. Silicon. Because the SOI technology is used, the emitter, base, and collector formed later will not generate a larger parasitic capacitance through the silicon substrate than the emitter, base, and collector in the conventional technology. Then, please refer to Figure 3B to define the protective layer 306 and silicon layer 302. 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) --- I ---- 丨 Order --------- · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 516230 6978twf.doc / 006 A7 _B7____ V. Description of Invention (G) to form a collector A protective layer 302a is formed between the protective layer 306a and the sidewall of the sand layer 302a. The material of the partition wall 304 is, for example, an oxide. Next, referring to FIG. 3C, an IBDP layer 308 is formed on the insulating layer 300. Then, a patterned oxide layer 310 is formed on the surface of the IBDP layer 308 to expose the protective layer 306a, and an emitter window opening 311 is formed. Next, referring to FIG. 3D, the protective layer 306 and the spacer 304 are removed. Then, referring to FIG. 3E, a SiGe layer 312 is formed in the emitter window opening 311 by using Jiajing to cover the silicon layer 302a, and a part of the sidewall of the oxide layer 310 is exposed. Since the SiGe layer 312 as a base covers the surface of the silicon layer 302a, a larger contact area can be obtained than a conventionally formed base to provide a larger current. Next, another spacer 314 is formed on the sidewall of the oxide layer 310 and the surface of the SiGe layer 312. The spacer 314 is used as a mask for an ion implantation step (not shown) for forming a collector later. Finally, referring to FIG. 3F, an ipDp layer 316 is formed on the insulating layer 300 as the emitter of the transistor. Figures 4D to 4F are cross-sectional views of a method for forming a heterojunction bipolar transistor according to another preferred embodiment of the present invention. For the method flow chart before Figure 4D, please refer to Figures 3A to 3C. Then, referring to FIG. 4D, the protective layer 306a is patterned to expose a part of the silicon layer 302a, and then the silicon layer 302a is etched with the patterned protective layer 306b to form a recess 307. Therefore, there is a larger contact area in this embodiment. Then 'Please refer to Figure 4E, remove the patterned protective layer 306b and the spacer 304' and use epitaxial growth to form a 9 in the emitter window opening hi (Please read the precautions on the back before filling this page)- --Order ------------ ^ 1- · This paper is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) 516230 6978twf doc / 00 6 pj _ B7 V. Description of the Invention (^)

SiGe層312，且覆蓋於凹槽307，並暴露出部分氧化層310 的側壁。最後，請參照第4F圖，於氧化層310側壁與SiGe層 312表面形成另一間隙壁314，其中間隙壁314是用來作爲之後形成集極的離子植入步驟（未繪出）之罩幕。接著於絕緣層300上形成一層IPDP層316做爲電晶體的射極。綜上所述，本發明的特徵如下： 1. 本發明是利用SOI的技術形成異質接合雙載子電晶體，而習知則是直接於矽基底上形成異質接合雙載子電晶體，故本發明中的射極、基極與集極不會如習知技術中的射極、基極與集極藉由矽基底而產生較大的寄生電容。 2. 本發明所形成的射極、基極與集極因爲深度大致一* 樣，不會像習知技術中的射極、基極與集極一樣在深度上有差異，而使製程在平坦化步驟遇到較多的問題。 3·本發明作爲基極的SiGe層是形成於立體矽層表面’故可獲得較習知方式形成的層狀基極有更大之接合面積，以提供更大的電流。雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者爲準。 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅？事項再填寫本頁) 裝 -------訂---------. 經濟部智慧財產局員工消費合作社印製The SiGe layer 312 covers the groove 307 and exposes a portion of the sidewall of the oxide layer 310. Finally, referring to FIG. 4F, another spacer 314 is formed on the sidewall of the oxide layer 310 and the surface of the SiGe layer 312. The spacer 314 is used as a mask for the ion implantation step (not shown) to form a collector later. . Next, an IPDP layer 316 is formed on the insulating layer 300 as an emitter of the transistor. To sum up, the features of the present invention are as follows: 1. The present invention is to form a heterojunction bipolar transistor using SOI technology, and it is conventional to form a heterojunction bipolar transistor directly on a silicon substrate. Therefore, the present invention The emitter, base, and collector in the conventional method do not generate large parasitic capacitance through the silicon substrate as in the emitter, base, and collector of the conventional technology. 2. The emitter, base, and collector formed by the present invention are approximately the same depth *, and will not have the same depth difference as the emitter, base, and collector in the conventional technology, so that the process is flat. The transformation step encountered more problems. 3. The SiGe layer used as the base of the present invention is formed on the surface of the three-dimensional silicon layer. Therefore, it is possible to obtain a larger bonding area than a conventionally formed layered base to provide a larger current. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 10 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) ---. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

Claims

516230 A8 B8 6978twf.doc / 006_g | _ VI. Scope of Patent Application 1. A method for forming a heterojunction bipolar transistor, including: providing a silicon substrate; (Please read the precautions on the back before filling out this page) at Forming an insulating layer on the silicon substrate; forming a silicon layer on the insulating layer; defining the sand layer; sequentially forming a first oxide layer and an adhesive layer on the insulating layer; forming a doping on the insulating layer Boron polycrystalline silicon layer; forming a second oxide layer on the insulating layer; patterning the second oxide layer to expose the adhesive layer to form an emitter window opening; removing the adhesive layer and the first surface of the silicon layer An oxide layer; forming a silicide layer of germanium on the surface of the silicon layer by epitaxial growth and exposing a part of the side wall of the second oxide layer; forming a gap wall on the side wall of the second oxide layer and the silicide layer of germanium; and A doped phosphorus polycrystalline silicon layer is formed on the insulating layer as an emitter of the transistor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. The method for forming a heterojunction bipolar transistor as described in item 1 of the scope of patent application, wherein the material of the adhesive layer includes silicon nitride. 3. A method for forming a heterojunction bipolar transistor, comprising: providing a silicon substrate; forming an insulating layer on the silicon substrate; forming a silicon layer on the insulating layer; forming a protection on the silicon layer 11 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A8B8C8D8 516230 6978twf.doc / 0〇 6. The scope of the patent application defines the protective layer and the silicon layer; A sidewall of the silicon layer forms a first gap wall; a boron-doped polycrystalline silicon layer is formed on the insulating layer; a patterned oxide layer is formed on the surface of the boron-doped polycrystalline silicon layer to form an emitter window opening; The oxide layer is a mask, removing the protective layer and the first spacer; forming a silicide layer of germanium on the insulating layer, covering the surface of the silicon layer, and exposing part of the sidewall of the patterned oxide layer; A sidewall of the patterned oxide layer and a surface of the silicide layer of the germanium form a second gap wall; and a doped phosphorus polycrystalline silicon layer is formed on the insulating layer as an emitter of the transistor. ^ 4. The method for forming a heterojunction bipolar transistor as described in item 3 of the scope of the patent application, wherein the material of the protective layer includes silicon nitride. 5. The method for forming a heterojunction bipolar transistor as described in item 3 of the patent application scope, wherein the material of the first spacer comprises an oxide. 6. A method for forming a heterojunction bipolar transistor, comprising: providing a silicon substrate; forming an insulating layer on the silicon substrate; forming a silicon layer on the insulating layer; forming a protection on the silicon layer Layer; define the protective layer and the silicon layer; form a first gap between the protective layer and the sidewall of the silicon layer; 12 (Please read the precautions on the back before filling this page) Order -------- -Line. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 516230 A8 B8 6978twf · doc / 006 C8 6. The scope of patent application is on this insulation layer A boron-doped polycrystalline silicon layer is formed on it; (Please read the precautions on the back before filling this page). Form a patterned oxide layer on the surface of the boron-doped polycrystalline silicon layer to expose the protective layer and form an emitter window opening; Patterning the protective layer to expose a portion of the silicon layer; using the patterned protective layer as a mask, etching the silicon layer to form a groove in the silicon layer; using the patterned oxide layer as a mask Screen, remove the guarantee A protective layer and the first spacer; forming a silicide layer of germanium on the insulating layer, covering the surface of the groove, and exposing part of the sidewall of the patterned oxide layer; on the sidewall of the patterned oxide layer and the germanium A second gap wall is formed on the surface of the silicide layer; and a doped phosphorus polycrystalline silicon layer is formed on the insulating layer as an emitter of the transistor. 7. The method for forming a heterojunction bipolar transistor as described in item 6 of the patent application scope, wherein the material of the protective layer includes silicon nitride. 8. The method for forming a heterojunction bipolar transistor as described in item 6 of the patent application scope, wherein the material of the first spacer comprises an oxide. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)