TW515061B - Electroplating nickel/gold process and structure for electric contact pad of chip package substrate - Google Patents

Electroplating nickel/gold process and structure for electric contact pad of chip package substrate Download PDF

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Publication number
TW515061B
TW515061B TW90127968A TW90127968A TW515061B TW 515061 B TW515061 B TW 515061B TW 90127968 A TW90127968 A TW 90127968A TW 90127968 A TW90127968 A TW 90127968A TW 515061 B TW515061 B TW 515061B
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TW
Taiwan
Prior art keywords
contact pad
layer
electrical contact
substrate
gold
Prior art date
Application number
TW90127968A
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English (en)
Inventor
Shr-Bin Shiu
Jiang-Du Chen
Yan-Hung Liou
Original Assignee
Phoenix Prec Technology Corp
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Publication date
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Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW90127968A priority Critical patent/TW515061B/zh
Application granted granted Critical
Publication of TW515061B publication Critical patent/TW515061B/zh

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

A Be D M5U01 第90127968號,%年4月7日更正頁 丨六、申請專利範圍 ⑷於基板上形成_第二光阻、 於第一光阻層開孔區之導電膜4一先阻層覆住殘露 該基板至少-電性制墊進行f 性接觸墊表面鍍上鎳/金層; 使所这電 (f)移除第二、-光阻層及其所覆蓋之導電膜。 5 ·如申請專利範圍第4項所述之 墊之電鑛鋅/全f程,b μ 基板電性接觸 =士其中在步驟⑴之後’更可包括一步驟 )*在邊基板表面上覆上一防焊層,該防焊層露出前述完 成電鍍鎳/金屬之電性接觸墊。 :觸申ΓΓ圍第4或第5項所述之—種晶片封裝基板電性 塾之電鍍鎳/金製程’其中所述電性接觸墊係為基板之 打線墊(Bonding Pad)。 7. 如申請專利範或第5項所述之—種晶片封裝基板電性 接觸墊之電制/金製程,其中所述電性接觸墊係為基板之 錫球墊(Solder Ball Pad)。 8. 如申請專利範圍第4或第5項所述之—種晶片封裝基板電性 接觸塾之電鑛錄/金製程,其中所述導電膜可為錫(sn)、 銅(〇0、鉻(⑺、!巴⑽、鎳⑽、錫/錯(Sn/pb) 等材質或其合金所組成。 9. 如申請專利第4或第5項所述之—種“封裝基板電性 接觸墊之電鍍鎳/金製程,其中所述物理沈積方式形成一導 電膜,係以濺鑛(Sputtering)方式形成。 12 本紙張尺度適用中國國家標準(CNS) A4規格(210x297公釐) (請先閱讀背面之注意事項再填寫本頁各攔) 裝 t4線!
TW90127968A 2001-11-12 2001-11-12 Electroplating nickel/gold process and structure for electric contact pad of chip package substrate TW515061B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW90127968A TW515061B (en) 2001-11-12 2001-11-12 Electroplating nickel/gold process and structure for electric contact pad of chip package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90127968A TW515061B (en) 2001-11-12 2001-11-12 Electroplating nickel/gold process and structure for electric contact pad of chip package substrate

Publications (1)

Publication Number Publication Date
TW515061B true TW515061B (en) 2002-12-21

Family

ID=27786862

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90127968A TW515061B (en) 2001-11-12 2001-11-12 Electroplating nickel/gold process and structure for electric contact pad of chip package substrate

Country Status (1)

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TW (1) TW515061B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7125745B2 (en) 2003-04-28 2006-10-24 Advanced Semiconductor Engineering, Inc. Multi-chip package substrate for flip-chip and wire bonding
US7627946B2 (en) 2006-03-20 2009-12-08 Phoenix Precision Technology Corporation Method for fabricating a metal protection layer on electrically connecting pad of circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7125745B2 (en) 2003-04-28 2006-10-24 Advanced Semiconductor Engineering, Inc. Multi-chip package substrate for flip-chip and wire bonding
US7627946B2 (en) 2006-03-20 2009-12-08 Phoenix Precision Technology Corporation Method for fabricating a metal protection layer on electrically connecting pad of circuit board

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