五、發明説明（1) 發明背景 發阻領域 本發明係有關一種半導體元件，半導體測試結構及半導 體元件之製造方法◦ 祖關技術說明 藉文獻[1 ]可得知此種半導體測試結構。 於製造含有複數個MOS電晶體（金屬氧化物半導體電晶體 )之大型積體電路期間，經常將電晶體有電漿處理步驟當 作一部分製造方法，這類電漿處理步驟指的就是那些使用 電漿當作該裝置的部分製造或處理或是當作部分交聯作用 的方法步驟。這種型式之電漿處理步驟中所用的電漿能夠 爲場效電晶體之閘極區域上的電導性供應導體（連接線）施 行電氣充電並爲該閘極區域施行電氣充電。累積於各供應 導體上及該閘極區域內的電荷會流出跨越落在該閘極區域 底下之絕緣區域的介電質，且若未於製造期間依適當方式 使電漿處理最佳化則可能會破壞或甚至摧毀該閘極區域。 例如，特別是可能產生漏電流路徑，這在經完全處理的電 晶體內可能會引致破損以及更縮短服務期限或是引致完全 故障。 這種對絕緣區域的破壞亦即降解現象及/或無意地將漏 電流路徑引進該介電質內，是吾人所熟知由電荷造成的電 漿-誘發損壞（PID)，如同文獻[2]中所顯示係取決於被帶 到接觸電漿處之供應導體表面積對該場效電晶體之活性介 電面積（亦即對其上塗覆有閘極區域之介電質表面）的天線 五、發明説明（2 ) 比（AR)。 ， 被帶到接觸電漿處之供應導體表面積與活性介電表面積 的比例會於製程期間連續地改變，亦即其天線比不是定常 的（參見文獻[2])。 位處其內之場效電晶體及晶片的最大服務期限及持久性 都可能因爲製造期間不同位準之電漿-誘發損壞而遭受可 觀的損害，結果其損害可能會比在晶片設計中所佈局的損 害大相當多。 爲了使吾人能夠估計晶片內所用元件特別是場效電晶體 (或者也包含電容器）的可靠度，例如有關熱載子或可動離 子的降解作用，必要的是儘可能使各量測內不包含電漿-誘發損壞的影響。 因爲這個理由，應該藉由保護結構亦即藉由半導體保護 結構儘可能使出電荷造成之電漿-誘發損壞的影響最小化 或是完全排除。此外，爲了獲致有關由電荷造成之電漿-誘發損壞程度的最佳可能定性資訊，極爲重要的是設計出 對應的半導體PID測試結構，使之具有經準確定義之導電 性供應導體表面積對活性介電表面積上被帶到接觸電漿處 之閘極區域的比例。 於文獻[1]和[2]中所說明半導體測試結構的例子裡，係 於較遲的處理位準中且因此係於製程內比電晶體處理位準 更高的位準中提供有保護二極體，以便減少各供應導體上 的電漿-誘發電荷，亦即允許電荷經由這類導體而漏泄掉 。可替代地，在使供應導體且因此使充電作用最小化的目 -4- 五、發明説明（3) 的之下說明了跨接線.的使用。 於本發明的說明中，係將處理位準一詞理解爲例如半導 體製程內的佈線位準，或者.一般而言指的是於至少某一處 理步驟期間用來施行半導體裝置之製造或處理的位準。 特別是使用保護二極體的缺點是只有一種型式的電荷載 子能夠漏泄掉。另一缺點是保護二極體會影響該元件的性 能且只能將保護二極體連接在第一金屬化位準之後。 發明之扼要說明 因此，本發明係以減低電子元件上由電荷造成之電漿-誘發損壞影響的問題爲基礎而提出的。 該問題係藉由具有如申請專利範圍各附屬項目中所給定 特性的半導體元件，半導體測試結構及半導體元件之製造 方法而獲致解決的。 一種例如晶圓上的晶片之類半導體元件係含有基板。電 氣活性區域係配置於該基板之內或之上。該電氣活性區域 可能是一種電容器且較佳的是ΜI S電容器（金屬-絕緣體-半 導體電容器）的電極，也可能是例如一種場效電晶體的通 路區域。 包括介電質的電氣絕緣區域係配置於該電氣活性區域上 。而將例如場效電晶體的另一電極或閘極區域之類的導電 區域加到該絕緣區域上。 該導電區域係依電氣方式耦合於導電性供應導體上亦即 連接於後者上。 此外，有一導電性輔助導體軌道配置在與該導電性供應 513814 五、發明説明（ 4) 導 體 相 鄰 處 且 係依 電 /二-: 方式 奉禹 合於至少- 個 區域上，此 區 域 係 由 基 板 或 基 板 內 之位阱 構 成而高度 地 攙 雜了具有第 一 導 電 型式的 攙 雜 原 子 Ο 本文 中 吾 人 m 該 指 出的 是 本發明並 不 受 限於MIS電 容 器 或 是 場 效 電 晶 體 5 而 是 適 用 於任何堆 疊 結 構，其中較 佳 的 是 能 夠 將 包括介 電 質 的 絕 緣 區域用在 例 如 包含導電區 域 的 電 氣 活性 1^ 域 上 妖 J\\\ 後 能 夠 將鍋合於 導 電 性供應導體 上 的另 一 導 電 1品 域 加到此 絕 緣 域上；藉 由 富 例吾人也能 夠 將 之 用 於 MIM 電 容 器 (金屬- 絕 緣體-金屬電容器）、多晶矽- 多晶矽 電 容 器 記 憶 體 單 元 可控整流 器 或其他具有 對 應 結 構 的功 率 半 導 體 元件 〇 輔 助 導 體 軌 道 — 詞 將 被 理 解爲依半 導 體 元件的功能 指 一 種 於半 導 體 元件 內所 提 供 電路元件 中 不 具任何功能 的 導 體 軌 道 且 只 會 於 電 漿 處 理特別是在 進 入連接到該 輔 助 導 體 軌 道 上之 高 攙 雜 區 域 內 的電漿飩 刻 處 理期間，經 由 該 輔 助 導 體 軌 道 而扮 演 著 使 發 生在絕緣 區 域 上導電性供 應 導 體 及 導 電 域 之 帶 電 載 子 累 積現象消 散 的 角色，以便依 這 種 方式 減 小 於 電 漿 蝕 刻 處 理 期間在介 電 質 上發生的損 壞 且 一 般 而 甚 至 使之 最 小化 〇 很 淸 楚 的 ， 能 夠 將 本 發 明 看 作與下列 事 實 是一致的， 電 漿 蝕 刻 處 理或 是 —. 般 的 電 漿 處 理期間累 積 於 導電性供應 導 體 Π-5Ζ. 上 之 帶 電 載 子 會 經 由 該 導 電 性輔助導 體 軌 道消散到例如 一 個 或 更 多 個 局 攙 雜 1^ 域 之內 ，且該導 電 性供應導體及 該 輔 助 導 體 軌 道 只 會 在 電 漿 鈾 刻步驟結束時依 -6· 處理工程的 方 513814 五、發明説明（5) 式達成電氣的去耦合.作用。 可以於該半導體元件內提供場效元件的源極區域以及場 效元件的汲極區域◦此例中，係將活性區域配置在該源極 區域與該汲極區域之間並形成該場效元件的通路區域。此 例中’該導電區域會形成場效元件例如場效電晶體的閘極 區域◦ 該電氣活性區域可能會形成電容器的第一電極，而該導 電區域可能會形成電容器的第二電極。 根據本發明的精煉型式，至少有一個第二區域係高度攙 雜具有第二導電型式的攙雜原子且係連接於該導電性輔助 導體軌道上。 較佳的是，將該高攙雜區域配置於基板內且用來使各帶 電載子消散到基礎材料之內亦即例如消散到該基板之內。 較佳的是將兩個高攙雜區域之一或是同時將兩個高攙雜區 域收納於該基板的位阱內。根據本發明的另一個組態而提 供的是將兩個高攙雜區域配置於該位阱內，且將一個或兩 個其他高攙雜區域配置於該基板的位阱外側，並同樣地使 之依電氣方式耦合於該輔助導體軌道上。 可以將該導電區域及該導電性供應導體配置於該半導體 元件的不同處理位準內，此例中較佳的是將該導電性供應 導體配置於該導電區域上方。 本文中，「上方」一詞將會被理解爲，於該半導體元件 的製程期間跟隨在製造另一層之步驟後的處理步驟內形成 落在另一層上方的層。 513814 五、發明説明（6) 此例中，係將該導s性供應導體及該導電性輔助導體軌 道配置於該半導體元件的相同處理位準內。 本文中吾人應該注意的是，由於只在已產生金屬層的圖 形之後形成該導電性供應導體及該輔助導體軌道，故於該 半導體元件的製程期間在對這兩種結構施行電漿鈾刻步驟 之前，它們相互間仍然是呈電氣耦合的。 在考量電漿蝕刻步驟時，較佳的是該導電性供應導體及 該導電性輔助導體軌道相互間只會在逼近電漿蝕刻步驟終 點時呈電氣耦合，亦即只有在逼近真實電漿蝕刻步驟終點 時仍然會於該導電性供應導體上形成並收集各帶電載子且 將之傳送到該閘極區域亦即一般的導電區域上，且依這種 方式能夠破壞該介電質，降低其晶片功能或在用於電晶體 之可靠度測試上干擾例如與熱載子或可動離子的降解作用 有關的量測結果。 不過於該電漿鈾刻處理步驟的大半持久性期間，該導電 性供應導體及該導電性輔助導體軌道相互間是呈電氣耦合 的，因此累積於這兩種結構上的各帶電載子能夠經由依電 風方式局度攙雜有攙雑原子的區域而漏泄掉。 根據本發明的某一組態’該導電區域係由高攙雜之多晶 矽形成的。 該導電性供應導體及/或該輔助導體軌道可能含有金屬 或金屬合金（或是由适類材料形成的）。較佳的是該導電性 供應導體及/或該輔助導體軌道係含有下列金屬中至少一一 種金屬： 513814 五、發明説明（7 ) •鋁，及/或 』 •銅，及/或 •金，及/或 •一種由上述金屬中至少一種金屬構成的合金。 一般而言該導電性供應導體及/或該輔助導體軌道可能 含有任意一種適合的導電材料，例如 •多晶矽， •金屬矽化物。 該基板可能含有或被形成於下列半導體材料中至少一種 半導體材料： •取自週期表中第IV族的單元素半導體材料，較佳的是砂， •由許多取自週期表中第IV族中單元素之不同半導體材料 構成的化合物，較佳的是矽化鍺， • III-V族半導體材料，較佳的是砷化鎵及磷化銦， • II-VI族半導體材料。 特別是’若該導電性供應導體及該輔助導體軌道係配置 在不同的處理位準上，亦即因此落在半導體元件內的不同 位準上，特別是它們係經由至少一個塡充有導電材料的接 觸孔而耦合在一起的。 根據本發明的某一解釋用實施例，這種導電性稱合作用 係含有下列金屬中至少一種金屬： •鎢，及/或 •鋁，及/或 •銅，及/或 -9-V. Description of the invention (1) Background of the invention The field of resistance The present invention relates to a semiconductor device, a semiconductor test structure, and a method of manufacturing a semiconductor device. During the manufacture of large-scale integrated circuits containing a plurality of MOS transistors (metal oxide semiconductor transistors), the plasma has a plasma processing step as a part of the manufacturing method. This type of plasma processing step refers to those using electricity The pulp is manufactured or processed as part of the device or as a method step for partial crosslinking. The plasma used in this type of plasma processing step is capable of electrically charging the conductive supply conductor (connecting wire) on the gate region of the field effect transistor and electrically charging the gate region. The charge accumulated on each supply conductor and in the gate region will flow out of the dielectric across the insulating region falling under the gate region, and it may be possible if the plasma treatment is not optimized in an appropriate manner during manufacturing. This gate area can be destroyed or even destroyed. For example, in particular, leakage current paths may occur, which may cause breakage and shorten service life or cause complete failure in a fully processed transistor. This kind of damage to the insulation area, that is, degradation and / or unintentional introduction of leakage current paths into the dielectric, is known to me as plasma-induced damage (PID) caused by electric charges, as in [2] What is shown is an antenna that depends on the active dielectric area of the field effect transistor (that is, the surface of the dielectric on which the gate region is coated) depending on the surface area of the supply conductor being brought into contact with the plasma. (2) ratio (AR). The ratio of the surface area of the supply conductor to the active dielectric surface area that is brought into contact with the plasma will continuously change during the process, that is, its antenna ratio is not constant (see reference [2]). The maximum service life and durability of field-effect transistors and wafers located within them may suffer considerable damage due to plasma-induced damage at different levels during manufacturing. As a result, the damage may be greater than that laid out in the wafer design. The damage is considerable. In order to enable us to estimate the reliability of the components used in the wafer, especially field-effect transistors (or also capacitors), such as the degradation of hot carriers or mobile ions, it is necessary to make sure that no electricity is included in each measurement. Pulp-induced damage effects. For this reason, the effect of the plasma-induced damage caused by the charge should be minimized or completely eliminated by the protective structure, that is, by the semiconductor protective structure. In addition, in order to obtain the best possible qualitative information on the degree of plasma-induced damage caused by electric charges, it is extremely important to design a corresponding semiconductor PID test structure with an accurately defined surface area of conductive supply conductors versus active dielectrics. Proportion of gate area on the electrical surface area that is brought into contact with the plasma. In the examples of semiconductor test structures described in [1] and [2], protection is provided at a later processing level and therefore at a level higher than the transistor processing level in the process. Pole body in order to reduce the plasma-induced charge on each supply conductor, that is, to allow the charge to leak through such conductors. Alternatively, the use of the jumper wire is explained below the purpose of minimizing the supply conductor and therefore the charging effect. Iv. The description of the invention (3). In the description of the present invention, the term processing level is understood to mean, for example, a wiring level in a semiconductor process, or, in general, refers to a process used to perform the manufacture or processing of a semiconductor device during at least one processing step. Level. In particular, the disadvantage of using a protective diode is that only one type of charge carrier can leak out. Another disadvantage is that the protection diode affects the performance of the element and can only connect the protection diode after the first metallization level. SUMMARY OF THE INVENTION Accordingly, the present invention is based on the problem of reducing the effect of plasma-induced damage caused by electric charges on electronic components. This problem was solved by a semiconductor element, a semiconductor test structure, and a method of manufacturing a semiconductor element having characteristics as given in the subsidiary items of the patent application scope. A semiconductor element such as a wafer on a wafer contains a substrate. The electrically active region is disposed in or on the substrate. The electrically active region may be an electrode of a capacitor and preferably an MIS capacitor (metal-insulator-semiconductor capacitor), or it may be a path region of a field effect transistor, for example. An electrically insulating region including a dielectric is disposed on the electrically active region. A conductive region such as another electrode of the field effect transistor or a gate region is added to the insulating region. The conductive area is electrically coupled to the conductive supply conductor, i.e. connected to the latter. In addition, a conductive auxiliary conductor track is arranged next to the conductive supply 513814 V. Description of the invention (4) The conductor is adjacent to the conductor and is connected to at least one area according to the electric / two-: method. This area is formed by The substrate or the potential wells in the substrate are highly doped with dopant atoms having the first conductivity type. In this article, we should point out that the present invention is not limited to MIS capacitors or field effect transistors. 5 It is applicable to Any stacked structure, among which it is preferable to be able to use an insulating region including a dielectric substance on, for example, an electrically active region including a conductive region. After the demon J \\\ is able to close the pot to another conductive supply conductor, Conductive 1 product domain is added to this insulation domain; with rich examples, we can also use it in MIM capacitors (metal-insulator-metal capacitors), polycrystalline silicon-polycrystalline silicon capacitor memory cell controllable rectifiers or other powers with corresponding structures semiconductor Component 〇 Auxiliary Conductor Track — The term will be understood to mean a semiconductor track that does not have any function among the circuit elements provided in the semiconductor element according to the function of the semiconductor element and will only be processed by plasma, especially when entering the auxiliary conductor track. During the plasma engraving process in the high-doped region, the auxiliary conductor track plays a role in dissipating the accumulation of charged carriers that occurs in the conductive supply conductor and conductive domain on the insulating region, so that in this way Reducing and generally minimizing damage to the dielectric during the plasma etching process can be considered as consistent with the fact that the plasma etching process is— The charged carriers accumulated on the conductive supply conductor Π-5Z during general plasma processing will dissipate to, for example, a conductive auxiliary conductor track to a Within the scope of more than 1 ^, and the conductive supply conductor and the auxiliary conductor track will only be reached at the end of the plasma uranium engraving step in accordance with the method of -6 · Treatment Engineering 513814 V. Invention description (5) Electrical decoupling. Role. The source region of the field effect element and the drain region of the field effect element can be provided in the semiconductor element. In this example, the active region is arranged between the source region and the drain region to form the field effect element. Access area. In this example, the conductive region will form the gate region of a field effect element such as a field effect transistor. The electrically active region may form the first electrode of a capacitor, and the conductive region may form the second electrode of a capacitor. According to the refining pattern of the present invention, at least one second region is highly doped with dopant atoms having a second conductivity type and is connected to the conductive auxiliary conductor track. Preferably, the highly doped region is arranged in a substrate and used to dissipate each of the charged carriers into the base material, that is, for example, into the substrate. Preferably, one of the two highly doped regions or both of the highly doped regions is housed in a potential well of the substrate. According to another configuration of the present invention, it is provided that two highly doped regions are arranged in the potential well, and one or two other highly doped regions are arranged outside the potential well of the substrate. Electrically coupled to the auxiliary conductor track. The conductive region and the conductive supply conductor may be arranged at different processing levels of the semiconductor element. In this example, it is preferable to arrange the conductive supply conductor above the conductive region. In this context, the term "above" will be understood to mean that a layer falling on top of another layer is formed in a processing step following the step of manufacturing another layer during the manufacturing process of the semiconductor device. 513814 V. Description of the invention (6) In this example, the conductive supply conductor and the conductive auxiliary conductor track are arranged in the same processing level of the semiconductor element. I should note in this article that since the conductive supply conductor and the auxiliary conductor track are formed only after the pattern of the metal layer has been generated, a plasma uranium engraving step is performed on these two structures during the process of the semiconductor element. Before, they were still electrically coupled to each other. When considering the plasma etching step, it is preferable that the conductive supply conductor and the conductive auxiliary conductor track are electrically coupled to each other only when approaching the end of the plasma etching step, that is, only when approaching the actual plasma etching step. At the end point, the charged carriers will still be formed and collected on the conductive supply conductor and transferred to the gate region, that is, the general conductive region. In this way, the dielectric can be destroyed and the chip can be reduced. Function or interference in reliability tests for transistors such as measurement results related to degradation of hot carriers or mobile ions. However, during most of the duration of the plasma uranium etching step, the conductive supply conductor and the conductive auxiliary conductor track are electrically coupled to each other, so each of the charged carriers accumulated on the two structures can pass through According to the electric wind method, the area doped with tritium atoms is leaked. According to a configuration of the present invention, the conductive region is formed of highly doped polycrystalline silicon. The conductive supply conductor and / or the auxiliary conductor track may contain a metal or a metal alloy (or be formed of a suitable material). Preferably, the conductive supply conductor and / or the auxiliary conductor track system contains at least one of the following metals: 513814 V. Description of the Invention (7) • Aluminum, and / or “• Copper, and / or • Gold And / or • an alloy composed of at least one of the above metals. In general, the conductive supply conductor and / or the auxiliary conductor track may contain any suitable conductive material, such as • polycrystalline silicon, • metal silicide. The substrate may contain or be formed from at least one of the following semiconductor materials: • a single-element semiconductor material from Group IV of the periodic table, preferably sand, • many from Group IV of the Periodic Table Single-element compounds composed of different semiconductor materials are preferably germanium silicides, • III-V semiconductor materials, more preferably gallium arsenide and indium phosphide, and • II-VI semiconductor materials. In particular, 'If the conductive supply conductor and the auxiliary conductor track are arranged at different processing levels, that is, they therefore fall at different levels within the semiconductor element, in particular, they are filled with a conductive material via at least one element. The contact holes are coupled together. According to an explanatory embodiment of the present invention, this conductivity is called a synergistic system containing at least one of the following metals: • tungsten, and / or • aluminum, and / or • copper, and / or -9-
五、發明説明（” •金，及/或 . •一種由_匕述金屬中至少一種金屬構成的合金。 根據本發明的某一組態，該輔助導體軌道係配置在與該 導電性供應導體相鄰而離開某一距離處，該距離係選擇爲 某一處理步驟之處理特徵的函數，該處理步驟係用來當作 部分製程及/或用來處理該輔助導體軌道及/或該導電性供 應導體的。這允許吾人將對應的處理特徵列入考量而進一 步施行本發明的最佳化。 較佳的是，該距離係選擇爲某一電漿蝕刻處理之處理特 徵的函數，該電漿蝕刻處理係用來當作部分製程及/或用 來處理該輔助導體軌道及/或該導電性供應導體的。 若該電漿蝕刻處理會蝕刻出非常大的露出表面且會依比 非常小的表面更快的速率與電漿形成接觸，有利的是該距 離係根據整體處理的最大解析度而選出的，例如以新近的 處理技術該距離係落在由0 . 1微米及0 . 3微米等構成的區 域內。 不過，若該電漿蝕刻處理係依比大型面積更快的速率蝕 刻出小型面積的方式而設立的’有利的是將該輔助導體軌 道與該導電性供應導體之間的距離選擇爲儘可能愈大愈好 ，以致能夠在各例中確保該輔助導體軌道與該導電性供應 導體之間的電氣耦合只會在逼近電漿蝕刻步驟終點時受到 電氣干擾。本文中，在選擇δ亥距離時應3亥將通夠於設g十圖 內該晶片上取得的自由空間列入考量。 在製程的架構之內’該距離的選擇係反映在對應配置以 -10- 513814 五、發明説明（9) 及對用來形成該導電性供應導體及該輔助導體軌道之個別 金屬層上光阻材料的圖形製作上。 因此’很淸楚的本發明係於電漿蝕刻處理期間利用去除 金屬的不同速率，達成使帶電載子於電漿飩刻處理期間依 最佳可能方式消散到個別的高攙雜區域之內，且因此減少 了於電獎餓刻處理期間對介電質的破壞。其中，文獻[2 ] 係描述電漿蝕刻處理之缺點。V. Description of the invention ("• Gold, and / or. • An alloy composed of at least one of the metals described in the above. According to a configuration of the present invention, the auxiliary conductor track is arranged with the conductive supply conductor Adjacent to a certain distance, the distance is selected as a function of the processing characteristics of a processing step, which is used as part of the process and / or used to process the auxiliary conductor track and / or the conductivity Supply of conductors. This allows me to take into account the corresponding processing characteristics and further implement the optimization of the present invention. Preferably, the distance is selected as a function of the processing characteristics of a certain plasma etching process, the plasma Etching is used as part of the process and / or for the auxiliary conductor track and / or the conductive supply conductor. If the plasma etching process will etch a very large exposed surface and will be very small The surface comes into contact with the plasma at a faster rate. It is advantageous that the distance is selected according to the maximum resolution of the overall processing. For example, with the latest processing technology, the distance falls from 0.1 micron. Within 0.3 m and 0.3 micron, etc. However, if the plasma etching process is to etch a small area at a faster rate than a large area, it is advantageous to connect the auxiliary conductor track with the conductive The distance between the conductive supply conductors is chosen to be as large as possible, so that in each case it can be ensured that the electrical coupling between the auxiliary conductor track and the conductive supply conductor is only electrically affected when the end of the plasma etching step is approached In this paper, when selecting the delta distance, the free space obtained on the chip that can reach the tenth figure should be taken into consideration. Within the framework of the process, the choice of this distance is reflected in the corresponding configuration. Take -10- 513814 V. Description of the invention (9) and the patterning of the photoresist material on the individual metal layers used to form the conductive supply conductor and the auxiliary conductor track. Therefore, the very 'sophisticated invention is based on During the plasma etching process, different rates of metal removal are used to achieve the best possible way for the charged carriers to dissipate into individual highly doped regions during the plasma etching process. Reduced damage to the dielectric during the engraving process the electrical award hungry. Wherein, [2] based plasma etching process described disadvantages of.
根據本發明的替代組態，係將另一電氣活性區域配置於 基板之內或之上，並將另一包括介電質的絕緣區域配置於 該另一電氣活性區域上，其中該介電質可能是與構成絕緣 區域之介電質完全相同的或者可能是一種不同的介電質。 根‘據本發明的這種組態，係將與另一導電性供應導體呈電 氣耦ί合的另一導電區域配置於另一絕緣區域上。另一絕緣 區域上配置有另一導電區域，該表面的尺寸是等於或大於 該絕緣區域上配置有該導電區域之該表面的尺寸。取決於 能夠取得的空間，另一絕緣區域之表面積（對該絕緣區域 之表面積）的比例可能是一個高達1 〇〇〇的倍數。可替代地 或是另外地，可以將另一絕緣區域的厚度亦即另一介電質 的厚度選擇爲小於該絕緣區域的厚度，亦即使該介電質的 厚度受到保護。 I 很淸楚地，根據本發明的這種組態提供的一種半導體元 件，係具有相同的結構但是增加了另一絕緣區域之表面積 對該絕緣區域之表面積的比例及/或具有較薄的介電質， 在本處理開始時亦即該導電性供應導體、該輔助導體軌道 -11- 513814 五、發明説明（10) 、及另一導電性供應導體耦合在一起時所產生的帶電載子 ’會藉由該半導體元件於電漿蝕刻處理期間消散到另一 絕緣區域的更大範圍之內。於另一介電質內，因爲已放大 的活性介電表面及/或因爲較薄的介電質而明顯地減小了 由該絕緣區域內之帶電載子對介電質造成的損壞。 本發明特別適合用於測試半導體元件，或者換句話說特 別有利的是該半導體元件具有用於測試半導體配置的半導 體測試結構。 · 不過，吾人應該注意的是本發明會適用於任何必要的電 路且能夠據此應用本發明。 在用於製造半導體元件的方法中，係將一電氣活性區域 配置於基板之內或之上。將包括介電質的絕緣區域加到該 電氣活性區域上，然後再將一導電區域加到該絕緣區域上 。形成連接於該導電區域上的導電性供應導體。此外，形 成配置在與該導電性供應導體相鄰處的導電性輔助導體軌 道’其方式是使其中至少某一區域係高度地攙雜了具有第 一導電型式的攙雜原子且係連接於該導電性輔助導體軌道 上。 根據本發明，能夠將任何必要數目的導電層且因此將任 何必要數目的供應導體互相配置於其上方且使之依電氣方 式耦合於個別的導電區域例如閘極區域上。 據此，於某些例子裡任何必要數目的導電性供應導體， 同時於部分電路區域內與個別高攙雜區域一起使用的很多 導電區域，都可能是相互耦合的；雖則在每一個例子裡都 -12- 513814 五、發明説明（u) 提供有至少一個在完成電漿蝕刻處理之後不具任何功能的 輔助導體軌道，然而於該電漿蝕刻處理期間特別是在該電 漿蝕刻處理開始時，該輔助導體軌道仍然會耦合於引導到 各導電區域上的個別導電性供應導體上。 吾人也能夠使各導電區域相互間於電漿蝕刻處理期間依 這種方式保持電氣連接，結果會將其他額外的各輔助導體 軌道（較佳的是小於該輔助導體軌道）結合在各現有的各導 電性供應導體之間。 因此，本發明突出地提供了各種結構或電路，不僅適用 於測試亦即晶片測試的領域且甚至會適用於晶片製造的領 域。 根據本發明，可以將不具任何功能的輔助導體軌道（依 類似於結構工程的方式而繪製的）當作損耗的結構產品， 亦即根據本發明所形成或提供的元件只有在製造期間具有 功能，但是在完成該半導體元件之後就不再具有任何功 會巨。 圖式簡單說明 以下將參照各附圖詳細地解釋本發明的各解釋用實施 例。 於各附圖中，完全相同的元件係提供有完全相同的符 號。 第1圖係用以顯示一種根據本發明第一解釋用實施例之 半導體元件的示意圖。 第2a到2d圖係用以顯示一種根據本發明第一解釋用實 -13- 513814 五、發明説明（12) 施例之半導體元件在電漿蝕刻處理期間的不同時刻的示意 圖，該電漿蝕刻處理係用來將金屬層製作成圖形並將導電 性供應導體形成於某一導電區域上。 第3圖係用以顯示一種根據本發明第二解釋用實施例之 半導體元件的示意圖。 第4圖係用以顯示一種根據本發明第三解釋用實施例之 半導體元件的示意圖。 較佳實施例的詳細說明 第1圖顯不的是一種根據本發明第一解釋用實施例之半 導體元件100。 該半導體元件1 00係含有：矽基板丨〇丨，係P _攙雜有硼 原子（1015cm‘3到l〇"cm 3);位阱ι15，係p-攙雜有硼原 子（1016cm·3到l〇igcm·3 );源極區域1〇2，係〆-攙雜有 砷或磷原子（10iycm_3到102lcm_3);以及汲極區域1〇3 ，係η、攙雜有砷或磷原子（1〇、^到1〇21cm_;)。該 源極區域1 02及該汲極區域1 〇3係形成於該p _位阱1 i 5 內。 其上塗覆有介電質當作絕緣區域丨〇 5內之絕緣材料的通 路區域1 04係形成於該源極區域1 〇2與該汲極區域丨〇3之 間。 根據本發明具體化之實施例，二氧化矽係爲最佳之介電 質。 可替代地，較佳的是使用下列材料當作介電質； •一氧化氮（NO )， -14- 513814 五、發明説明（13) •〇N〇結構（氧化物-氮化物-氧化物結構）， •氮化矽（Si3N〇， •高-k介電質， •包括互相配置於其上之不同高-k介電質的堆疊結構。 閘極區域106係配置於該絕緣區域105上，且部分閘極 區域會延伸而覆蓋住該絕緣區域1 05。該閘極區域係由攙雜 有濃度爲102°cnT3到1021ciir3之磷原子的多晶矽形成的。 該閘極區域106係經由塡充有鎢的接觸孔107而與由鋁 形成的導電性供應導體108達成電氣耦合，且係配置於配 置在該閘極區域106上方之處理平面內。 在與該導電性供應導體108相鄰處亦即落在與該導電性 供應導體相同處理位準內，存在有一個在電路的真實迴路 上不具任何功能且在此一解釋用實施例中同樣係由鋁構成 的的輔助導體軌道109。 該輔助導體軌道109係經由包括鎢之第一輔助接觸孔110 而耦合於配置在基板101內且係P+-攙雜有硼原子（1019cnT3 到1 021 cm 3)的電氣高攙雜區域111上。因此，能夠使帶電 電荷（正或負）亦即於電漿蝕刻處理期間在該導電性供應導 體、閘極區域、以及該輔助導體軌道上所累積的電子經由 該第一輔助接觸孔110而消散到該高攙雜區域111之內。 如第1圖所示，吾人能夠使用一種選用或替代的各接觸 組態，其中含有第二高攙雜區域113及第二輔助接觸孔112 及/或第三高攙雜區域116及第三輔助接觸孔117及/或第 -15- 513814 五、發明説明（14) 四高攙雜區域1 1 8及/第四輔助接觸孔1 1 9，且也可能含有實 際上將要形成於該電路之內的預定迴路功能，而給出較佳 的取用性。這類替代式接觸組態的保護作用會受到下列事 實的影響，取決於其電荷極性在各例中都存在有於放電電 流路徑上沿著向前方向或是沿著阻斷方向的pn二極體。 根據本發明提供了具有與基板相同導電型式的高攙雜區 域，能夠同時使可以由電漿蝕刻處理產生的負及正電荷消 散到基板1 0 1之內且因此消散到該支撐材料之內，以致只 要該導電性供應導體108係耦合於該輔助導體軌道109 上，便能夠防止於電漿飩刻處理期間對介電質造成損壞。 此外如第1圖所示，配置於η-位阱114內之選用第三電 氣高攙雜區域116係ρ1 -攙雜有硼原子（1019cnT3到1021cnT3) ，且係經由包括鎢的該第三輔助接觸孔1 1 7而依電氣方式 耦合於該輔助導體軌道1 09上。另外，第1圖中存在有配 置於基板1 0 1內之η -位阱1 1 4外側的選用第四電氣高攙雜 區域118係η1 -攙雜有砷或磷原子（10l9cm 3到102lcnT3)， 且係經由包括鎢的該第四輔助接觸孔1 1 9而依電氣方式耦 合於該輔助導體軌道109上。 第2a到2d圖係用以顯示如何根據本發明於電漿鈾刻處 理期間減低該介電質上的負載。爲了淸楚的理由，於第 2a到2d圖中並未標示出位阱Π 4和1 1 5以及第三電氣高攙 雜區域1 1 6、第三輔助接觸孔1 1 7、第四高攙雜區域1 1 8、 及第四輔助接觸孔Π 9 ’且在任何例子裡都是屬於選用的。 首先，使用各習知處理步驟以製造出如第2a圖所示的結 -16- 513814 五、發明説明（15) 構。 . 其內藉由塡充鎢形成有接觸孔1 07的電氣絕緣層20 1係 配置於該閘極區域1 06上方。 例如藉由噴灑法、澱積法、或氣相澱積法將由鋁構成的 金屬層202塗覆於該電氣絕緣層20 1上，如同以下所作的 更詳盡解釋，藉著電漿蝕刻作用由金屬層202形成了該導 電性供應導體及該輔助導體軌道。 藉由光刻技術製作成圖形的光阻層203係塗覆於該金屬 層202上，此光阻層203之圖形製作方式是藉由隨後使用 的電漿蝕刻處理去除將要露出該金屬層202的各區域。 第2b圖顯示的是第2a圖中的結構在已開始施行電漿蝕 刻處理之後很短時刻上所觀測到的情形。 根據此一解釋用實施例，因爲該電漿蝕刻處理的處理特 徵而假定曝露在處理氣體中的非常大之露出面積204和2〇5 會依比非常小之露出面積206和207更快的速率被蝕刻掉。 從苐2a圖可以看出，該已製作成圖形的光阻層203之圖 形製作方式，係以對應到該半導體元件之製程用處理法之 最大處理解析度（最小器件尺寸）的距離F，使得用來覆蓋 將要形成之導電性供應導體1 〇 8的各區域與該輔助導體軌 道1 09作互爲相鄰的配置，根據本解釋用實施例該距離爲 0.25微米。 第2 b圖顯示的是於電漿蝕刻處理期間的半導體元件。 第2b圖顯示的是如同文獻[2 ]中所說明的，能夠藉由蝕 刻氣體依比非常小的露出區域206和207更快的速率將非 -17- 513814 五、發明説明（16) 常大的露出區域204和205蝕刻掉。 於第2b圖中，這意指在相當處理時間之後亦即各露出區 域204、20 5、206、和207已接觸到電漿期間，該金屬層 202上具有非常大表面積的第一露出區域204和205會比具 有非常小表面積的第一露出區域206和207回蝕得更多。 最後，第2c圖顯示的是已將該金屬層上非常大的第二露 出區域204和205完全蝕刻掉時的半導體元件。 從第2c圖可以看出，此時仍然有存在於將要形成之導電 性供應導體108與該輔助導體軌道109之間的金屬亦即導 電性耦合作用，以致該閘極區域1 06、該導電性供應導體 108、及該輔助導體軌道1 09上所累積的帶電載子，能夠經 由引進高攙雜區域1 1 1和1 1 3內的第一輔助接觸孔1 1 0和 第二輔助接觸孔112消散到該基板101之內。 第2d圖顯示的是在已結束該電漿蝕刻步驟此外也已將不 含光阻材料的部分金屬層202去除掉之後已完全處理的半 導體元件100。 因此於這種狀態中，仍然存在的只有該導電性供應導體 1 08和該輔助導體軌道1 09，且現在其相互間係呈電氣去耦 合的。 第3圖顯示的是一種根據本發明第二解釋用實施例之半 導體元件300。 於P-攙雜有硼原子（l〇l5cm —3到10l7cnT3)的矽基板301 內形成第一場效電晶體302，亦即形成了含有η 1 -攙雜有 砷或磷原子（1019cnT3到1021cnT3)之源極區域303以及同 -18- 五、發明説明（n) 地n+-攙雜有砷或磷原子（1019cnT3到1021cnT3)之汲極區域 3〇4而p-攙雜有硼原子（1016cm_3到1018cm·3)的位阱313。 通路區域305係配置在該源極區域303與該汲極區域304 之間。該源極區域303和該汲極區域304皆係形成於該p-位阱3 1 3內。 包括二氧化矽306的閘極介電質係塗覆於該通路區域3 05 上方，包括多晶矽而高度攙雜有磷原子（102GCnT3到 1021cnT3)且其上套有由多晶矽製成的導電性供應導體308 的閘極區域307則係塗覆於該閘極介電質上。 輔助導體軌道309係落在與該導電性供應導體308相同 的處理位準上，且再次係以一最小距離換句話說以對應到 最小器件尺寸的距離，配置在緊鄰該導電性供應導體308 處。 此外，根據本發明第二解釋用實施例之半導體元件300 ，存在著含有另一絕緣區域3 11而由介電質（根據此一解 釋用實施例係二氧化矽）製成的輔助介電結構310，且其上 塗覆有另一閘極區域312(—般而言指的是另一導電區域 3 12)〇 輔助介電結構3 10可能是一種於實際電路中不具任何功 能且只用來接收帶電載子的結構，且可以據此依與該活 性介電質表面積相關的方式加以放大，或者可能是一種 提供有具相同或更薄厚度之介電質的電晶體。 根據此一解釋用實施例，該另一絕緣區域311上塗覆有 -19- 513814 五、發明説明（18) 另一閘極區域3 1 2的表面是比該絕緣區域306上塗覆有該 第一場效電晶體302之閘極區域307的表面大了 1 000倍。 根據本發明第二解釋用實施例，於依與如第2a到2d圖 所示之類似方式施行的電漿蝕刻處理期間（因爲這個理由不 再作更詳盡的解釋），於開始施行該電漿蝕刻處理時，會 在該場效電晶體亦即該輔助導體軌道309的閘極區域307 與該輔助介電結構3 1 0的絕緣區域3 1 1之間存在有電氣耦 合作用。此時，由電漿累積在該導電性供應導體上的各帶 電載子，基本上會藉由該輔助介電結構3 1 0而消散掉。 如同第一解釋用實施例一般，根據本發明第二解釋用實 施例該電氣耦合作用只會在逼近電漿蝕刻步驟終點時被打 破’且只有在那之後不再能夠使各帶電載子經由該輔助導 體軌道309消散到該輔助介電結構3 1 0之內。 第4圖係用以顯示一種根據本發明第三解釋用實施例之 半導體元件400的平面圖示。 該半導體元件400係含有複數個相互作緊鄰配置的電晶 體，且每一個電晶體都含有閘極區域以及其組成爲高度攙 雜有多晶矽之金屬或金屬合金的相關閘極供應導體40 1。 各電晶體的源極/汲極區域402配置在兩個閘極之間或是該 相關閘極供應導體401上。 來自於閘極供應導體40 1之最小距離（最小器件尺寸）F 具有輔助導電軌道4 0 3 ’依類似於根據本發明第一解釋用 實施例之半導體元件1 〇〇的方式使各電晶體的源極/汲極 區域402耦合於各高攙雜區域上，且能夠經由各高攙雜區 -20- 513814 五、發明説明（19) 域使各帶電載子消散掉。可替代地’如同根據本發明第二 解釋用實施例之半導體元件300，可以經由另一介電質而 配置輔助導體軌道403。 此外，於每一個例子裡係將各額外輔助導體軌道404配 置在兩個閘極區域之間或是該相關閘極供應導體40 1上。 在開始施行該電漿蝕刻處理時，使各額外輔助導體軌道 404依電氣方式耦合於兩個緊密相鄰的閘極供應導體401 上，以致由各閘極供應導體401、各額外輔助導體軌道 404、及該輔助導體軌道403形成一個共同的導電層。 在開始該電漿蝕刻步驟之前對該共同的導電層施行的 圖形製作的施行方式，是在結束該電漿鈾刻步驟之後將 各額外輔助導體軌道404配置在各例中離開某一閘極供應 導體401或是該輔助導體軌道403最小距離F以外。 淸楚地此一解釋用實施例指的是不再需要於該半導體元 件內提供連續的輔助導體軌道，而是能夠使用在某些例子 裡已存在於該電路內之導體軌道當作各額外輔助導體軌道 404，以便使該輔助導體軌道403上的帶電載子經由該輔助 導體軌道403消散到各高攙雜區域之內或是消散到其他介 電質之內。 於下文中，吾人將要說明的是對上述解釋用實施例作一 些改變的情形。 吾人應該注意的是該輔助導體軌道的結構不需要依輔助 導體軌道109和309的方式設計成使其走向平行於該導電 性供應導體。理論上也可以依任意方式形成該輔助導體軌 道109和309，雖則較佳的是至少將部分的輔助導體軌道 -21- 513814 五、發明説明（20) 1 09和309配置在離開該導電性供應導體某_•最小距離處。 根據本發明，吾人也能夠針對連接線也就是說各閘極區 域上的供應導體以及連接其上的各元件，減小由電氣充電 作用所造成的電漿-誘發損壞。 本文中吾人應該注意的是，根據本發明能夠使各例中許 多（理論上是任何必要數目的）至少局部地配置在介電質上 方的導電性供應導體只與一個輔助導體軌道呈電氣耦合， 然後能夠使所產生的全部帶電載子經由該輔助導體軌道， 消散到許多閘極區域內的高攙雜區域之內或是消散到某--輔助介電結構之內。 若將上述根據本發明某一解釋用實施例之半導體元件用 於某一測試結構內，此元件會確保吾人能夠非常準確地定 出由電漿-誘發損壞對具有天線之電晶體造成的降解作用 ，且吾人也能夠避免對電晶體亦即用來量測各電晶體參數 之各電晶體上的介電質造成破壞。 此外，吾人能夠在利用配置於某一供應導體兩側上各輔 助導體軌道之間的距離F(最小器件尺寸）時改良該半導體 結構本身的映射準確度。 另外吾人應該注意的是，在使用根據本發明的輔助導體 軌道時，可能在沒有去耦合二極體下使各表面之間的直接 接點有受到充電的危險，且此例中於由充電作用造成電 漿-誘發損壞期間各損壞性帶電載子的極性是無關的，亦 即能夠使電子以及來自正離子的電荷兩者獲致消散，這是 不同於根據習知設計使用保護二極體時的情形。 -22- 五、發明説明（21) 此外根據本發明，吾人能夠於個別金屬化位準或是某一 多晶矽位準內提供其他不具任何功能的塡充結構，亦即提 供任何必要而不具任何功能的導體軌道結構，因爲各輔助 導體軌道1 09和309不會扮演著受到電漿充電之表面的角 色。 另外根據本發明，吾人能夠提供一種導體軌道橋接結構 ’如同文獻[2 ]中所說明的。這種型式的額外導體軌道橋 接結構會允許吾人更進一步減小由電漿造成的充電作用。 總言之，很淸楚地能夠將本發明看作是與下列事實一致 的，於測試結構甚至是產品設計圖中或者依更一般化的 形式於半導體元件中，係將呈平行走向且一般而言係互爲 相鄰的各輔助導體軌道引導到至少一個閘極區域上或是其 上邊電極的導電性供應導體上，並在它們之間提供落在所 有供應導體上的最小距離。 用來形成各導體軌道的各金屬化位準皆係連接於該基板 上。使不允許基板連接的各導體軌道位準連接到配置於閘 極上方各完全相同半導體元件的電極上，該閘極係包含具 有相同或更薄厚度的各介電質，且其活性介電表面是將要 接受保護之半導體元件表面的數倍大。 此外，能夠在將要接受保護的結構與該基板的各高攙雜 區域之間提供一溝渠，藉由此溝渠使各高攙雜區域與將要 接受保護的結構（例如與場效電晶體或是電容器）達成更好 的電氣絕緣。較佳的是該溝渠的深度至少會對應到該基板 內各高攙雜區域的深度或是該基板內將要接受保護之結構 -23- 513814According to an alternative configuration of the present invention, another electrically active region is disposed in or on the substrate, and another insulating region including a dielectric is disposed on the other electrically active region, wherein the dielectric It may be exactly the same as the dielectric constituting the insulation region or it may be a different dielectric. According to the configuration of the present invention, another conductive region which is electrically coupled with another conductive supply conductor is disposed on another insulating region. Another conductive region is disposed on the other insulating region, and the size of the surface is equal to or larger than the size of the surface on which the conductive region is disposed on the insulating region. Depending on the space available, the ratio of the surface area (surface area of the insulation area) of another insulation area may be a multiple of up to 1,000. Alternatively or additionally, the thickness of another insulating region, that is, the thickness of another dielectric, may be selected to be smaller than the thickness of the insulating region, even if the thickness of the dielectric is protected. I very clearly, a semiconductor device provided according to this configuration of the present invention has the same structure but increases the ratio of the surface area of another insulating region to the surface area of the insulating region and / or has a thinner dielectric. Electricity, which is the charged carrier generated when the conductive supply conductor, the auxiliary conductor track-11-513814, the description of the invention (10), and another conductive supply conductor are coupled together at the beginning of this process. The semiconductor element is dissipated to a larger range of another insulating region during the plasma etching process. In another dielectric, damage to the dielectric caused by charged carriers in the insulating region is significantly reduced because of the enlarged active dielectric surface and / or because of the thinner dielectric. The present invention is particularly suitable for testing a semiconductor element, or in other words, it is particularly advantageous that the semiconductor element has a semiconductor test structure for testing a semiconductor configuration. · However, I should note that the present invention will be applicable to any necessary circuits and can be applied accordingly. In a method for manufacturing a semiconductor element, an electrically active region is disposed in or on a substrate. An insulating region including a dielectric is added to the electrically active region, and then a conductive region is added to the insulating region. A conductive supply conductor connected to the conductive region is formed. In addition, a conductive auxiliary conductor track 'formed adjacent to the conductive supply conductor is formed in such a manner that at least one of the regions is highly doped with dopant atoms having a first conductivity type and is connected to the conductivity. On auxiliary conductor track. According to the invention, it is possible to arrange any necessary number of conductive layers and therefore any necessary number of supply conductors above each other and to electrically couple them to individual conductive regions such as gate regions. According to this, in some examples, any necessary number of conductive supply conductors, and many conductive areas that are used together with individual highly doped areas in some circuit areas, may be coupled to each other; although in each example- 12- 513814 V. Description of the invention (u) At least one auxiliary conductor track which has no function after the completion of the plasma etching process is provided. However, during the plasma etching process, especially at the beginning of the plasma etching process, the auxiliary The conductor tracks will still be coupled to individual conductive supply conductors that are guided to the various conductive areas. We can also keep the conductive areas electrically connected to each other during the plasma etching process in this way, as a result, other additional auxiliary conductor tracks (preferably smaller than the auxiliary conductor tracks) will be combined with each of the existing ones. Conductive supply between conductors. Therefore, the present invention prominently provides various structures or circuits, which are applicable not only to the field of testing, that is, wafer testing, but even to the field of wafer manufacturing. According to the present invention, an auxiliary conductor track (drawn in a manner similar to structural engineering) without any function can be regarded as a lossy structural product, that is, a component formed or provided according to the present invention has a function only during manufacture, However, after the completion of the semiconductor device, it will no longer have any great achievements. Brief Description of the Drawings Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings. In the drawings, identical components are provided with identical symbols. Fig. 1 is a schematic view showing a semiconductor device according to a first embodiment of the present invention. Figures 2a to 2d are schematic diagrams showing a semiconductor device according to the first explanation of the present invention at 13-513814. V. Description of the Invention (12) The semiconductor device of the embodiment at different times during the plasma etching process, the plasma etching Processing is used to pattern the metal layer and form a conductive supply conductor on a conductive area. Fig. 3 is a schematic view showing a semiconductor device according to a second embodiment of the present invention. Fig. 4 is a schematic view showing a semiconductor element according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 shows a semiconductor element 100 according to a first explanatory embodiment of the present invention. The semiconductor device 100 contains: a silicon substrate 丨 〇 丨, which is doped with boron atoms (1015 cm'3 to 10 " cm 3); and potential well ι15, which is doped with boron atoms (1016 cm · 3 to lOigcm · 3); the source region 102 is doped with arsenic or phosphorus atoms (10iycm_3 to 102lcm_3); and the drain region 103 is doped with arsenic or phosphorus atoms (10, ^ To 1021cm_;). The source region 102 and the drain region 103 are formed in the p_bit well 1 i 5. A via region 104 which is coated with a dielectric material as an insulating material in the insulating region 105 is formed between the source region 102 and the drain region 101. According to an embodiment of the present invention, silicon dioxide is the best dielectric. Alternatively, it is preferable to use the following materials as the dielectric; • Nitric oxide (NO), -14- 513814 V. Description of the invention (13) • Ono structure (oxide-nitride-oxide Structure), • silicon nitride (Si3N0, • high-k dielectric, • a stacked structure including different high-k dielectrics disposed on each other. The gate region 106 is disposed on the insulating region 105 Part of the gate region will extend to cover the insulating region 105. The gate region is formed of polycrystalline silicon doped with phosphorus atoms with a concentration of 102 ° cnT3 to 1021ciir3. The gate region 106 is filled with thorium The contact hole 107 of tungsten is electrically coupled with the conductive supply conductor 108 formed of aluminum, and is arranged in a processing plane disposed above the gate region 106. It is adjacent to the conductive supply conductor 108, that is, Within the same processing level as the conductive supply conductor, there is an auxiliary conductor track 109 that does not have any function on the actual circuit of the circuit and is also made of aluminum in this explanatory embodiment. The auxiliary conductor Orbit 109 The first auxiliary contact hole 110 including tungsten is coupled to the electrical high doped region 111 which is disposed in the substrate 101 and is doped with boron atoms (1019cnT3 to 1 021 cm 3). Therefore, a charged electric charge (positive or Negative) That is, the electrons accumulated on the conductive supply conductor, the gate region, and the auxiliary conductor track during the plasma etching process are dissipated into the highly doped region 111 through the first auxiliary contact hole 110. As shown in Figure 1, we can use an optional or alternative contact configuration, which includes a second high-doped region 113 and a second auxiliary contact hole 112 and / or a third high-doped region 116 and a third auxiliary contact hole 117 and / or -15-513814 V. Description of the invention (14) Four-high-doped region 1 1 8 and / or fourth auxiliary contact hole 1 1 9 and may also contain a predetermined circuit that will actually be formed in the circuit Function and give better accessibility. The protective effect of this type of alternative contact configuration will be affected by the fact that the polarity of the charge is present in each case along the discharge current path along the forward direction. Direction or along The pn diode in the blocking direction is provided. According to the present invention, a highly doped region having the same conductivity type as the substrate is provided, and the negative and positive charges that can be generated by the plasma etching process can be dissipated into the substrate 1 0 1 at the same time. Therefore, it is dissipated into the supporting material, so that as long as the conductive supply conductor 108 is coupled to the auxiliary conductor track 109, the dielectric can be prevented from being damaged during the plasma etching process. In addition, as shown in FIG. 1 It is shown that the third electrical high doped region 116 in the η-position well 114 is selected from the series ρ1-doped with boron atoms (1019cnT3 to 1021cnT3), and is electrically dependent on the third auxiliary contact hole 1 1 7 including tungsten. The mode is coupled to the auxiliary conductor track 109. In addition, in the first figure, there is a fourth electrical high doped region 118 series η1-doped with arsenic or phosphorus atoms (10l9cm 3 to 102lcnT3), which is arranged outside the n-potential 1 1 4 in the substrate 101. It is electrically coupled to the auxiliary conductor track 109 via the fourth auxiliary contact hole 1 1 9 including tungsten. Figures 2a to 2d are used to show how to reduce the load on the dielectric during the plasma uranium engraving process according to the present invention. For the sake of clarity, the potential wells Π 4 and 1 15 and the third electrical high impurity region 1 1 6, the third auxiliary contact hole 1 1 7, and the fourth high impurity region are not shown in the figures 2a to 2d. 1 1 8 and the fourth auxiliary contact hole Π 9 ′ are optional in any case. First, the conventional processing steps are used to produce the structure as shown in Figure 2a. 513-513814 V. Description of the Invention (15) Structure. An electrical insulating layer 20 1 in which a contact hole 107 is formed by thoriated tungsten is disposed above the gate region 106. For example, a metal layer 202 made of aluminum is coated on the electrical insulating layer 20 1 by a spraying method, a deposition method, or a vapor deposition method, as explained in more detail below. The layer 202 forms the conductive supply conductor and the auxiliary conductor track. A photoresist layer 203 made into a pattern by photolithography is coated on the metal layer 202. The pattern of the photoresist layer 203 is formed by using a subsequent plasma etching process to remove the metal layer 202 that will be exposed. Each area. Fig. 2b shows the structure observed in Fig. 2a in a short time after the plasma etching process has been started. According to this exemplary embodiment, because of the processing characteristics of the plasma etching process, it is assumed that the very large exposed areas 204 and 205 exposed to the processing gas will be faster than the very small exposed areas 206 and 207. Was etched away. It can be seen from the figure 2a that the patterning method of the patterned photoresist layer 203 is based on the distance F corresponding to the maximum processing resolution (minimum device size) of the processing method for the semiconductor device, so that The areas for covering the conductive supply conductors 108 to be formed are arranged adjacent to the auxiliary conductor track 1009, and the distance is 0.25 micrometers according to the embodiment of the present interpretation. Figure 2b shows a semiconductor device during a plasma etching process. Figure 2b shows that as explained in [2], non--17-513814 can be changed by the etching gas with very small exposed areas 206 and 207 at a faster rate. 5. Description of the invention (16) Often large The exposed areas 204 and 205 are etched away. In Fig. 2b, this means that after a considerable processing time, that is, while each of the exposed areas 204, 20 5, 206, and 207 has been in contact with the plasma, the first exposed area 204 with a very large surface area on the metal layer 202 And 205 will etch back more than the first exposed areas 206 and 207 with a very small surface area. Finally, Figure 2c shows the semiconductor device when the very large second exposed regions 204 and 205 on the metal layer have been completely etched away. It can be seen from FIG. 2c that at this time, there is still a metal coupling effect between the conductive supply conductor 108 and the auxiliary conductor track 109 to be formed, that is, the gate region 106, the conductivity The charged conductors accumulated on the supply conductor 108 and the auxiliary conductor track 1 09 can be dissipated through the first auxiliary contact holes 1 1 0 and the second auxiliary contact holes 112 in the high-doped regions 1 1 1 and 1 1 3. Into the substrate 101. Fig. 2d shows the semiconductor element 100 which has been completely processed after the plasma etching step has been completed and a portion of the metal layer 202 containing no photoresist material has been removed. Therefore, in this state, only the conductive supply conductor 108 and the auxiliary conductor track 10 09 still exist, and they are now electrically decoupled from each other. Fig. 3 shows a semiconductor element 300 according to a second explanatory embodiment of the present invention. A first field-effect transistor 302 is formed in a silicon substrate 301 in which P-doped with boron atoms (1015cm-3 to 1017cnT3), that is, a semiconductor containing η 1 -doped with arsenic or phosphorus atoms (1019cnT3 to 1021cnT3) is formed. Source region 303 and same as -18- V. Description of the invention (n) Ground n +-doped with arsenic or phosphorus atom (1019cnT3 to 1021cnT3), drain region 304 and p-doped with boron atom (1016cm_3 to 1018cm · 3 ) 的 bit well 313. The via region 305 is disposed between the source region 303 and the drain region 304. The source region 303 and the drain region 304 are both formed in the p-bit well 3 1 3. A gate dielectric including silicon dioxide 306 is coated over the via region 3 05. It includes polycrystalline silicon and is highly doped with phosphorus atoms (102GCnT3 to 1021cnT3) and is covered with a conductive supply conductor 308 made of polycrystalline silicon. The gate region 307 is coated on the gate dielectric. The auxiliary conductor track 309 falls on the same processing level as the conductive supply conductor 308, and is again arranged at a minimum distance, in other words, a distance corresponding to the smallest device size, immediately adjacent to the conductive supply conductor 308 . In addition, according to the semiconductor device 300 according to the second embodiment of the present invention, there is an auxiliary dielectric structure made of a dielectric material (the embodiment is based on silicon dioxide) containing another insulating region 3 11. 310, and it is coated with another gate region 312 (generally refers to another conductive region 3 12). The auxiliary dielectric structure 3 10 may be a type that does not have any function in the actual circuit and is only used for receiving. The structure of the charged carrier can be enlarged accordingly in a manner related to the surface area of the active dielectric, or it can be a transistor provided with a dielectric with the same or thinner thickness. According to the embodiment for this explanation, the other insulating region 311 is coated with -19-513814. V. Description of the invention (18) The surface of the other gate region 3 1 2 is coated with the first surface of the insulating region 306. The surface of the gate region 307 of the field effect transistor 302 is 1,000 times larger. According to the second explanatory embodiment of the present invention, during the plasma etching process performed in a similar manner as shown in Figs. 2a to 2d (the reason will not be explained in more detail for this reason), the plasma is started. During the etching process, there is an electrical coupling effect between the field effect transistor, that is, the gate region 307 of the auxiliary conductor track 309 and the insulating region 3 1 1 of the auxiliary dielectric structure 3 1 0. At this time, each of the charged carriers accumulated on the conductive supply conductor by the plasma is basically dissipated by the auxiliary dielectric structure 3 1 0. As with the first explanatory embodiment, according to the second explanatory embodiment of the present invention, the electrical coupling effect will only be broken when the end of the plasma etching step is approached ', and only after that, each of the charged carriers can no longer be passed through the The auxiliary conductor track 309 dissipates into the auxiliary dielectric structure 310. Fig. 4 is a plan view showing a semiconductor device 400 according to a third embodiment of the present invention. The semiconductor device 400 includes a plurality of transistors arranged next to each other, and each of the transistors includes a gate region and a related gate supply conductor 401 composed of a metal or a metal alloy highly doped with polycrystalline silicon. The source / drain region 402 of each transistor is disposed between two gates or on the relevant gate supply conductor 401. The minimum distance (minimum device size) F from the gate supply conductor 40 1 with auxiliary conductive tracks 4 0 3 ′ is similar to that of the semiconductor element 100 according to the first embodiment of the present invention. The source / drain region 402 is coupled to each of the highly doped regions and can dissipate each of the charged carriers through each of the highly doped regions-20-513814 V. Description of the Invention (19). Alternatively ', like the semiconductor element 300 according to the second embodiment of the present invention, the auxiliary conductor track 403 may be configured via another dielectric. Further, in each example, each additional auxiliary conductor track 404 is arranged between two gate regions or on the relevant gate supply conductor 401. When the plasma etching process is started, each additional auxiliary conductor track 404 is electrically coupled to two closely adjacent gate supply conductors 401, so that each gate supply conductor 401 and each additional auxiliary conductor track 404 are electrically coupled. And the auxiliary conductor track 403 form a common conductive layer. The patterning of the common conductive layer before the plasma etching step is performed is to arrange the additional auxiliary conductor tracks 404 in each case to leave a gate supply after the plasma uranium etching step is ended. The conductor 401 or the auxiliary conductor track 403 is outside the minimum distance F. This explanation clearly refers to the use of an embodiment to mean that it is no longer necessary to provide a continuous auxiliary conductor track in the semiconductor element, but that the conductor track already existing in the circuit can be used as additional assistance in some examples. The conductor track 404 is used to dissipate charged carriers on the auxiliary conductor track 403 into the highly doped regions or to other dielectric materials through the auxiliary conductor track 403. In the following, I will explain the case of making some changes to the above-mentioned explanation examples. I should note that the structure of the auxiliary conductor track need not be designed in such a way that the auxiliary conductor tracks 109 and 309 run parallel to the conductive supply conductor. Theoretically, the auxiliary conductor tracks 109 and 309 can also be formed in any way, although it is preferable to configure at least part of the auxiliary conductor tracks -21- 513814 V. Description of the Invention (20) 1 09 and 309 are disposed away from the conductive supply Conductor at a minimum distance. According to the present invention, we can also reduce the plasma-induced damage caused by the electrical charging effect on the connection lines, that is, the supply conductors on the gate regions and the components connected thereto. I should note in this article that according to the present invention, many (theoretically any necessary number) in each case the conductive supply conductor arranged at least partially above the dielectric can be electrically coupled with only one auxiliary conductor track, Then all of the generated charged carriers can be dissipated into the highly doped region in many gate regions or into some auxiliary dielectric structure through the auxiliary conductor track. If the above-mentioned semiconductor element according to an embodiment of the present invention is used in a test structure, this element will ensure that we can accurately determine the degradation effect of plasma-induced damage on the transistor with an antenna Moreover, we can also avoid causing damage to the transistor, that is, the dielectric on each transistor used to measure the parameters of each transistor. In addition, we can improve the mapping accuracy of the semiconductor structure itself when using the distance F (minimum device size) between the auxiliary conductor tracks arranged on both sides of a supply conductor. In addition, I should note that when using the auxiliary conductor track according to the present invention, the direct contact between the surfaces may be charged without the decoupling diode, and in this example, the charging effect The polarity of each damaging charged carrier during plasma-induced damage is irrelevant, that is, it can dissipate both the electrons and the charge from the positive ions, which is different from the conventional design when using a protective diode situation. -22- V. Description of the invention (21) In addition, according to the present invention, we can provide other non-functioning charge structures within an individual metallization level or a certain polycrystalline silicon level, that is, provide any necessary without any function Conductor track structure, because each auxiliary conductor track 109 and 309 will not play the role of the surface charged by the plasma. In addition, according to the present invention, we can provide a conductor track bridge structure ′ as described in reference [2]. This type of extra conductor track bridge structure will allow us to further reduce the charging effect caused by the plasma. In summary, the present invention can be thought of as being consistent with the fact that the test structure or even the product design drawing or the semiconductor device in a more general form will run parallel and generally Each of the auxiliary conductor tracks adjacent to each other is guided to the conductive supply conductor of at least one gate region or an upper electrode thereof, and a minimum distance between all the supply conductors is provided between them. Each metallization level used to form each conductor track is connected to the substrate. The level of each conductor track that does not allow the connection of the substrate is connected to the electrodes of each identical semiconductor element arranged above the gate, the gate system including the dielectrics having the same or thinner thickness, and the active dielectric surface thereof It is several times larger than the surface of the semiconductor element to be protected. In addition, a trench can be provided between the structure to be protected and each highly doped region of the substrate, by which the high doped region and the structure to be protected are reached (for example, with a field effect transistor or a capacitor). Better electrical insulation. It is preferable that the depth of the trench corresponds to at least the depth of the highly doped regions in the substrate or the structure to be protected in the substrate. -23- 513814
五、發明説明（22) n vi ..¾V. Description of the invention (22) n vi .. ¾
的深度，但是該溝咖深度也會作必要時穿透到該趣丨入 的Μ㈣1㈣，塡絲任何必要的電氣絕緣树料U 例如用來當作絕緣材料的一氧化矽。 ， 參考文獻 . 本發明參考了下列文件： U ]美國專利第6 , 〇 2 8 , 3 2 4號文件 [2 ]由賽門（P . Simon )、路斯基士（ j，_M . Luschi es )、莫 里（W. Maly)發表於 proceecjingS 〇f international Symposium on Plasma Process-1nduced Damage’s. 1 6 - 20,1999標題爲「用於超大型積體電路的天線比定 義（Antenna Ratio Definition for VLSI Circuits)」 的論文。 ， 符號之說明 100 .....半導體元件 101 .....矽基板 102 .....源極區域 103 .....汲極區域 104 .....通路區域 105 .....絕緣區域 106 .....閘極區域 107 .....接觸孔 108 .....導電性供應導體 1 09.....輔助導體軌道 110.....第一·輔助接觸孔 -24- 513814 21 五、發明説明（） 111 .....第一高攙雜區域 112 .....第二輔助接觸孔 113 .....第二高攙雜區域 114 .....η -位阱 115 .....ρ -位阱 116 .....第三高攙雜區域 117 .....第三輔助接觸孔 1 18.....第四高攙雜區域 1 19.....第四輔助接觸孔 20 1.....絕緣層 202 .....金屬層 203 .....光阻層 204 .....大型露出區域 205 .....大型露出區域 206 .....小型露出區域 207 .....小型露出區域 300 .....半導體元件 301 .....基板 302 .....場效電晶體 303 .....源極區域 304 .....汲極區域 305 .....通路區域 306 .....絕緣區域 307 .....閘極區域 -25- 513814 五、發明説明（24 ) 308 .....導電性供應·導體 309 .....輔助導體軌道 310 .....輔助介電結構 3 11.....介電質 312 ........另一閘極區域 313 .....p -位阱 400 .....半導體元件 401 .....閘極供應導體 402 .....源極/汲極區域 403 .....輔助導體軌道 404 .....額外的輔助導體軌道 -26-However, the depth of the ditch coffee will also penetrate to the interesting M㈣1㈣ when necessary, and reel any necessary electrical insulating tree material U, such as silicon oxide, which is used as an insulating material. References. The present invention refers to the following documents: U] US Patent No. 6, 028, 324 [2] by Simon (P. Simon), Luskis (J, _M. Luschi es) ), W. Maly published in proceecjingS 〇f international Symposium on Plasma Process-1nduced Damage's. 1 6-20, 1999 titled "Antenna Ratio Definition for VLSI Circuits ) ". Explanation of symbols 100 ..... semiconductor element 101 ..... silicon substrate 102 ..... source region 103 ..... drain region 104 ..... via region 105 ... .. Insulation area 106 ..... Gate area 107 ..... Contact hole 108 ..... Conductive supply conductor 1 09 ..... Auxiliary conductor track 110 ..... First · Auxiliary contact hole-24- 513814 21 V. Description of the invention (111) ..... First high impurity region 112 ..... Second auxiliary contact hole 113 ..... Second high impurity region 114 ... ... η-potential well 115 ..... ρ-potential well 116 ..... third high impurity region 117 ..... third auxiliary contact hole 1 18 ..... fourth high impurity Area 1 19 ..... Fourth auxiliary contact hole 20 1 ..... Insulation layer 202 ..... Metal layer 203 ..... Photoresist layer 204 ..... Large exposed area 205. .... Large exposed area 206 .... Small exposed area 207 .... Small exposed area 300 ..... Semiconductor element 301 ..... Substrate 302 ..... Field effect transistor 303 ..... source area 304 ..... drain area 305 ..... path area 306 ..... insulation area 307 ..... gate area-25- 513814 V. Invention Explanation (24) 308 ..... Conductive supply · Conductor 309 ..... Auxiliary conductor track 310 ..... Auxiliary dielectric structure 3 11 ..... Dielectric 312 ..... Another gate region 313 ..... p- Potential well 400 .... semiconductor element 401 ..... gate supply conductor 402 ..... source / drain region 403 ..... auxiliary conductor track 404 ..... additional auxiliary Conductor track-26-