TW513796B - A scalable stacked gate flash memory device and the manufacturing method of high-density array - Google Patents

Abstract

A scalable stacked-gate flash memory device and the manufacturing method of high-density array are provided. It utilizes four kinds of spacer technologies to produce a scalable stacked-gate flash memory device. The first spacer technology is used to form a buffering oxide spacer to be the channel stop of STI (shallow trench isolation) implantation without sacrificing the width of active region of the non-volatile memory device during oxidizing the etched surface of the shallow trench. The second spacer technology uses a shallow trench isolation method to produce a self-aligned floating gate whose coupling ratio can be largely modulated and then the external control voltage for writing and erasing can be reduced. The third spacer technology is used to define the gate length of the scalable stacked-gate structure. The fourth spacer technology is used to form sidewall spacers for ion implantation of self-aligned source/drain diffusion region, salicide formation of the self-aligned source/drain diffusion areas or the common buried source area and self-aligned contact formation. The scalability of this invention is that the channel length of the stacked-gate flash memory device can be modulated to let the minimum length smaller than the applying technology and let the existing different types of flash memory structure, such as NOR and NAND to obtain the high-density stacked-gate flash memory device array. Accordingly, the scalable stacked-gate flash memory device can be used to manufacture the high-density, high-speed, low-voltage and low-power flash memory array and system required by massive storage applications.

Description

513796 A7 B7 V. Description of the invention () Background of the invention: (1) The scope of the invention The invention relates to general flash memory devices, especially to ultra-high density, high speed, low voltage and low power stacked gate type (stacked-gate) Flash memory elements are related to their memory element arrays. (2) Description of the conventional technology Flash memory devices are known to use Fowler-Nordheim tunneling or hot carrier injection to pass charges from a semiconductor substrate or across a thin dielectric layer to a Isolation gate (commonly known as floating gate) and stored therein, and the charge stored in the isolation gate is transferred or scrubbed to the semiconductor substrate or control gate by the Fuller-Nordheim penetration method. Basically, the memory cell must be reduced to facilitate high-density and large-scale storage applications, and the device structure needs to be oriented toward low voltage, low current, and high-speed operation, and has both high endurance and retention. A stacked flash memory device in a conventional flash memory array is shown in FIG. 1, where FIG. 1A shows a structural cross-sectional view in the length direction of the channel; FIG. 1B shows a structural cross-sectional view in the width direction of the channel; Figure 1C shows a top plan view of a NOR-type configuration. The stacked gate flash memory device shown in FIG. 1A includes a P-type semiconductor substrate 100 and a P-well 101 formed in the P-type semiconductor substrate. A thin penetrating oxide layer 102 is placed on the surface of a P-well 101 with a thickness of about 100 angstroms. A polycrystalline silicon layer 103 is placed on top of a thin penetrating oxide layer 102 as a floating gate, using silicon dioxide-3 This paper is sized for China National Standard (CNS) A4 (210X297 mm)-f (please first (Please read the notes on the back and fill in this page.) Order · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513796 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 The structure is used as the inter-gate dielectric layer between the floating gate 103 and the control gate 105. The control gate can be a highly doped polycrystalline silicon layer or a highly doped polycrystalline silicon layer covered with silicide. The source diffusion region 106 may be a highly doped η- region, and the drain diffusion region 107 may be a double-diffusion structure in which the low-doped η- region is placed in the highly doped η- region to reduce the band pair generated during scrubbing. Band-to-band tunneling effects. It can be clearly seen from Figure 1A that the gate length of a stacked gate structure is mainly limited by the minimum width (λ) of the technology used, and the minimum width (λ) is mainly limited by the photo-etching technology. However, the distance between components (λ 1) is usually larger than the minimum width (λ) because of the relationship between the contacts, that is, == + 2 △ λ ′. Therefore, the equivalent length of each cell is about 2λ (1 + Δ λ, / λ) > 2λ. Furthermore, only when the gate length λ is reduced, the external source-to-drain (usually grounded) voltage required for the hot electrons generated during writing can be reduced, and the coupling ratio of the floating gate can only be increased It can reduce the control gate voltage applied during writing. Similarly, the coupling ratio of the floating gate also plays an important role in reducing the voltage applied to the scrubbing of the charge stored in the floating gate to the P well or the control gate. The coupling ratio of a stacked gate flash memory element can be improved by the isolation structure in the channel width direction. FIG. 1B shows a typical shallow-trench-isolation technology of the high-density stacked flash memory array in the channel width direction, in which the silicon dioxide is oxidized at P before the silicon dioxide layer is not filled. A thin thermal silicon dioxide layer 108 is formed on the surface of the well 101 by etching the single crystal silicon groove. Floating gate 103 is defined by photoetching so that it extends Δ λ above the IS departure zone 'to increase the coupling ratio of floating. Obviously, the width of the isolation zone λ " must be equal to or greater than A + 2Δ λ ", and 4 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm), ... .. # ......... Order ......... Line · (Please read the notes on the back before filling this page) 513796 A7 B7 V. Description of the invention () (Please read first Note on the back page, please fill in this page again) That is; 1 ·· $; 1 + 2Δ and '', then the equivalent width of each cell is 2 (λ + Δ λ ''). For a NOR type configuration, as shown in Figure 1C, the equivalent area of each cell is 4λ2 (1 + Δ; 1 "/; 1) (1 + Δ λ7λ). Furthermore, the tolerance of the photolithography of the floating gate to incorrect alignment will produce different coupling ratios between different wafers and asymmetric isolation of components. It can be clearly seen here that the coupling ratio of the floating gate in Figure 1B is increasing, but the area of the equivalent cell is sacrificed. Paper ‘’ A 130-μη2, 256-Mbit N AND Flash with Shallow Trench Isolation by K. Imamiza et al.

Technology ", IEEE Jour, of Solid-State Circuits, Vol.34, No.ll, ρρ · 1536-1541, Nov. 1 999, which mentioned that the non-aligned floating gate is composed of two layers of polycrystalline silicon. λ = 0.25 microns, △ person " = 0.1 λ = 0.025 microns, △ '= 0.03 3 75 microns. Obviously, the asymmetry caused by the inaccurate alignment error of photolithography △ λ " It can be seen from the picture in the published paper. For automatic alignment of the floating gate, △ λ " = 0, the equivalent area of each cell can be reduced by 10%, and the floating gate is not accurately aligned. It can be eliminated automatically. For the manufacturing of the self-aligning floating gate and high coupling ratio printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to the following U.S. patent cases. And shallow groove isolation method, which uses a silicon nitride mask to remove the polycrystalline silicon floating gate covering the isolation region. This method has two important disadvantages: one is the planarization of the shallow groove After the formation of the isolation oxide layer ' In addition to the pad-oxide on the active area, the second is to remove the mask silicon nitride layer covering the polycrystalline silicon and the polycrystalline silicon covering the isolating oxide layer. Removing the pad oxide layer will cause isolation The change in the height of the oxide layer further created 5 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 513796 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Change in coupling ratio ( In addition, if it is removed by non-isotropic dry etching, the silicon surface of the active area and the corners of the isolation area will be etched, resulting in the growth of a poor silicon surface that penetrates the silicon dioxide layer and the shape of the isolation area. If wet etching is used, the upper and lower corners of the isolation area will be etched. Excessive engraving will cause voids to form in the lower corners of the isolation oxide layer. Insufficient etching will cause thin penetration of the silicon dioxide layer with uneven thickness. Similarly, removing the covered silicon nitride mask and the polycrystalline silicon covering the isolation oxide layer will cause the height of the extended floating gate of the side wall to change. Moreover, the polycrystalline silicon floating gate tip after etching will be changed. Irregular shapes will cause the problems of survivability and interference of stored charges due to field emission. Furthermore, the patented shallow groove isolation has no channel forbidden zone formation to eliminate unnecessary surface leakage. Another US patent number 5,770,50 1 According to the same method of US Patent No. 5,516,721, a liquid-phase deposition method is used to grow the isolation oxide in the middle of the formed photoresist. It is obvious that the etched surface of the shallow groove It is impossible to grow a thermal silicon dioxide layer to eliminate surface defects caused by shallow groove engraving. Furthermore, the height of the oxide deposited in the liquid phase is used to determine the coupling ratio of the auto-alignment to the floating gate, but it is difficult to control it using the liquid deposition method. The main deficiency presented in U.S. Patent No. 5,770,50 1 was corrected by U.S. Patent No. 6,153,472, in which a polycrystalline silicon underlayer was formed on the side wall of the planarized plutonium oxide, and the etched surface of the shallow groove with uranium The carved polysilicon side walls of the main floating gate are all oxidized. From this structure, it can be clearly seen that the thickness of the active area of the so-called flash memory element is reduced due to the bird's beak effect, which greatly increases the thickness of the two sides of the oxide layer. In addition, shallow groove isolation has no channel ban. 6 β-sheet scale is applicable to China National Standard (CNS) A4 specification (210x297 public love) ............ 夔 ........ .............. Line · (Please read the notes on the back before filling out this page) 513796 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Formation of the communication zone . According to the above description, the automatic alignment of the floating gate is a necessary method to reduce the isolation area, and the high coupling ratio of the automatic alignment of the floating gate is more important to improve the writing and scrubbing efficiency of the external control voltage. In addition, if the definition of the gate length of stacked gate flash memory elements is not limited by the minimum line width, the cell size and the applied source / drain voltage can be further reduced. Therefore, the main object of the present invention is to propose a method for manufacturing a shrinkable stacked gate flash memory device with a large modulation coupling ratio, so as to overcome the shortcomings of the past methods, and as a high density, high speed, low voltage and low For power storage. Summary of the Invention: The present invention discloses a method for manufacturing a shrinkable stacked gate flash memory element and a high-density memory array using four different underlayer technologies. The first underlayer technology of the present invention is used to form a buffer oxide underlayer, which is used as a channel forbidden region isolated by implanting shallow grooves and etched surfaces of oxidized shallow grooves without sacrificing non-volatile semiconductor memory elements. Active area width; the second cushion technology uses a shallow groove isolation method to drastically adjust the coupling ratio of the self-aligned floating gate, in which the thickness of the planarized plutonium-filled isolation oxide layer is equal to the first mask nitrogen After the thickness t of the siliconized layer is added to the thickness of the first polycrystalline silicon layer, a first polycrystalline sand cushion layer is formed on the side wall of the first masked silicon nitride layer and the first polycrystalline silicon layer after etching. Then, the first masked nitrided sand layer is automatically aligned and removed ', and then the first polycrystalline silicon layer formed, the first polycrystalline silicon cushion layer formed, and the etching are performed. The paper size applies to Chinese National Standard (CNS) A4. Specifications (210X297 mm) .........., ......... Line · (Please read the precautions on the back first (Fill in this page again) 513796 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The first dielectric layer was deposited on the oxide layer after filling. The first dielectric layer may be a composite layer composed of silicon dioxide-silicon nitride-silicon dioxide (ONO). Then, a second polycrystalline silicon layer is deposited and then a silicide layer is deposited to form a control gate. The coupling of the self-aligning floating gate of the present invention is greatly increased compared with the previous method, and the effective active area width λ is not affected by the formation of the forbidden zone of the channel isolated by the shallow groove and the oxidation of the surface of the etched groove. Therefore, the effective width of each cell is only 2λ, where λ is the smallest line width using the technology. The third underlayer technology of the present invention is to define the gate length ΔL of the stacked gate flash memory element by using the first silicon dioxide underlayer formed by the formed first mask polysilicon sidewall, and then etching The second mask silicon nitride layer is used as a hard mask for etching the silicide layer, the first polycrystalline sand layer, the first dielectric layer, the first polycrystalline sand pad layer, and the first polycrystalline silicon layer. Then, a thin first polycrystalline oxide layer is grown on the sidewall of the first polycrystalline silicon layer after the etching, the first polycrystalline silicon pad layer after the etching, and the second polycrystalline silicon layer after the etching. Then, arsenic impurities are automatically implanted and aligned across the first thermal silicon dioxide layer to form a mid-doped source / drain diffusion region of the stacked gate flash memory device. The fourth underlayer technology of the present invention is to form a thin silicon nitride underlayer on a side wall of a stacked gate structure for automatic alignment of highly doped source / drain ion implantation and automatic alignment of source / drain. Or the silicidation and self-aligned contact of the common buried source diffusion region. The equivalent length of each cell is only λ (1 + Δ L / λ), which is much smaller than the length of the stack-gate flash memory device defined by the smallest line width method used in the past. In terms of the common buried source N 0 R configuration, the equivalent area of each cell is only 2 λ 2 (1 + Δ L / λ). Obviously, △ L < λ can be easily obtained by the cushion formation technology. 8 paper sizes are applicable to China National Standard (CNS) A4 (210X297 mm) -... ... # ........., 玎 ......... line · (Please read the precautions on the back before filling out this page) 513796 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Description of the invention () The equivalent cell size can be much smaller than 4 λ 2 (when λ = △ L) and can be adjusted by the width of the cushion. In addition, because the gate length is smaller than the minimum line width used, the externally applied source-drain voltage can be reduced, and because of the extra-high coupling ratio of the automatic floating gate of the present invention, the applied control gate voltage can also naturally reduce. Similarly, the scrubbing voltage can be reduced across the control gate and the substrate. In summary, the manufacturing method of the miniaturizable stacked gate flash memory device of the present invention can be used to manufacture high-density, high-speed, low-voltage, and low-power flash memory arrays and systems for mass storage applications. Brief description of the figures: FIGS. 1A to 1C respectively show a partial cross-sectional view and a partial top plan view of a channel length direction and a channel width direction of a conventional stacked gate flash memory element array; FIG. 2A to FIG. 2C respectively discloses a partial cross-sectional view and a partial top plan view of a channel length direction and a channel width direction of the stacked gate flash memory element array of the present invention; FIGS. 3A to 3D respectively disclose the stack of the present invention Sectional view of the manufacturing process and structure of the gate-type flash memory element array with shallow groove isolation in the width direction; FIG. 4A to FIG. 4 show that the present invention simultaneously manufactures a miniaturizable stackable gate-type flash memory element array and complementary peripherals Process and structure of structural components 9 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) • '· ............ 0 ........ Order ......... line · (Please read the notes on the back before filling in this page) 513796 A7 B7 V. Description of the invention () ΓΞΓ Figures, Figures 5A to 5C reveal the invention at the same time Fabrication of a NOR-type miniaturized stacked gate flash memory element array and peripheral complementary elements FIG. 6A to FIG. 6B show the connection diagrams of the miniaturizable stacked gate flash memory element array and peripheral complementary elements of the present invention that simultaneously manufacture N AND type architectures. Four process and structure cross-sections. Description of drawing numbers: 20 monocrystalline silicon substrate 21a P well (memory element array) 21b η well (P-MOS) 21c P well (n-MOS) 22 First thermal silicon dioxide layer 23 First polycrystalline silicon layer 24 The first mask silicon nitride layer 25 forms a mask photoresist (a, ... q) 26 a first good coverage silicon dioxide layer 26a a first silicon dioxide underlayer 27 a second thermal silicon dioxide layer 28 Thick silicon dioxide film 29 First good coverage polycrystalline silicon layer 29a First polycrystalline silicon underlayer 30 First dielectric layer 31 Third thermal silicon dioxide layer 32 Second polycrystalline silicon layer 33 Silicide layer 34 Second mask silicon nitride layer 35 First mask polycrystalline silicon layer 36 Second good coverage silicon dioxide layer 37 Second silicon dioxide pad layer 38 Lightly doped P-source and drain diffusion region 39 Lightly doped η-Source and Diffuse Diffusion Zone 10 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 public love) ......... I (Read first, read back & ii) (cIfi-describe this page)-Order ·% Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 513796 A7 B7 V. Description of the invention () 40 moderately doped n + source and drain diffusion region 40a highly doped and buried together Layer Source Diffusion Zone 41 Sand layer 41a ~ Nitrided sand pad layer 42 Highly doped P + source and drain diffusion region 43 Highly doped n + source and drain diffusion region 43a Highly doped n + drain diffusion region 43b Highly doped n + source diffusion region 43c Highly doped common buried layer source diffusion region 44 Fourth thermal silicon dioxide layer 45 Silicon titanium layer 47 Thick dielectric layer 49 Tungsten layer 5 1 Interlayer dielectric layer 53 Protective dielectric layer 46 Titanium nitride layer 48 Thin Titanium nitride layer 5G Ml metal connection layer 52 M2 metal connection layer (please read the precautions on the back before filling out this page) Detailed description of the invention printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: Refer to Figure II A to Figure Two C, these three figures reveal the advantages of the present invention compared to FIGS. 1A to 1C. Figure 2A reveals that the present invention uses a cushion technology to define the gate length ΔL of a stacked gate flash memory element, and ΔL is smaller than the minimum line width λ of the technology used and can be adjusted through the cushion width. In addition, the silicon nitride pad 4 1 a is used as the ion implantation of the auto-aligned source / drain diffusion region of the stacked gate flash memory element to form the source / drain highly doped diffusion regions 43 a and 43 b or co-buried. The layer source diffusion region 43c (not labeled), the auto-aligned source / drain diffusion region, or the common buried source diffusion region is silicided to form an auto-aligned silicide 45 and an auto-aligned contact. FIG. 2B discloses the structure of the automatic alignment floating gate of the channel width direction of the present invention, wherein the automatic floating gate is composed of a first polycrystalline silicon layer 23 and two first polycrystalline sand cushion layers 29a placed on the isolation region λ. composition. 11 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 513796 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) The area of the invention's automatic alignment of the floating gate It is much larger than the previous technology, and the surface of the shallow groove is implanted with ions to form the forbidden area of the channel without sacrificing the area of the active area. FIG. 2C shows a partial top view of the stacked stack flash memory array of the N 0 R configuration according to the present invention. Compared with FIG. 1C, it shows that the present invention has a very small cell area, and thus a small composition area. Memory array. The manufacturing steps and sectional structures of these special technologies will be described later. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Referring to Figures 3A to 3D, these figures reveal the first part of the present invention. The first aspect of the present invention includes a method for manufacturing a channel-width shallow groove isolation structure of a stacked gate flash memory element array. In the P-type (100) single crystal substrate 20, the isolated P wells 21a and 21c and the isolated η well 21b are grown. The first thermal silicon dioxide layer 22 is grown to a thickness of about 70 angstroms to 110 angstroms. The growth condition is about Dry oxygen environment at 850 ° C. The P wells 21a, 21c and η well 21b can be isolated by using conventional local silicon oxide (LOCOS) or modified local silicon oxide (LOCOS) or the technology described in the first part of the present invention. Low-pressure chemical vapor deposition (LPCVD) method is used to thermally decompose silane at a temperature between 580 ° C and 65 (TC), and grow between about 300 angstroms and 1,500 angstroms. The first polycrystalline silicon layer 23 with a natural in-situ doped phosphorus (or boron) impurity concentration of about 1018 to 5x 1019 / cm3 is above the first thermal silicon dioxide layer 22. A low voltage is used. In the chemical vapor deposition method, dichoiorsilane and nitrogen are reacted at a temperature of about 720 ° C to deposit a first mask silicon nitride layer 24. The thickness ⑴ is used to control or adjust the flash memory device. The coupling of the floating gate uses the formed first screen photoresistor 25a to define the flash memory element array. 12 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 513796 A7 B7. 5. The channel of the invention description () The width is as shown in Fig. 3A. Anisotropically etching the first mask nitrided sand layer 24, the first polycrystalline sand layer 23 and the first thermal silicon dioxide layer 22, and then the formed first mask Photoresist 25 is removed. Using LPCVD method, the temperature of about 750 ° C to 850 ° C The teuaethoxysilane (TEOS) is thermally decomposed, and the first good covering silicon dioxide layer 26 with a thickness of about 200 angstroms to 500 angstroms is deposited, and then the first good covering silicon dioxide layer 26 is anisotropically etched. The carved side wall forms a first silicon dioxide pad layer 26a, as shown in Fig. 3B. Then, a portion of the single crystal silicon in the P well 21a is etched to a depth of about 2000 to 4000 Angstroms, and about 8 50 In the dry oxygen environment of ° C, the etched single crystal silicon surface of the P well 21a is oxidized, and a second thermal silicon dioxide layer 27 having a thickness of about 50 to 150 angstroms is grown on the single crystal silicon surface after the uranium etching. Then, a large-tilt-angle is used to implant boron impurities to form a shallow groove-isolated channel forbidden area. As can be seen from the figure, the first silicon dioxide pad layer 26a is used as a shallow groove isolation. The formation of the forbidden area of the channel and the buffer oxide pad layer that avoids the oxidation of the shallow grooves to the two sides of the first thermal silicon dioxide layer. The high-density plasma CVD method is used to silane ) Or tetraethoxysilane as the silicon source, fill the etched shallow grooves with a thick and good coverage Conformable sand dioxide film 28, and a chemical-mechanical-polishing (CMP) method is used to planarize the surface of the structure and remove the overfilling of the silicon nitride layer 24 beyond the first mask Silicon dioxide, as shown in Figure 3B. Then, the diluted silicon dioxide layer 28 is flattened with diluted hydrofluoric acid or buffered hydrofluoric acid or anisotropic etching, and the etching thickness is approximately equal to the thickness t of the first mask silicon nitride layer 24 plus the first complex. The thickness of the crystalline silicon layer 23. Then, use 13 paper sizes to apply Chinese National Standard (CNS) A4 specifications (210X297 mm) .............. I (Please read the precautions on the back before filling this page) Order · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513796 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) Low pressure chemical vapor deposition method, between 58 (TC to 650 ° C) The silane is thermally decomposed to a temperature of about 200 to 500 Angstroms, and the first well-covered polycrystalline silicon layer 29 is naturally doped with phosphorous (or boron). Next, anisotropically etched naturally doped phosphorus (or boron) 29 ) Of the first good polycrystalline silicon layer 29, the first polycrystalline silicon pad layer 29a is formed on the exposed side walls of the exposed first mask silicon nitride layer 24 and the first polycrystalline silicon layer 23. The wet Thermal phosphoric acid, the first mask silicon nitride layer 24 is removed, and then the first dielectric layer 30 is stacked, as shown in FIG. 3C. It should be noted here that the first dielectric layer 30 may be silicon dioxide. -Silicon nitride-silicon dioxide (ONO) composite layer or other composite dielectric layers. As can be seen from the figure, the first polycrystalline silicon pad formed by the present invention The bilateral area of 29a will greatly increase the coupling ratio of the self-alignment to the floating gate. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will use the formed second screen photoresistor 25b to cover all areas where flash memory arrays are to be manufactured. The non-isotropic dry etching is used to remove the first dielectric layer 30 and the first polycrystalline silicon 23 or the first polycrystalline silicon cushion layer 29a in other regions, as shown in FIG. 4A, and then the formed second mask is removed. Photoresist 25b. Then, using the formed third mask photoresist 25c (not shown), boron impurities are implanted across the first thermal silicon dioxide layer 22 into the single crystal silicon region of the P-well region 21c to adjust Threshold-voltage and punch-through voltage of all n-channel metal-oxide half-elements in the peripheral complementary metal-oxide half-elements, and then the formed third mask 25c is removed. The same The reason is to use the formed fourth mask photoresist 25d (not shown) to implant boron or phosphorus impurities across the first thermal silicon dioxide layer 22 into the single crystal silicon region of the n-well region 21b to adjust the peripheral complementarity. Criticality of all P-channel metal-oxide half-elements Voltage and withstand voltage, and remove the formed fourth mask photoresist 25d to 14 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 513796 A7 B7 V. Description of the invention () except (please first (Please read the notes on the back and fill in this page.) In the dry oxygen environment between 850 ° C and 1 050 ° C, the peripheral complementary metal-oxygen half-elements in the P well 21c and η well 21b single crystal silicon regions will be manufactured. The first thermal silicon dioxide layer 22 is oxidized to form a third thermal silicon dioxide layer 31, which has a thickness between about 2000 and 400 angstroms, as shown in FIG. 4B. It is worth mentioning here that the third thermal silicon dioxide layer 31 is mainly used as a gate dielectric layer of a peripheral complementary metal-oxide half-element. The low-pressure chemical vapor deposition method was used to thermally decompose the silane at a temperature between 5 80 ° C and 65 ° C, and a second polycrystalline silicon layer 32 having a thickness of about 1,000 to 2000 angstroms was deposited, and then a low-pressure chemical gas was used. A silicide layer 33 having a thickness of about 1,000 to 2,000 angstroms is deposited on the phases, as shown in Figure 3D of the channel width direction and Figure 4C of the channel length direction. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Then, a low-pressure chemical vapor deposition method is used to deposit a second mask silicon nitride layer 34 having a thickness of about 500 to 1000 Angstroms. Then, a low-pressure chemical vapor deposition method is used at 5 80 ° C to 65 ( The silane is thermally decomposed between TC temperature, and the first mask polycrystalline silicon layer 35 is deposited with a thickness of about 1000 angstroms to 2000 angstroms. The first mask polycrystalline silicon layer is etched with the formed fifth mask photoresist 25e. 35, to define the virtual gate length Lv (virtual gate length) of the stacked gate flash memory element, as shown in Figure 4D, where λ is the minimum line width of the technology used, and △ L is the stacked gate fast The gate length of the flash memory element. After removing the formed fifth mask photoresist 2 5 e, use a low voltage Using the vapor deposition method, tetraethylene oxysilane is thermally decomposed at a temperature between 700 ° C and 850 t, and a second good covering silicon dioxide layer 36 having a thickness of ΔL is deposited, followed by anisotropic Etching the second good covering silicon dioxide layer 36, and forming a second sand dioxide pad layer 37 (as shown in FIG. 4E) on the side wall of the first mask polycrystalline silicon layer 35 after the etching, and then Cover 15 This paper is in the size of China National Standard (CNS) A4 (210X297 mm) 513796 A7 B7 5. Description of the invention () The polycrystalline silicon layer 3 5 can be removed by anisotropic etching, as shown in Figure 4F (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, using the formed sixth cover photoresistor 25f to define the gate lengths of the n-channel and p-channel metal-oxygen half elements, as shown in the figure As shown at 4F, the second mask silicon nitride layer 34 is anisotropically etched and the formed second silicon dioxide pad layer 37 is removed, and then the silicide layer 33 and the second polycrystalline silicon are anisotropically etched. Layer 3 2, and then remove the formed sixth mask photoresist 25f. Anisotropically etch the flash memory cells in an automatic alignment manner The first dielectric layer 30 and the first polycrystalline silicon layer 23 of the device array. Then, in a dry oxygen environment of about 85 ° C., the first polycrystalline silicon layer 23 and the second polycrystalline silicon layer are etched. The side wall of 3.2 and the first polycrystalline silicon cushion layer 29a is oxidized to grow a thin first polycrystalline silicon oxide layer. Using a formed seventh mask photoresist 25g (not shown), boron impurities are automatically aligned across The third thermal silicon dioxide layer 31 is implanted into the single crystal silicon region of the η well 2 1 b to form a lightly doped source and a shallow diffusion region 38 of all P-channel metal-oxide half-elements, and then removed. The formed seventh mask photoresist is 25g. Similarly, using the formed eighth mask photoresist 25h (not shown), the phosphorous impurities are automatically aligned across the third thermal silicon dioxide layer 3 1 to be implanted into the single crystal silicon of P well 2 1 c. To form the lightly doped source and drain diffusion region 39 of all n-channel metal-oxide half-elements, and then remove the formed eighth mask photoresist 25h. The lightly doped implantation dose is between about 1013 and 1014 / cm2. Using the formed ninth mask photoresist 25i (not shown), the mid-doped source and drain diffusion region 40 of the stacked gate flash memory element cross the first thermal diode via the arsenic impurity. The silicon oxide layer 22 is implanted with single crystal silicon in P well 2 1 a to complete the implantation at a dose of about 1014 to 1015 / cm2, and then the formed ninth mask photoresist 25i is removed, as shown in the figure. Four Gs. Using low pressure chemical vapor deposition method, at a temperature between 65 ° C and 800 ° C. 16 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 513796 A7 B7 V. Description of the invention ( ) (Please read the notes on the back before filling out this page) The first reaction of silane and ammonia gas, the first good coverage silicon nitride layer 41 with a thickness of about 500 Angstroms to 1000 Angstroms, followed by anisotropic etching A good coverage silicon nitride layer 41 forms a first silicon nitride pad layer 41a on the side wall of the compound silicon silicide gate of the complementary metal-oxide-semiconductor element and the stacked gate of the stacked gate flash memory element, such as Figure 4 shows. For a NOR-type architecture, the common buried-source diffusion can use a non-critiCal alignment formed tenth mask photoresist 25j, and the field oxide layer 28 and the first The thermal silicon dioxide layer 22 is automatically etched in alignment, and then phosphorous is implanted to form a highly doped source and common buried layer source diffusion region 40a, as shown in FIG. 5A, and then the formed tenth mask photoresist 25j is removed. The exposed surface of the single crystal silicon is then oxidized in a dry oxygen environment at about 850 ° C to grow a fourth thermal silicon dioxide layer 44 between about 50 and 100 angstroms. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed and used the formed eleventh mask photoresist 25k (not shown) to automatically align the boron impurity across the third thermal silicon dioxide layer 31 and implant it into the η well 21b. The monocrystalline silicon surface is formed to form a heavily doped source and drain diffusion region 42 for all P-channel metal-oxide half-elements, and then the formed eleventh mask photoresist 25k is removed. Similarly, using the formed twelfth mask photoresist 251 (not shown), the arsenic impurities are automatically aligned across the third thermal silicon dioxide layer 31 and implanted on the surface of the single crystal sand in the P well 21c. In order to form highly doped source and drain diffusion regions 43 of all n-channel metal-oxide half-elements, an impurity cloth is implanted into the P well 21a across the first thermal silicon dioxide layer 22 and the fourth thermal silicon dioxide layer 44. Monocrystalline silicon surface to form a high-concentration diffusion region of the highly doped source 43b, 43a, and common buried layer source 43c of the stacked gate flash memory device, and then the formed twelfth mask 17 is removed China National Standard (CNS) A4 specification (210X 297 mm) 513796 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Photoresistor 251. Then, in a nitrogen environment of 850 ° C to 950 ° C, thermal annealing is performed by a furnace tube or a rapid annealing system to activate the doping of the implant and eliminate defects caused by the implant. The completed structure is shown in Figure 5B. The third thermal silicon dioxide layer 31, the first thermal silicon dioxide layer 22, and the first thermal silicon dioxide layer 22 are overlaid on the highly doped drain, source, and common buried layer source diffusion regions using diluted hydrofluoric acid or buffered hydrofluoric acid or anisotropic etching. Fourth heat silicon dioxide layer 44. Then, a titanium metal layer having a thickness of about 500 to 1,000 angstroms is sputtered on the surface of all structures. A rapid thermal annealing was performed under a nitrogen atmosphere at 600 ° C to form a titanium silicide (TiSi2) layer 45 on the surface of the exposed single crystal silicon, and a titanium nitride (TiN) layer 46 was formed on all surfaces. The solution of ammonia: hydrogen peroxide: pure water (1: 1: 5) is used to remove the titanium nitride layer 46, and then the completed structure is annealed in an argon atmosphere to reduce the resistance of the titanium silicide. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, using plasma enhanced chemical vapor deposition (PECVD), a thick dielectric layer 47 such as boron-phosphorus doped glass (BPSG) is deposited, and then the entire structure surface is flattened by CMP Into. A thick dielectric layer 47 is formed by using the formed thirteenth mask photoresist 25m (not shown) to form contact holes, and then the formed thirteenth mask photoresist 25m is removed. Then, the thick dielectric layer 47 was caused to flow at a temperature of 850 ° C to round the contact hole. By sputtering or CVD, a thin titanium nitride layer 48 of about 100 to 200 angstroms is deposited as a barrier metal layer between the upper metal and the lower metal. Tungsten fluoride and hydrogen are reduced by sputtering or LPCVD at a temperature between 250t and 50 ° C. A layer of tungsten is deposited as metal plugs. 49 The CMP method is used again to remove excess tungsten and nitrogen. Titanium oxide is removed and the structure is flattened. Ml metal with a thickness of about 5,000 to 10,000 angstroms is deposited by sputtering method. 18 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 513796 A7 B7 5 2. Description of the invention () (Please read the precautions on the back before filling this page) layer, and then use the formed fourteenth mask photoresist 25n (not shown) to etch the Ml metal layer to form the Ml metal connection between the components Line 50, and then remove the formed fourteenth mask photoresist 25η, as shown in Figure 5C. It should be noted that the formation process of the above-mentioned common buried layer source includes the tenth mask photoresist and field oxide layer. Etching, ion implantation, and re-oxidation are eliminated, and the NAND-type architecture can serially connect the source / drain diffusion regions of the stacked gate flash memory elements into bytes, as shown in Figures 6A and B. Then connect the two ends to two separate metal-oxide half-elements ( select MOS devices) (not shown). The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed and deposited the first intermediate dielectric layer 51 (not shown), followed by CMP planarization. The five-mask photoresist 25 (not shown) etches the first connection hole (Was), removes the formed fifteenth mask photo-resist 25, the barrier metal layer and the plug gold deposits are stacked, the CMP is planarized, and the M2 metal Sputtering, using the formed sixteenth mask photoresist 25p (not shown) uranium to etch the M2 metal layer to form the M2 metal connection 52, and then removing the formed sixteenth mask photoresist 25p. Multilayer metal connection The line can be completed by repeating the above process steps. Finally, a passivation layer 53 (not shown) is deposited, and a 17th mask photoresist 25q (not shown) is used to etch the bonding wire holes to The bonding pads are exposed, and then the formed seventeenth mask photoresist 25q is removed. It should be noted here that the titanium metal layer can be replaced with other conventional refractory metals, such as tantalum and molybdenum. , Cobalt, etc .; the intermetal dielectric layer can be CVD Silicon layer or other low dielectric constant dielectric layer; the connecting metal can be aluminum or aluminum alloy or copper. It is very clear that the miniaturizable stacked gate flash memory device of the present invention can be 19 paper sizes Applicable to China National Standard (CNS) A4 specification (210X297 mm) 513796 A7 ___B7 _ V. Description of the invention () In order to easily have a gate length much smaller than the minimum line width of the technology used, and coupled with the present invention can greatly adjust the coupling Compared with the shallow groove isolation structure of the floating gate, it can manufacture high-density, high-speed, low-voltage and low-power flash memory element arrays and systems required for large-scale storage applications. The connotation disclosed in Figures 3 to 6 is the use of a P-type substrate containing an isolated n-well and an isolated P-well. For those skilled in the art, it should be understood that different types of substrates can also be used. Furthermore, using the advantages of the present invention, a miniaturizable stack-type flash memory device can also be manufactured in a well, to form a P-channel flash memory device. In addition, the shrinkable stacked gate flash memory elements have been fully applied to the manufacture of arrays of NOR and NAND architectures. Other different architectures such as DINOR and AND can also be easily modified and connected through a few processes. Technology to complete. Although the present invention is particularly illustrated and described with reference to the attached connotation, those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 This paper size applies to China National Standard (CNS) A4 (210X297)

Claims (1)

513796 ABCD VI. Scope of patent application Patent scope: (Please read the precautions on the back before filling out this page) 1 · A method of manufacturing a miniaturizable stacked gate flash memory element and its array, the method includes manufacturing The shallow groove isolation structure of the channel width of the non-volatile semiconductor memory element array and the self-aligned floating gate that can greatly adjust the coupling ratio, the method at least includes: preparing a semiconductor substrate; forming a multilayer structure, including: A first thermal silicon dioxide layer, a first polycrystalline silicon layer, and a first mask silicon nitride layer are sequentially formed; the non-volatile semiconductor memory element array is defined by etching the multilayer structure with the formed first mask photoresist. The width of the channel and selectively removing the first mask silicon nitride layer, the first polycrystalline silicon layer, and the first thermal silicon dioxide layer, and then removing the formed first mask photoresist; A first good covering sand dioxide layer is formed on the formed multilayer structure, and then the first good covering silicon dioxide layer is anisotropically etched. After the polycrystalline silicon layer and the first thermal silicon dioxide layer are etched, a sidewall is formed to form a first silicon dioxide underlayer; the semiconductor substrate is automatically etched to form a shallow groove; and the surface of the groove where the semiconductor substrate is etched is oxidized. To grow the second thermal silicon dioxide layer; the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the implanted boron impurity into the surface of the semiconductor substrate with the shallow groove to form a forbidden area for the channel; a thick layer of good coverage dioxide was deposited The silicon layer is laminated with this oxygenated layer, filling the etched shallow grooves and exceeding the flatness of the first mask silicon nitride layer. The paper size is in accordance with Chinese National Standard (CNS) A4 (210X 297). (Public change) 513796 ABCD Sixth Intellectual Property Bureau of the Ministry of Economic Affairs employee consumer cooperative printed the scope of patent application; chemical-mechanical smoothing (CMP) method was used to flatten the structure to remove excess silicon nitride layer beyond the first mask. Filled silicon dioxide layer; automatically aligning the flattened silicon dioxide layer and the first silicon dioxide pad layer to a depth of d, where d is equal to the thickness of the first mask silicon nitride layer t The thickness of the first polycrystalline silicon layer; depositing the first good covering polycrystalline silicon layer, and then anisotropically etching the first good covering polycrystalline silicon layer, in the first mask silicon nitride and the first An exposed side wall of a polycrystalline silicon forms first polycrystalline silicon spacers; the first mask silicon nitride layer is removed anisotropically using a hot phosphoric acid wet chemical solution or an active ion etching method; A dielectric layer over the first polycrystalline silicon layer, the first polycrystalline silicon underlayer, and the uranium-etched planarized plutonium-filled silicon dioxide layer; and phosphorus is implanted across the first dielectric layer (Or boron) impurities enter the first polycrystalline silicon layer and the first polycrystalline silicon underlayer. 2. The method as described in item 1 of the scope of the patent application, wherein the semiconductor substrate is a P-type semiconductor with retrograde implanted n-well or isolated n-well and P-well or isolated P-well And the non-volatile semiconductor memory element array is manufactured on the P-well or the isolated P-well. 3. The method according to item 1 of the scope of the patent application, wherein the first thermal silicon dioxide layer is used as a thin penetrating oxide layer with a thickness of about 70 to 110 angstroms. 22 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 513796 ABCD Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, X, Patent scope 4. The method according to item 1 of the scope of patent application, wherein the first polycrystalline silicon layer is the self-aligned floating gate as the non-volatile semiconductor memory element, and is naturally doped with phosphorus (or Boron) The impurity concentration is between about 1018 and 5x 1019 / cm3, and the thickness is between about 300 and 2000 Angstroms. 5. The method according to item 1 of the scope of the patent application, wherein the first mask silicon nitride layer is used as a hard mask to selectively etch the first polycrystalline silicon layer and the first thermal silicon dioxide layer. The thickness t of the first mask silicon nitride layer is also used to adjust the height of the first polycrystalline silicon pad layer. 6. The method according to item 1 of the scope of the patent application, wherein the thickness of the first good coverage silicon dioxide layer is between about 200 and 500 angstroms, and the first silicon dioxide underlayer is used as a buffer oxide. A cushion layer to form a forbidden area of the channel isolated by the shallow groove and avoid oxidation on both sides of the first thermal silicon dioxide layer. 7. The method according to item 1 of the scope of patent application, wherein the shallow groove is between a depth of about 2000 Angstroms and about 4000 Angstroms in the single crystal silicon, and the thin second thermal silicon dioxide layer is grown after the etching. The thickness of the single crystal silicon groove surface is between about 50 and 150 Angstroms. 8. The method as described in item 1 of the scope of patent application, wherein the boron impurity implantation in the forbidden area of the channel isolated by the shallow groove described above can be rotated at a large angle to 23 The paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297mm) ............ 0 ........., but ......... line · (Please read the precautions on the back first (Fill in this page) 513796 A8 B8 C8 D8 The scope of patent application is completed, and the implantation dose is between about 1013 and 1014 / cm2. (Please read the precautions on the back before filling this page) 9. The method described in item 1 of the scope of patent application, wherein the depth d of the etched silicon dioxide layer is equal to the first mask The thickness t of the curtain silicon nitride layer plus the thickness of the first polycrystalline silicon layer is also used to further adjust the coupling ratio of the self-aligned floating gate of the non-volatile semiconductor memory element. 10. The method according to item 1 of the scope of the patent application, wherein the first good coverage polycrystalline silicon layer is a natural doped phosphorus (or boron) impurity with a concentration of about 1018 to 5 X 1019 / cm3. The thickness of the first polycrystalline silicon cushion layer is determined by the thickness of the first polycrystalline silicon layer. 11. The method according to item 1 of the scope of the patent application, wherein the first dielectric layer may be a silicon dioxide-silicon nitride-silicon dioxide (0ΝΟ) composite layer or other dielectric layer, which is equivalent The thickness of silicon dioxide is between about 100 and 200 Angstroms. 1 2. The method according to item 1 of the scope of patent application, wherein phosphorus (or boron) impurities are implanted across the first dielectric layer into the first polycrystalline silicon layer and the first polycrystalline silicon pad. The dose of the layer is between about 1014 and 5 x 105 / cm2. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13. The method described in item 1 of the scope of patent application, which further includes the use of the above-mentioned invention, which has the channel forbidden zone and a large modulation coupling ratio of the automatic alignment The advantages of the shallow groove isolation structure of the floating gate to make any structure 24 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm) 513796 ABCD application for this non-volatile semiconductor memory element and array. 14. The method according to item 1 of the scope of patent application, further comprising using a formed second mask photoresist to remove the first dielectric on other semiconductor devices, such as peripheral complementary metal-oxide half-device regions, which are to be manufactured. Layer and the first polycrystalline silicon layer or the first polycrystalline silicon pad layer, and then removing the formed second mask photoresist. 15. The method according to item 14 of the patent application scope, further comprising using a formed third mask photoresist to implant boron impurities across the first thermal silicon dioxide layer cloth into the single crystal in the P well. Silicon region to adjust the threshold voltage and breakdown voltage of all n-channel metal-oxide half-elements, and then remove the formed third mask photoresist; use the formed fourth mask photoresist to pass boron or phosphorus impurities across the A first thermal silicon dioxide layer cloth is implanted into the single crystal silicon region in the n-well to adjust the threshold voltage and the breakdown voltage of all P-channel metal-oxide half-elements, and then remove the formed fourth mask photoresist. 16. The method according to item 15 of the patent application scope, further comprising oxidizing the first thermal silicon dioxide layer exposed to grow a third thermal silicon dioxide layer. 17. The method according to item 16 of the scope of patent application, wherein the third thermal silicon dioxide layer is a gate dielectric layer of the complementary metal-oxide half-element, and has a thickness of about 200 to 400 angstroms. 18. The method described in item 16 of the scope of patent application, which also includes stacking 25 paper sizes to apply Chinese National Standard (CNS) A4 specifications (210X297 mm) f: (Please read the precautions on the back before filling this page )-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 513796 ABCD VI. Patent application scope of the second polycrystalline silicon layer, and then a silicide layer is deposited to serve as the polycrystalline silicidation of the non-volatile semiconductor memory device 1ycide) control gate and complex silicon silicide gate of the complementary metal-oxide half-element. 19. The method according to item 18 of the scope of the patent application, wherein the second polycrystalline silicon layer is naturally doped with phosphorus (or boron) with an impurity concentration of about 1018 to 5x 10 19 / Cm3, and its thickness Between about 1000 and 2000 Angstroms. 20. The method as described in item 18 of the scope of patent application, wherein the silicide layer may be a tungsten silicide (WSi2) layer or other refractive metal silicides such as titanium silicide (TiSi2), molybdenum silicide (TaSi2), molybdenum silicide ( MoTi2) or cobalt silicide (CoSi2), etc., and its thickness is between about 1,000 and 2,000 Angstroms. 21. The method as described in claim 18 of the scope of patent application, which further includes the following method for simultaneously manufacturing a miniaturizable stack gate flash memory element and its array and peripheral complementary metal-oxide half-elements, the method including at least : Forming a multi-layer mask structure, including sequentially stacking a second mask silicon nitride layer and a first 'mask polycrystalline sand layer; etch the multi-layer mask structure with the formed fifth mask photoresist to The minimum line width (λ) of the technology is used to define the pitch of the stacked gate flash memory elements and the virtual gate length (Lv) of the stacked gate flash memory elements, where the virtual gate length is equal to two stacks The gate length of the stack gate type flash memory element (2ΔΙ〇 plus a source or drain diffusion window (λ)), and then selectively engraving the first mask polycrystalline silicon layer and removing the formed fifth mask photoresist; 26 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) .............. I (Please read the precautions on the back before filling this page)-Order · Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 513796 ABCD Patent Application ? (Please read the precautions on the back before filling in this page) Deposit a second good coverage silicon dioxide layer with thickness equal to AL, and then anisotropically etch the second good coverage silicon dioxide layer. The side wall of the first mask polycrystalline silicon layer forms a second silicon dioxide underlayer, wherein the width of the second silicon dioxide underlayer is equal to AL, and AL is smaller than the minimum line width λ of the technology used; Isotropic etching removes the etched first mask polycrystalline silicon layer, leaving the second silicon dioxide cushion layer as the hard mask of the stack length of the stacked gate flash memory element; The six-mask photoresist defines the gate lengths of all the complementary metal-oxide-semiconductor half-elements, and then anisotropically etches the second mask silicon nitride layer and removes the first silicon dioxide cushion layer, and then removes the formed sixth Mask photoresist; automatically aligning the silicide layer, the second polycrystalline silicon layer, the first dielectric layer, the first polycrystalline silicon layer, and the first polycrystalline silicon pad layer in an anisotropic manner To form the stack gate flash memory element and the peripheral complementary metal-oxide half-element Gate area; oxidize the side wall of the etched first polycrystalline silicon layer and the etched second polycrystalline silicon layer to grow a thin first polycrystalline sand oxide layer; printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The formed seventh mask photoresist is implanted with boron impurities to form the lightly doped source and drain diffusion region of all the P-channel metal-oxide half-elements in all the complementary metal-oxide half-elements, and then removing the formed seventh The mask photoresist; the formed eighth mask photoresist is used to implant phosphorus impurities to form the complementary metal-oxide half-half. The lightly doped source and drain diffusion region of all the n-channel metal-oxide half-elements in the element, and then Removal of the formed eighth mask photoresist; by means of the formed ninth mask photoresist, arsenic impurities are implanted to form the stacked gate flash memory device. Moderately doped (mid- 27 This paper is applicable to China National Standard (CNS) A4 specification (210X297 mm) 6 9 7 3 ABCD VI. Patent application scope doped) source and shallow diffusion area, and then remove the formed ninth mask photoresist; and deposit the first good coverage nitrogen Silicon layer, and then anisotropically etch the first good coverage nitrogen Silicon layer, a first silicon nitride pad layer is formed in the side wall of the stack gate type all flash memory element and the complementary metal-oxide-semiconductor element of. 22. The method as described in claim 21, wherein the thickness of the second silicon nitride layer is about 500 to 1500 angstroms. 23. The method of claim 21, wherein the thickness of the first mask polycrystalline silicon layer is between about 500 and 2500 angstroms. 24. The method according to item 21 of the scope of patent application, wherein the implantation dose of the lightly doped source of the P-channel metal-oxygen half element and the boron impurity in the diffusion diffusion region is about 1013 to 1014 / cm2. 25. The method according to item 21 of the scope of patent application, wherein the implantation dose of the lightly doped source of the n-channel metal-oxide half-element and the phosphorus impurity in the diffusion diffusion region is about 1013 to 1014 / cm2. 26. The method according to item 21 of the scope of patent application, wherein the implantation dose of the moderately doped drain and source diffusion region of the stacked gate flash memory device described above is about 1014 to 1 〇i5 / cm2. 27. The method as described in item 21 of the scope of patent application, wherein the first 28 paper sizes mentioned above are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ... .I (Please read the notes on the back before filling this page)-Ordered · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed on 513796 AB CD Application for a patent covering the thickness of the silicon nitride layer is about 300 to 1,000 Angstroms between. (Please read the precautions on the back before filling this page) 28. The method described in item 21 of the scope of patent application, including the following methods to manufacture NOR-type stacks with a common buried-source A stack gate flash memory element array and a peripheral complementary metal-oxide half-element, the method at least includes: forming a common buried layer source by a non-critical alignment lithographically formed tenth mask photoresist Window, and then automatically align and remove the shallow groove-isolated field oxide layer and the first thermally-diluted sand layer on the local doped source diffusion region of the stacked gate flash memory element, and then implant Phosphorus or arsenic impurities to form a highly doped source diffusion region and a highly doped diffusion region of a common buried layer source, and then removing the formed tenth mask photoresist; oxidizing the single crystal silicon surface of the etched common buried layer source, Grow a fourth layer of thermal silicon dioxide, with a thickness of about 50 to 150 angstroms; the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed and formed the eleventh mask photoresist, and implanted boron impurities to form all the p channels Metal Oxygen Half Element The highly doped source and drain diffusion regions are then removed from the formed eleventh mask photoresist; by using the formed twelfth mask photoresist, arsenic impurities are implanted to form the high doping of all the n-channel metal-oxide half-elements The impurity and drain diffusion regions and the highly doped source and drain and common buried layer source diffusion regions of the stacked gate flash memory element array, and then removing the formed twelfth mask photoresist, wherein the highly doped The quality of the implantation dose is about 1015 to 5x105 / cm2; thermal annealing is performed to activate the implantation impurities and eliminate the defects caused by the implantation; automatically align and remove the stack gate flash The high content of the memory element array is 29. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 513796 A8 B8 C8 D8. 6. The scope of patent application for miscellaneous leakage and source / common buried layer source diffusion area. A first and a fourth thermal silicon dioxide layer and a third thermal silicon dioxide layer on the highly doped source and the drain diffusion region of the peripheral complementary metal-oxide-semiconductor element; a titanium metal layer is deposited on all structural surfaces, Followed by rapid annealing in a nitrogen environment, in the highly doped diffusion region The surface of the single crystal silicon is exposed to form a titanium silicide layer, and a titanium nitride layer is formed on all the surfaces. Aqueous ammonia: hydrogen peroxide: pure water (1: 1: 5) solution is used to selectively remove titanium nitride, and then in the argon Anneal in an environment to reduce the resistance of the titanium silicide layer; deposit a thick dielectric layer, and then planarize the surface of the structure by CMP, where the thick dielectric layer may be a CVD silicon dioxide layer or a boron-phosphorus doped glass (BPSG) layer; by forming the thirteenth mask photoresist, removing the planarized thick dielectric layer to form contact holes, and then removing the formed thirteenth mask photoresist, and then heating The thick dielectric layer is caused to flow, and the opening is rounded; a titanium nitride layer is deposited as a barrier metal, and then tungsten is deposited as metal plugs, and then the planarized dielectric is formed by a CMP method The titanium nitride and the tungsten on the layer are removed and flattened; the Ml metal layer is deposited, and the Ml metal layer is engraved with a formed fourteen mask photoresist age to form an Ml metal wiring layer, and then the Formed Fourteenth Curtain Photoresist 'Where The drains of the stacked gate flash memory elements are connected using a first layer M1 metal connection to form a bit line. The source of the stacked gate flash memory elements is titanium silicide. The common buried layer source diffusion area is connected to the ground; / 30 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) f (Please read the precautions on the back before filling this page)-Order · Ministry of Economics Wisdom Printed by the Consumer Cooperative of the Property Bureau 513796 A8 B8 C8 D8 6. Scope of patent application (谙 Read the precautions on the back before filling this page) Stack the first intermetal dielectric layer on the first M1 metal connection. Then the CMP is planarized, the vias of the first intermetal dielectric layer are engraved by the formed fifteenth mask photoresist uranium, the formed fifteenth mask photoresist, the barrier metal and the peg metal are removed , CMP planarization, stacking of the M2 metal layer, etching the M2 metal layer with the formed sixteenth mask photoresist to form a second layer of M2 metal wiring, and then removing the formed sixteenth mask photoresist; repeating with The same process of connecting the second layer of M2 to form the first layer n layers of Mn metal wires, where N = 3, 4, 5, 6, ···, as required; and depositing a thick passivation layer, and then using the formed seventeenth mask The photoresist etches the bonding wire holes to expose the bonding pads, and then removes the formed seventeenth mask photoresist. 29. The method as described in item 21 of the scope of patent application, which further includes the following method for manufacturing a NAND-type stacked gate flash memory element array and peripheral complementary metal-oxide-semiconductor elements. The method includes at least: Ministry of Economic Affairs wisdom The Property Cooperative Consumer Cooperative printed a formed eighteen mask photoresist, implanted boron impurities to form the highly doped source and leakage diffusion regions of all the p-channel metal-oxide half-metals, and then removed the formed tenth Eight mask photoresistor. By forming the nineteenth mask photoresistor, arsenic impurities are implanted to form all doped sources and leak diffusion of the n-channel metal-oxide half-element and the stacked gate flash memory element. Area, and then removing the formed nineteenth mask photoresist, wherein the implantation dose of the erbium dopant is between about 1015 and 5x10i5 / cm3; performing thermal annealing to activate the implanted doping Quality and eliminate the defects caused by the planting; 31 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297) Chu 513796 8 8 8 8 ABCD patent application scope (please read the precautions on the back before filling this page) ) Automatically remove the peripheral complement Third doped silicon dioxide layer on the highly doped source and drain diffusion region of the metal-oxide-semiconductor half-element and the first doped source and drain diffusion region on the stacked gate flash memory element A thermal silicon dioxide layer; a titanium metal layer is deposited on the surface of all structures, followed by rapid annealing under a nitrogen atmosphere, and a titanium silicide layer is formed on the surface of the single crystal silicon exposed in the highly doped diffusion region, and on all structures A titanium nitride layer is formed on the surface; the ammonia nitride: hydrogen peroxide: pure water (1: 1: 5) solution is used to selectively etch the titanium nitride layer, and then rapid annealing under an argon atmosphere to reduce the resistance of the titanium silicide; A thick dielectric layer is stacked and all structural surfaces are planarized by a CMP method, wherein the thick dielectric layer may be a CVD silicon dioxide layer or a boron-phosphorus doped glass; the formed twentieth mask photoresist uranium Carve the planarized thick dielectric layer to form a contact hole, then remove the formed twentieth mask photoresist, and then heat to make the contact hole flow and round; stack a titanium nitride layer as a barrier metal, deposit Tungsten metal as a plug metal, then The CMP method was used to planarize the entire structure, and the titanium nitride layer and the tungsten layer on the plane of the planarized thick dielectric layer were removed; the M1 metal layer was printed and deposited by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then the formed The twenty-first mask photoresist is formed to form an M1 metal connection, and then the formed twenty-first mask photoresist is removed, in which a series of stacked gate flash memory elements are highly doped with titanium silicide. The source / drain diffusion area is connected into characters, and the two ends of the concatenated character are connected to separate selective metalloid semi-elements, and one of the selective metalloid semi-elements is 32. This paper size applies to the Chinese National Standard (CNS ) A4 specification (210X297 mm) 513796 A8 B8 C8 D8 The patent application scope of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the patent application of the drain electrode using the first layer of M1 metal connection to the bit line, and the other end of the selection gold The source of the oxygen half element is connected to the ground using the first layer M1; a first intermetal dielectric layer is deposited on the first M1 metal line, then planarized by CMP, and the formed twenty-second is used Mask photoresist etching first The connection hole of the dielectric layer is removed from the formed twenty-second mask photoresist, the barrier metal layer and the plug metal are deposited, planarized by CMP, the M2 metal layer is deposited, and the formed twenty-third The mask photoresist etches the M2 metal layer to form a second M2 metal connection, and then removes the formed twenty-third mask photoresist; repeats the same process steps as the second M2 metal connection to form the Nth Layer of Mn metal connection, where N = 3,4,5,6 ····, as needed; and depositing a thick protective dielectric layer, and then using the formed twenty-fourth mask photoresist to etch the thick protective layer The dielectric layer is used to form a solder window to expose the solder pad, and then the formed twenty-fourth mask photoresist is removed. 30. The method as described in claim 28 or 29, wherein the titanium metal mentioned above can be replaced by other refractive metals, such as giant, cobalt or molybdenum. 31. The method as described in claim 28 or 29, wherein the Mn metal connection may be aluminum, aluminum alloy, copper, or the like. 32. The method described in item 28 or 29 of the scope of patent application, in which the upper 33 paper standards are applicable to China National Standard (CNS) A4 specifications (210X297 public love) f: (Please read the precautions on the back before filling in this Page)-Ordered · 513796 A BCD Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 6. The intermetal dielectric layer described in the scope of the patent application can be a CVD silicon dioxide layer or Low dielectric constant dielectric layer.