A7A7
經濟部智慧財產局員工消費合作社印製 513723 五、發明說明（） I明領域： 本毛明係關於一種控制動態隨機存取記憶體的方 法，特別是關於-種關閉動態隨機存取記憶體之讀取放大 為電源的方法。 發明皆景： 現今，動態隨機存取記憶體。”·。random access memories，DRAMs)已成為高產量的半導體裝置。雖然dram 需要較複雜的週邊電路，以針對資料做讀、寫與再補充 (refresh)的運作，其高積集度（integrati〇n level)與較 低的電源消耗，仍使得DRAM成為許多電腦應用的主流。 此外，採用DRAM可顯著地增加每單位記憶胞（mem〇ry cells)的資料健存量。因此，低成本、高積集度的優點已 使得半導體產業界積極地投入DRAM的研發工作。 DRAM中的讀取放大器被設計用於執行每一個記憶胞 中的讀取動作。DRAM中的記憶胞皆連接於讀取放大器，以 檢測記憶胞中電容的電壓值，並將結果與讀取放大器中的 參考電壓值作比較。依上述的過程，記憶體中的資料即可 被判讀。然而DRAM記憶胞的資料在經過讀寫過程後，會 造成DRAM記憶胞内電容器的電荷處於非平衡狀態（non-equilibrium)，因此需要進行週期性地再補充 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公" .^ -------^-------- (請先閱讀背面之注意事項再填寫本頁) 513723 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） (refresh) 〇 在DRAM的設計架構中，電源消耗（p〇wer c〇nsumpti〇n) 問題係主要的考量之一。隨著技術的演進，DRAM將朝向低 電壓的設計觀念發展’例如新一代的DRAM設計即將「啟 動電源關閉」（power down，act ive)列為設計規格之一， 用以設定DRAM晶片電源消耗的界限。 由於考量電晶體的可靠度，一種設計在晶片上的電壓 調降轉換器（voltage down converter)，即所謂的「調降 器」（regulator)係在維持外部電壓的情況下，提供一較 低的電壓給記憶體胞，以降低熱電子效應（h〇t electr〇n effect)。在記憶體的設計中，通常會有兩個以上的調降 器，用於週邊電路與位元線讀取放大器（bit Hne sense amp 1 ifier)，且不論調降器是否在運作，其對於直流電的 消耗量非常大。 一般而言’位元線讀取放大器並無電源關閉（p〇wer d 〇 w η )的設計’或現今的設計並不能滿足記憶體設計規格 的要求。例如現今的設計之一即設定一固定且過長的時 間，使讀取放大器能夠得到足夠的電量以正常運作。在這 種情況下，電量的消耗還是過大’且會引發電流流量的變 化以及溫度過高的問題。因此，有必要發展較佳的電源關 閉設計，使位元線讀取放大器的操作電壓（Vccsa)能夠即 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ϋ ϊ .^1 »1 ϋ n ί 一-0、I - - II ϋ I K I n *. In. I i I n n I - In n ϋ ϋ 1> 經濟部智慧財產局員工消費合作社印製 513723 A7 B7 五、發明說明（） 時關閉，從而大量地降低電量的消耗，以符合更嚴格的 DRAM設計要求。 發明目的及概述： 本發明所揭露的方法與裝置，係提供一電源控制設 計，使位元線讀取放大器降低電源的消耗，其特徵在於應 用控制電路模組所產生的控制訊號，以產生用於控制位元 線讀取放大器電源的訊號。 本發明所揭露的方法與裝置，利用兩個DRAM的内部 訊號··列址選通脈衝（row address strobe, RAS)的控制 訊號 ras — x 與位元線讀取放大器的電源控制訊號 s 1 pf 2pwr一X，以產生關閉位元線讀取放大器電源的控制訊 號。此兩内部訊號係本發明所揭露之邏輯控制電路的輸入 訊號。 因此，本發明的目的之一係提供一種將動態隨機存取 記憶體之位元線讀取放大器（s e n s e a m p 1 i f i e r)電源關閉 的方法 上述之目的係藉由設計邏輯控制閘與時間延遲電 路，並配合外部控制模組所產生的控制訊號來達成。 4 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ^_wl — n n ϋ ϋ H 一«J· ϋ ϋ n n n ϋ ϋ J. lr I n ϋ n n I I I -.- ϋ d n - n n I* ϋ n ϋ 1· ϋ « A7Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513723 V. Description of Invention (I) Field: This Maoming is about a method of controlling dynamic random access memory, especially about a method of turning off dynamic random access memory Read how to zoom in to power. All inventions: Today, dynamic random access memory. ". Random access memories (DRAMs) have become high-volume semiconductor devices. Although the dram requires more complicated peripheral circuits to read, write, and refresh data (refresh), it has a high degree of integration. n level) and low power consumption still make DRAM the mainstream of many computer applications. In addition, the use of DRAM can significantly increase the data storage capacity per unit of memory cells (memry cells). Therefore, low cost and high accumulation The advantages of concentration have led the semiconductor industry to actively invest in the research and development of DRAM. The read amplifier in DRAM is designed to perform the read action in each memory cell. The memory cells in DRAM are connected to the read amplifier. To detect the voltage value of the capacitor in the memory cell and compare the result with the reference voltage value in the read amplifier. According to the above process, the data in the memory can be read. However, the data in the DRAM memory cell is read After the process, the charge of the DRAM memory cell capacitor will be in a non-equilibrium state, so it is necessary to periodically replenish 2 paper rulers. Degree applies to China National Standard (CNS) A4 specifications (210 X 297 male ". ^ ------- ^ -------- (Please read the precautions on the back before filling this page) 513723 Economy Printed by the Intellectual Property Bureau employee consumer cooperative A7 B7 V. Description of the invention () (refresh) 〇 In the design architecture of DRAM, the power consumption (pοwer c〇nsumpti〇n) problem is one of the main considerations. With With the evolution of technology, DRAM will develop towards a low-voltage design concept. For example, a new generation of DRAM design will soon include "power down (act ive)" as one of the design specifications to set the limit of DRAM chip power consumption. Considering the reliability of the transistor, a voltage down converter designed on the chip, the so-called "regulator", provides a lower voltage while maintaining an external voltage. Voltage is applied to the memory cell to reduce the hot electron effect. In the design of memory, there are usually more than two regulators for peripheral circuits and bit line read amplifiers ( bit Hne sense amp 1 ifier ), And whether the regulator is operating or not, its consumption of DC power is very large. Generally speaking, 'bit line read amplifiers have no power off (p〇wer d 0w η) design' or current design It does not meet the requirements of memory design specifications. For example, one of the current designs is to set a fixed and long time, so that the read amplifier can get enough power to operate normally. In this case, the power consumption is still too large 'and it will cause changes in the current flow rate and excessive temperature problems. Therefore, it is necessary to develop a better power-off design so that the operating voltage (Vccsa) of the bit line read amplifier can be 3 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please first Read the notes on the reverse side and fill out this page) ϋ ϊ. ^ 1 »1 ϋ n ί 一 -0, I--II ϋ IKI n *. In. I i I nn I-In n ϋ ϋ 1 > Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 513723 A7 B7 V. When the invention is closed (), the power consumption is greatly reduced to meet more stringent DRAM design requirements. Purpose and summary of the invention: The method and device disclosed in the present invention provide a power control design to reduce the power consumption of a bit line read amplifier. It is characterized by applying a control signal generated by a control circuit module to generate a power supply. A signal for controlling the bit line read amplifier power. The method and device disclosed in the present invention utilize internal signals of two DRAMs. A control signal ras — x of a row address strobe (RAS) and a power control signal s 1 pf of a bit line read amplifier 2pwr-X to generate a control signal to turn off the power of the bit line read amplifier. These two internal signals are input signals of the logic control circuit disclosed in the present invention. Therefore, one of the objects of the present invention is to provide a method for turning off the power of a bit line read amplifier of a sense random access memory (senseamp 1 ifier). The above object is to design a logic control gate and a time delay circuit, and Cooperate with the control signal generated by the external control module. 4 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) ^ _wl — nn ϋ 一 H «J · ϋ ϋ nnn ϋ ϋ J. lr I n ϋ nn III -.- ϋ dn-nn I * ϋ n ϋ 1 · ϋ «A7
五、發明說明（） 簡單説明： (請先閱讀背面之注意事項再填寫本頁) 本發明的詳細說明將藉由一最佳實施例，並配合所附 圖示加以說明。 第1圖係位元線讀取放大器之電源關閉設計的時序圖； 第2圖係本發明所揭露之關閉電源設計之控制邏輯圖示。 凰^號對照說明： 1 〇列址選通脈衝的控制訊號ras_x 12位元線讀取放大器的電源控制訊號sipf 2pwr_x 14讀取放大器的内部操作電壓ena__vccsa 20邏輯控制電路 22或閘（OR gate) 24 及閘（AND gate) 26 反或閘（NOR gate) 2 8時間延遲電路 3 0時間延遲電路 經濟部智慧財產局員工消費合作社印製V. Description of the invention () Brief description: (Please read the notes on the back before filling out this page) The detailed description of the invention will be explained by a preferred embodiment and the accompanying drawings. Figure 1 is a timing diagram of the power-off design of the bit line read amplifier; Figure 2 is a control logic diagram of the power-off design disclosed in the present invention. Explanation of the reference number ：: 1 〇 Control signal of the address strobe pulse ras_x 12-bit line read amplifier power control signal sipf 2pwr_x 14 Internal operating voltage of the read amplifier ena__vccsa 20 logic control circuit 22 or gate (OR gate) 24 AND gate 26 NOR gate 2 8 time delay circuit 3 0 time delay circuit Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs
32位元線讀取放大器的電源控制訊號slpf 2pwr_x 34列址選通脈衝的控制訊號ras_x 36節點A 38節點B 40讀取放大器的電源關閉訊號dab_vccsa_x 發明詳細說明’· 參閱第2圖，其為本發明所揭露之關閉電源設計的控 5 本紙張尺度適用中國國家標準（CNS)A4 &格（210 X 297公釐） 513723 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 制邏輯圖示，其輸出為一電源關閉控制訊號。邏輯控制電 路 20 包含一或閘（OR gate)22、一及閘（AND gate)24、一 反或閘（NOR gate)26，以及兩個時間延遲（t ime delay )電 路 28 與 30。列址選通脈衝（row address strobe，RAS) 的控制訊號ras_x 34，係用以控制字元線的開啟時間。讀 /寫的動作的進行’必須藉由RAS時脈的傳遞’以選擇一 字元線。當字元線開啟時’位元線讀取放大器（bit line sense amplifier)的電源控制訊號 32(slpf2pwr_x)將提 供電源給反相器（inverter)(未表示出），使其閂鎖（latch) 資料。 參閱第1圖，其為位元線讀取放大器之電源關閉設計 的時序圖。首先，考慮每一輸入端的初始邏輯狀態（loglc level)。ras 一 X 10 (RAS 的控制訊號）、slpf2pwr_x 12 (位 元線讀取放大器的電源控制訊號）、ena-vccsa 14 (讀取 放大器的内部操作電壓）以及節點B 3 8 (如第1圖所示）的 初始邏輯狀態分別為邏輯0、邏輯1、邏輯〇與邏輯0° 參閱第2圖，當ras_x訊號34上升時（由邏輯〇至 邏輯1)，dab_vccsa_x訊號（讀取放大器的電源關閉訊 號）40仍維持在初始邏輯狀態（即邏輯1 )。由於ras-x 34 經過時間延遲電路3 0的作用，節點B的狀態為邏輯1 ° 因此，經過時間ti的延遲後，dab一vccsa一X訊號40的 邏輯狀態轉變為邏輯0，且反或閘26的輸出與 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------.—r^w---------------^ ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 513723 A7 B7 五、發明說明（） dab_vccsa__x訊號40的狀態分別為邏輯0與邏輯〇。由 ras_x訊號10至ena —vccsa訊號14的延遲ti表示於第1 圖中。其中，時間延遲電路28與30可藉由設計一串列 的反相器來達成。 參閱第1圖，當ras — x訊’號10的前緣（leading edge) 產生時，slpf2pwr_x訊號12開始進行t2時間延遲。經 過t2時間後，slpf 2pwr_x訊號12的狀態下降至邏輯0, 且 ras_x訊號 10、節點 A 36(如第 2圖所示）以及 dab_vccsa_x訊號40(如第2圖所示）的狀態分別為邏輯 1、邏輯0與邏輯1。其中，位元線放大器的電源開啟時 間為13，而節點A 3 6的邏輯狀態直到延遲14時間後才 改變。因此，時間延遲t 4可視為由内部訊號所產生的自 發時間延遲（self time delay)。至此，如第2圖所示， 節點A 3 6的狀態為邏輯0 ; dab —vccsa-X訊號4 0的狀態 將經過或閘2 2、及閘2 4與反或閘2 6的作用而上升為邏 輯1。因此，只要電源關閉控制訊號dab一vccsa —X進行 運作，位元線讀取放大器將可於足夠的時間内閂鎖住記 憶胞中的資料，而同時達到即時關閉讀取放大器電源的 目的。 因此，位元線讀取放大器的關閉電源控制訊號 dab一vccsa一X 40可經由上述之邏輯控制電路20(如第2圖 所示）產生。本發明所揭示的控制邏輯電路提供一電源關 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " '一 ' ' LJAW-------訂-------- (請先閱讀背面之注意事項再填寫本頁) 513723 A7 B7 八命的龟你消耗。解決讀 五、發明說明（ 閉的控制訊號 放大器電源消耗過大的問題’其關鍵係在於其停止作用 後’儘速關閉讀取放大器的供應電流，而與字元線的開啟 時間長度無關。 以大多數記憶體設計的規格而言，字元線的開啟時 長度約長達1 2 0, 0 0 0奈秒。藉由實施本發明所揭示之關 電源的設計，讀取放大器的直流電源、、&> & ’與先前技術 由ras__x訊號控制的設計相較之下，可、 減少至約16. 9% 以上所述僅為本發明之較佳實施 Μ而已，並非用L、j 限定本發明之申請專利範圍；凡其它I ^ &脫離本發明所相 示之精神下所完成之等效改變或修飴 t 卜 ^應包含在下对 之申請專利範圍内。 --------------------^--------- ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）32-bit line read amplifier power control signal slpf 2pwr_x 34 column address strobe control signal ras_x 36 node A 38 node B 40 read amplifier power off signal dab_vccsa_x Detailed description of the invention '· Refer to Figure 2, which is Control of the power-off design disclosed in the present invention 5 The paper size is applicable to the Chinese National Standard (CNS) A4 & (210 X 297 mm) 513723 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( ) Control logic diagram, whose output is a power-off control signal. The logic control circuit 20 includes an OR gate 22, an AND gate 24, a NOR gate 26, and two time delay circuits 28 and 30. The control signal ras_x 34 of the row address strobe (RAS) is used to control the turn-on time of the word line. The read / write operation is performed 'must pass through the RAS clock' to select a word line. When the word line is turned on, the power control signal 32 (slpf2pwr_x) of the bit line sense amplifier will provide power to the inverter (not shown) to latch it. data. See Figure 1 for a timing diagram of the power-off design of the bit line read amplifier. First, consider the initial loglc level of each input. ras one X 10 (control signal of RAS), slf2pwr_x 12 (power control signal of bit line read amplifier), ena-vccsa 14 (internal operating voltage of read amplifier) and node B 3 8 (as shown in Figure 1) (Shown) The initial logic states are logic 0, logic 1, logic 0, and logic 0 °. See Figure 2. When the ras_x signal 34 rises (from logic 0 to logic 1), the dab_vccsa_x signal (the power-off signal of the read amplifier) ) 40 is still maintained in the initial logic state (ie logic 1). Because ras-x 34 passes the function of time delay circuit 30, the state of node B is logic 1 °. Therefore, after the delay of time ti, the logic state of dab-vccsa-X signal 40 changes to logic 0, and the OR gate is reversed. Output of 26 and 6 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------.-- r ^ w ----------- ---- ^ ^ (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513723 A7 B7 V. Description of the invention () The status of dab_vccsa__x signal 40 is logic 0 and logic 0 respectively. . The delay ti from ras_x signal 10 to ena —vccsa signal 14 is shown in Figure 1. Among them, the time delay circuits 28 and 30 can be achieved by designing a series of inverters. Referring to Fig. 1, when the leading edge of ras-x signal '10 is generated, slpf2pwr_x signal 12 starts to perform t2 time delay. After the time t2, the state of the slpf 2pwr_x signal 12 drops to logic 0, and the states of the ras_x signal 10, node A 36 (as shown in Figure 2), and the dab_vccsa_x signal 40 (as shown in Figure 2) are logic 1 respectively. Logic 0 and logic 1. Among them, the power-on time of the bit line amplifier is 13 and the logic state of node A 3 6 does not change until after a delay of 14 time. Therefore, the time delay t 4 can be regarded as a self time delay caused by an internal signal. At this point, as shown in Figure 2, the state of node A 3 6 is logic 0; the state of dab —vccsa-X signal 40 will rise through the action of OR gate 2 2 and gate 2 4 and anti OR gate 26. Is logic 1. Therefore, as long as the power-off control signal dab-vccsa-X is operated, the bit line read amplifier can latch up the data in the memory cell in sufficient time, and at the same time achieve the purpose of immediately turning off the power of the read amplifier. Therefore, the power-off control signal dab-vccsa-X 40 of the bit line read amplifier can be generated through the above-mentioned logic control circuit 20 (as shown in FIG. 2). The control logic circuit disclosed by the present invention provides a power supply. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) " '一' 'LJAW ------- Order --- ----- (Please read the notes on the back before filling this page) 513723 A7 B7 Eight-Life Turtle you consume. Solve the fifth, invention description (closed control signal amplifier power consumption problem is too large, the key is that after it stops functioning) as soon as possible to turn off the read amplifier supply current, regardless of the length of the word line on time. In terms of the specifications of most memory designs, the length of the word line is about 120,000 nanoseconds when turned on. By implementing the power-off design disclosed in the present invention, the DC power of the read amplifier, & > & 'Compared with the prior art design controlled by the ras_x signal, it can be reduced to about 16.9%. The above is only a preferred implementation of the present invention. It is not limited by L and j. The scope of patent application of the present invention; all other equivalent changes or repairs that deviate from the spirit shown in the present invention shall be included in the scope of patent application of the following pair. ------ -------------- ^ --------- ^ (Please read the notes on the back before filling out this page) 8 copies printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)