513574 A7 五、發明說明（） 本發明係關於一種電路板線路漏接之檢蜊方去 ^ 種可準確檢測出電路板上線路偏移及因而生 尤扣 象之電路板檢測方法。 ^成漏接現 按，板邊試樣（TeSt C〇upon)係業者用來測試與 $路板成品品質的方法’主要係用來瞭解電路板的細部品 貝，尤其是多層板的通孔結構，由於不能只靠外觀檢查: 電性測試，故需對其結構作進一 — /ir · 少的被切片 :〇SeCti〇ning)顯微檢查。如第十圖所示，揭示有— =路板（7〇)成品的示意圖，其中間部分為複數的線路 早凡（71)，由圖中可以看出，該電路板（7〇) ^即線路單元（71)的外圍處）預留有適#寬度的板 邊（7〇1)，又每-線路單元（71)的周圍亦預留有 板邊（711);其中：電路板（7〇)周圍的板邊（了 〇 1 )係供製造商在製程中作夹持等各項動作，至於線路 單元（7 1 )與電路板（7 〇 )間係採可斷開形式 (Break-away panel)，使用時可經斷開成獨立的線路板， 以進行封裝或其他後續製程，而線路單元（7丄）周圍預 留的板邊（7 1 1 )則供前述製程使用。 又，前揭所述的「板邊試樣」—般係在電路板（7 〇 )周圍的板邊（7Q1)上進行，主要原因在於：電路板 (70)周圍預留的板邊（7〇u面積較大，而線路單 兀（71)周圍的板邊（711)因已單元化，故面積十 分有限，而既有板邊試樣必須佔用相當的空間，自益法利 用線路單元（71)的板邊（711)作前述測試。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁} 壯衣.. #_ 經濟部智慧財產局員工消費合作社印製 A7 B7 五 、發明說明（ ，有μ…述可知’既有「板邊試樣」存在實施位置的限制 間：此-問題實際上與目前的實施方式必須佔用較大空 另除此問題以外，另亦存在精確度問題： =第十一圖所示，既有「板邊試樣」係在電路板 成，式、=二；=1(7〇1)的範圍内分別形 路俜隨缓拉； 線路區（72)上的線 路^ :早元（71)同時製造形成，故具有相同的線 路區貝（7 ?進订板邊測試時，係利用微切片方法將測試線 進疒研麻^的線路沿其導通孔處鋸開，隨後對鋸開處 上；端：否ί至導通孔的中心處’再以顯微鏡觀測導通孔 下^否與線路確實連接，以壯其是否有漏接現象。 :由上述霄施方式說明可看出，先鋸開再研磨之方式 /刀繁複㈣，且其精確度亦有待商榷，仙在 :?=r夺，只能由相同於鑛開方向的-轴線上判斷線 疋否偏& ’ “、㈣可能偏移的方 方向，故其判讀結果自難確保精確。1止[亥鑛開 置谁：ri「板邊試樣」多半以電路板（7〇)的對角位 進订板邊試樣，但實際上電路板（7〇) 部 智 慧 財 消 費 合 社 印 偏移量與對角處的偏移量並不盡然相同，报可能一= ==許=内’對角處的偏移量則超出容許範圍 ' 口…法確涊那一個線路單元（γ丄）的線 路偏移量仍在容許範圍内，而必須 、’、’ 作廢，造成其成本居高不下。將整個電路板（7〇) 由上述可知，既有「板邊試樣」因作業空間大，在實 I_ 4 (CNS)A4 (mT^7 )_ ft濟部智慧財產局員工消費合作社印製 、發明說明（） =置降㈣測的準確度，並提高了製造 有待進-步檢討，並謀求可行的解決方案。 因此，本發明主要目的 化製程、卩备柄士I 種積確度鬲且可簡 、牛低成本之電路板檢測方法。 為達成前述目的採取的主 電路板上的適當位置純#手&係切述方法在 包括有· /成有至V 一檢測區，該檢測區至少 一共通線路，係位於電路板底面； 多數焊墊，係位於電路板表面； ϋ木針，係貫穿電路板且分別位於焊墊底 其構成電性連接；其中： 〃 則述共通線路上形成有複數的窗口，各窗口分別呈有 遞增的内#，且對正於前述的各探針，常態下，該電路板 底面的共通線路與探針間係呈開路狀； 俟進行測試時，僅須測試各焊墊間是否呈短路狀，藉 此可偵測出線路區的線路是否出現偏移，進而可判斷線路 與焊墊間是否有漏接現象。 珂述檢測區的一焊墊係透過探針與電路板底面共通線 路構成電性連接，故進行測試時，僅測試其他焊墊與前述 焊墊是否短路即可判斷出是否漏接。 别述電路板上形成有複數的線路區，其中電路板周圍 預留有板邊，各線路區周圍亦預留有板邊，而前述檢測區 係可位於電路板或線路區周圍預留之板邊上。 前述檢測區的探針係先在電路板上鑽孔，再施以穿孔 5 (請先閱讀背面之注意事項再填寫本頁) 裝 訂· .線， 卜紙張尺，5適財關家鮮（CNS)A4規格 (210 X 297^f ) 、發明說明（） 電鍍或充填導電材料所構成。 月,J述電路板係一多層電路板。 〜為使貴審查委員進一步瞭解前述目的及本發明之技 術特徵，紅附以圖式詳細說明如后： (一）圖式部分： 係本發明一較佳實施例之實施位 第二圖 第三圖 弟四圖 第五圖 第六圖 第七圖 弟八圖 且小忍 係本务明一較佳實施例之剖視圖 係本發明一較佳實施例之俯視平面圖。 係本發明一較佳實施例之底視平面圖。 係本發明一較佳實施例之使用狀態參考圖 係本發明又一較佳實施例之剖視圖。 係本冬明又較佳貫施例之俯視平面圖。 第九圖 ··係已知板邊試樣的實施位置示意圖。 (一）圖號部分··513574 A7 V. Description of the Invention The present invention relates to a circuit board detection method for detecting a circuit board circuit leakage, which can accurately detect the circuit board circuit deviation and the resulting problem. ^ The test method is used by the manufacturer to test the quality of the finished circuit board. It is mainly used to understand the details of circuit boards, especially the through holes of multilayer boards. The structure cannot be relied only on the appearance inspection: electrical test, so its structure needs to be further improved-/ ir · less sectioned: oSeCtining) microscopic inspection. As shown in the tenth figure, a schematic diagram of the finished product of the == circuit board (70) is revealed, and the middle part is a complex line of the early (71). As can be seen from the figure, the circuit board (70) ^ The edge of the circuit unit (71) is reserved with a board edge (701) with a suitable width, and the edge of the circuit unit (71) is also reserved with a board edge (711); of which: the circuit board (7 〇) The surrounding board edge (了 〇1) is used by the manufacturer to perform various actions such as clamping during the manufacturing process. As for the circuit unit (7 1) and the circuit board (70), a disconnectable form (Break- away panel), when used, it can be disconnected into an independent circuit board for packaging or other subsequent processes, and the board edge (7 1 1) reserved around the circuit unit (7 丄) is used for the aforementioned process. In addition, the “board edge sample” described in the previous disclosure is generally performed on the board edge (7Q1) around the circuit board (70), mainly because the board edge (7) reserved around the circuit board (70) 〇u has a large area, and the board edge (711) around the line unit (71) is unitized, so the area is very limited. The existing board edge sample must occupy a considerable amount of space. The self-interest method uses the line unit ( 71) board edge (711) for the aforementioned test. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page} Zhuangyi .. #_ Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (, there are μ ... description can be seen that there is a limitation in the implementation position of the existing" board edge sample ": this-the problem is actually necessary for the current implementation In addition to this problem, in addition to this problem, there are also accuracy issues: = As shown in Figure 11, the existing "board edge sample" is formed on the circuit board, where, = 2; = 1 (7〇1) Within the range, the shape of the road cutting is slowly pulled along; the line on the line area (72) ^: Zaoyuan (71) makes shapes at the same time It has the same circuit area. When testing the edge of the binding board, the micro-slicing method is used to saw the test line into the ground along the through hole, and then the saw is opened; : No, go to the center of the via hole, and then observe under the via hole with a microscope to see if it is indeed connected to the line to strengthen whether there is a missing connection.: As can be seen from the description of the above application method, first saw and then grind it. The method / knife is complicated, and its accuracy is still open to question. The immortal can only be judged by the-axis that is the same as the direction of the mine. Direction, so it is difficult to ensure the accuracy of the interpretation result. 1 stop [Who opened the mine: ri "board edge sample" Mostly the board edge sample is ordered in the diagonal position of the circuit board (70), but in fact the circuit The offset of the board (7〇) of the Intellectual Property Consumption Co., Ltd. and the offset at the diagonal are not necessarily the same. The report may be one = == 许 = 'the offset at the diagonal is outside the allowable range' … The method confirms that the line offset of that line unit (γ 丄) is still within the allowable range, and must, ', Obsolete, resulting in high costs. The entire circuit board (70) can be seen from the above, the existing "board edge sample" due to the large working space, the actual I_ 4 (CNS) A4 (mT ^ 7) _ ft economy Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property Bureau, Invention Description () = accuracy of speculation, and improved manufacturing to be further reviewed, and seek feasible solutions. Therefore, the present invention mainly aims at the process, I am a kind of circuit board detection method with a high degree of accuracy and simplicity and low cost. The proper position of the main circuit board adopted in order to achieve the aforementioned purpose is pure # 手 & A detection area to V, at least one common line in the detection area, is located on the bottom surface of the circuit board; most solder pads are located on the surface of the circuit board; alder needles, which penetrate the circuit board and are respectively located on the bottom of the pad, which constitute an electrical connection; ： 〃 Then there are multiple windows formed on the common line, each window has an increasing inner #, and is aligned with the aforementioned probes. Under normal conditions, the common line on the bottom of the circuit board and the probe are open. Test; During the test, it is only necessary to test whether there is a short-circuit between the pads, thereby detecting whether the line in the circuit area is shifted, and then determining whether there is a leakage between the line and the pad. A soldering pad of the Keshu detection area is electrically connected to the common line of the bottom surface of the circuit board through a probe. Therefore, when testing, only the other soldering pads and the aforementioned soldering pads are short-circuited to determine whether they are missing. There are multiple circuit areas formed on the circuit board. Board edges are reserved around the circuit board, and board edges are also reserved around the circuit area. The aforementioned detection area can be located on the circuit board or the board reserved around the circuit area. On the edge. The probe in the aforementioned detection area is drilled on the circuit board first, and then perforated 5 (please read the precautions on the back before filling in this page). Binding · Line, paper rule, 5 Shicai Guanjia Xian (CNS ) A4 size (210 X 297 ^ f), description of the invention () Plated or filled with conductive material. Month, J circuit board is a multilayer circuit board. ~ In order for your review committee to further understand the foregoing objectives and the technical features of the present invention, detailed drawings are attached as follows: (1) Schematic part: The implementation of a preferred embodiment of the present invention The fourth figure, the fifth figure, the sixth figure, the seventh figure, and the eighth figure, and Xiao Ni is a cross-sectional view of a preferred embodiment of the present invention, which is a top plan view of a preferred embodiment of the present invention. It is a bottom plan view of a preferred embodiment of the present invention. It is a sectional view of a use state of a preferred embodiment of the present invention. This is a top plan view of this preferred embodiment. The ninth figure is a schematic diagram of the implementation position of a known plate edge sample. (I) Drawing No. ··
係本發明又-較佳實_之底視平面圖。 m +罔係本發明又—較佳實_之夹層平面圖。 ί十圖：係-電路板之平面示意圖。 A7This is a bottom plan view of the present invention. m + 罔 is a sandwich plan view of the present invention. Figure 10: Department-a schematic plan view of a circuit board. A7
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即可瞭解線路區（1 2 ) 為例，共通線路（2 6 )上的Γ偏移狀況。以前述實施例 以各探針（2 〇 1 )〜（2。：口内徑見至少為14l«U，如共通線路（2 6 )偏移曰$ 下端外搜為4 mi 1計， 吩、匕G J偏移I超過5 口（262)孔緣即可能與對應 =、内徑的窗 此狀況下’其對應的焊墊 〇 2 )接觸，在 、共通線路（2 6)、探針（2Q 0 )構成短路，因此，當吾人谓知輝塾（二「=(21 :::即可瞭解該電路板(1。)在檢二 = 相關乾圍的線路已有偏移現象，且偏移量2 〇 )及其 而依此類移，當線路偏移量分 為5 mi1。 及8 mil時，將分別在焊墊（2 、 mU、7犯1 ⑴)〜(24)間及谭墊(21)〜3 = “二= Π2=:移量超過“11惟未超過r 0 0 ~塾（2 2 )透過探針（2 0 2 )、丘通線路 出線路的偏移=。）則未與焊塾（21)短路，故具體判斷 上述祝明可看出本發明可準確 :的偏移量，又利用本發明中供偵測用的檢測c=:; 施的位置上並不限於電路板（1〇)周圍的 )’而可擴及各線路區（1 1 )周圍的板邊 ，由於偵測點不再侷限於電路板（丄〇 )的對 角位置’而可深入至各線路區（11)，故可精確的判斷 (請先閱讀背面之注意事項再填寫本頁) 「裝 n n H ϋ n I I 兮°I I I I I i f . # n - |_ 9 ^張尺朗公爱 1½ Λ7That is to know the line area (1 2) as an example, the Γ offset status on the common line (2 6). In the foregoing embodiment, the probes (201) to (2 .: The internal diameter of the bore is at least 14l «U, such as the common line (2 6) offset. The lower end is searched for 4 mi 1 meter, phen, dagger GJ offset I is more than 5 (262) hole edges may be in contact with the corresponding =, inner diameter window under this condition 'its corresponding pad 〇2), the common line (2 6), the probe (2Q 0 ) Constitutes a short circuit, so when I say that Zhihui Yan (two "= (21 ::: you can understand that the circuit board (1.) in the detection two = the relevant trunk around the line has an offset phenomenon, and the offset 2 〇) and so on, when the line offset is divided into 5 mi1 and 8 mil, it will be between the pad (2, mU, 7 commit 1 ⑴) ~ (24) and Tan pad (21 ) ~ 3 = "Second = Π2 =: The displacement exceeds" 11 but does not exceed r 0 0 ~ 塾 (2 2) The offset of the outgoing line of the Qiaotong line through the probe (2 0 2) =.) The solder pad (21) is short-circuited, so specifically judging the above-mentioned Zhu Ming, we can see that the present invention can accurately: offset, and use the detection for detection in the present invention c = :; the position of the application is not limited to the circuit board (1〇) around) 'and can be extended around each line area (1 1) Board edge, because the detection point is no longer limited to the diagonal position of the circuit board (丄 〇) and can penetrate into each circuit area (11), so it can be accurately judged (please read the precautions on the back before filling this page) ) 「装 nn H ϋ n II xi ° IIIII if. # N-| _ 9 ^ 张 尺 朗 公 爱 1½ Λ7
電路板（1 〇 )上線路偏移量仍在容許範圍内及超出 谷星範圍以外的區域，以便保留堪用的線路區（1 1 )， 進而可有效降低成本。 又本發明亦可運用多層電路板之板邊試樣，如第六 圖二不，係本發明又一較佳實施例之剖視圖，其構造與前 貝％例大致相同（請配合參閱第七至九圖所示），不同 處在於°亥电路板（1 0 )係一多層電路板，而内部於對應 k測區（2 0 )的位置處形成有一夾層線路（丄2 )，該 夹層線路（1 2 )係對應於電路板（1 Q )底面的共通線 路（26)，又夾層線路（12)上形成有複數個等徑寬 的自口（120)(請參閱第八圖所示），各窗口（12 〇)係分別對應於各探針（2 Q丄）〜（2 Q 5)與共通 線路（26)上的窗口（262)〜（265)。 由上述可看出本發明之具體技術手段與原理特性，以 該等設計至少具備以下優點： ’ 1 ·貝轭方法簡化··本發明之漏接偵測方法係於電路 板製程中同時形成檢測區線路，利用檢測區線路與線路區 具有相同品質_性，得在無須關與研磨等繁複步驟的 前提下完成電路板的偵測。 2 ·偵測結果更為精確··由於本發明在電路板上形成 的仏測區面積小，故可形成在電路板及其上線路區周圍的 板邊上，由於偵測位置深入至線路區，故可詳細區分電路 板上符合要求與不符合要求的線路區，而避免淘汰掉仍然 堪用的線路區。 10 本紙張尺度翻t國國家標準（CNS)A4^；k⑵ο X 297公髮） (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 A7 五 、發明說明（） 板 3·降低成本：因本發明可避免廢棄仍然堪用的電路 反’故可有效降低製造成本。 的實！ί:述，本發明確已具備前述優點，其已具備顯著 請。、·，、進步性，並符合發明專利要件，爰依法提起申 經濟部智慧財產局員工消費合作社印製 本紙張 尺度適用 11 釐） c if5f先閱讀背面之注音？事項再填寫本頁}The circuit offset on the circuit board (10) is still within the allowable range and beyond the range of the valley star, in order to retain the usable circuit area (1 1), which can effectively reduce costs. Also, the present invention can also use a board edge sample of a multilayer circuit board, as shown in Figure 6 and Figure 2. It is a cross-sectional view of another preferred embodiment of the present invention, and its structure is substantially the same as that of the previous example (please refer to the seventh to the second) (Shown in Figure 9), the difference is that the circuit board (1 0) is a multi-layer circuit board, and an interlayer circuit (丄 2) is formed at a position corresponding to the k measurement area (20). The interlayer The circuit (1 2) is a common circuit (26) corresponding to the bottom surface of the circuit board (1 Q), and a plurality of self-ports (120) of equal diameter are formed on the sandwich circuit (12) (see the eighth figure) ), Each window (120) corresponds to each of the probes (2Q 丄) to (2Q5) and the windows (262) to (265) on the common line (26). From the above, it can be seen that the specific technical means and principle characteristics of the present invention have at least the following advantages with these designs: '1 · The yoke method is simplified. · The miss detection method of the present invention is formed during the circuit board manufacturing process. In the area circuit, the detection area circuit has the same quality and quality as the circuit area, and the circuit board detection can be completed without the complicated steps such as closing and grinding. 2 The detection result is more accurate. Since the area of the detection area formed on the circuit board is small, it can be formed on the edge of the board around the circuit board and the upper circuit area. Therefore, the circuit area that meets the requirements and does not meet the requirements can be distinguished in detail, and the circuit area that is still usable can be eliminated. 10 This paper has a national standard (CNS) A4 ^; k⑵ο X 297 issued) (Please read the notes on the back before filling out this page) Printed on the A7 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs () Board 3 · Cost reduction: The present invention can effectively reduce manufacturing costs because it can avoid discarding circuits that are still usable. Really! It is stated that the present invention does have the aforementioned advantages, and it has significant advantages. 、,,, and progressive, and meet the requirements of the invention patent, and filed the application according to law. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. This paper is applicable to 11%) c if5f read the phonetic on the back? Matters refill this page}