TW511254B - Manufacture method of high-density flat-unit type mask ROM - Google Patents

Abstract

A manufacture method of high-density flat-unit type mask ROM that uses compatible CMOS process and an extra mask for etching isolation layer is provided. First, implement a shallow trench isolation process to make plural shallow trenches on the substrate and then fill in a isolation layer. Second, etch the isolation layer to let it below the substrate surface a fixed distance and then form a doped poly-silicon layer on the isolation layer. Third, implement a well implantation and anneal process to let the dopant diffuse to form plural bit-lines. Where there is a channel region between every two bit-lines. Forth, sequentially form gate oxide and gate word-line and then select a part of the channel regions to be the code regions. Finally, proceed the ion implantation to the code regions.

Description

511254

V. Description of the invention (1) The present invention relates to a mask, in particular, to a high-density flat wall cell manufacturing method and special method. ~ 70 51 The traditional method of manufacturing veil-type read-only memory is to increase the record of veil-type read-only memory by making flat M_. Patent No. 5, 688, 66 No. 1 patent However, its density is not only unique, such as the U.S. Patent No. 1 read-only memory with a surface wheel that is complicated, and even this mask No. 6,034,403 is due to the characteristics of the process, In addition, the U.S. patent process is so compatible that it is impossible to use the standard and special CMOS and peripheral circuit areas. In view of this, it is impossible to form a high-density flat system with the CMOS process unit area and the surrounding area using a matched CMOS mask to manufacture a high-density implementation. A shallow trench is used to fill a predetermined distance into the isolation layer. , Then layer, and then implement a plurality of bit line areas, and then sequentially form the track area as the coding below, as shown in the figure is compatible with the invention and the flat unit process of the road unit is flat off the process, followed by this isolation well The implantation area, the gate oxygen area, can not explain the problem. The mask step and the unit type are based on the substrate etching and isolation layer surface entry and exit any two layers, and the standard for the present invention is used to implement the curtain. Adding a mask to the bottom of the screen to form a fire process. The bit line gates are formed on the surface. One of these stone horses is determined by the above process to read the memory path for the above purpose. In order to make it lower than a dopant ion so as to make the system line between the dopant regions, the selected regions are separated from each other at high density, the plane is complicated, and the memory is formed with time. The present invention provides a manufacturing method for engraving the memory of the isolation layer. . First, shallow trenches, but a complex crystal fragment on the surface of the substrate. Ion diffused to form a channel. Tan haplotype

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511254

V. Description of the invention (2)

An embodiment of a method for manufacturing a mask-type read-only memory. Brief Description of the Drawings Fig. 1 shows one of the present inventions-one you-λ. Flowchart of a method for manufacturing a curtain read-only memory. Fig. 2a shows the formation step in the embodiment of the present invention. ... < Steps to form an isolation layer shallowly, remove a part of the isolation layer, remove the pad silicon nitride layer Figure 2b ', which shows the steps in the trench in the embodiment of the present invention. Fig. 2c 'shows the steps in the embodiment of the present invention. Fig. 2d 'shows the steps in the embodiment of the present invention. Fig. 2e shows a step of forming a conductive layer doped with ions in an embodiment of the present invention. Fig. 2f 'shows a step of forming a well region, a source / drain region, and a buried bit line region in an embodiment of the present invention. Figure 2g shows the steps of removing the pad oxide layer and forming the gate oxide layer in the embodiment of the present invention. Fig. 2h shows a step of forming a gate word line in the embodiment of the present invention. Figure 2i shows the ion implantation step of the coding region in the embodiment of the present invention. [Symbol description] MO ~ substrate; 130a, 130b ~ shallow trench;

0725-6804tw \ Jessica.ptd Page 5 511254

140a'l40b ~ isolation layer 160a ~ bit line area; 180 ~ gate oxide layer; I7 0a ~ coding area; 102 ~ peripheral circuit area; II 0 ~ pad oxide layer; 103 ~ P-type well area; Example; 160 to doped ion conductive layer 170 to channel area; 190 gate word line; 1 0 to memory cell area; 1 2 5 to cushion structure; 1 2 0 ~ pad silicon nitride layer; 1 04 ~ N-type well area. 〇 Please refer to Fig. 1 and Figs. 2a to 2i, which show an ancient $ Φ early-type mask-type read-only memory manufacturing method, including ^ quilt and flat S10 to S90, because the above process system matches the CM0s process. The step-by-step process simultaneously forms the memory cell area and the peripheral circuits. For this purpose, it can be noted that first step S10 is performed to provide a substrate 100, but the user does not implement a shallow trench isolation process for the base shallow trench 130a. There are several τ bins, of which a silicon substrate 100 and a circuit area 102 are implemented. An example of the steps is shown in FIG. 2a. First, it is mentioned that the Shixi substrate has a memory cell area and a periphery.

^ ^ The second is to implement a shallow trench isolation process, for example, first on the silicon substrate surface ^ ^ / pad structure 125, which can choose from pads with a thickness of 80-20 Angstroms ^ and pads with a thickness of 1 000 ~ 2000 Angstroms The silicon nitride layer 12 is composed of 20, and then the micro-shirt process is used to transfer the shallow trench pattern to the silicon substrate 100. For example, a layer of photoresist material is laid out. After exposure and development, the pad structure 125 is etched. A part of the surface of the silicon substrate is blown out, and then a cushion structure 1 2 5 is used as a cover.

511254 V. Description of the invention (4) The curtain is engraved on the Shi Xi substrate to form shallow trenches with a depth of 250,000-45 Angstroms in the memory cell area and peripheral circuit areas. 〇b, finally remove the remaining photoresist. Step S30 is performed next to the shallow trenches 13a & 13b and an isolation layer 140a. In the embodiment of implementing the above steps, an oxide layer is formed as described above. The bran is careful # τ Η ^ m ^ .., and then a planarization step is performed, such as using a chemical mechanical polishing process to remove multiple devices. The isolation oxide layer 14/142 emulsified layer of the groove, leaving the shallow trenches S40 filled to remove part of the isolation layer, so that the isolation layer 40a is lower than the substrate surface by a predetermined distance d. An example of the steps described on the coupon is shown in Figures 2c and 2d. First, a μ 7I does not. An additional oxide etching mask is made, and then a lithography process is performed to transfer the image. To… ,, first, and bismuth ancestor γ 3, take the tea to the silicon substrate 100, for example, first coat a layer of Yuyang® ^ and cover the remaining circuit area 102, 90, where this remaining Structure of photoresist layer 1 50 and pad layer 丨 π., Λ a…, and then perform an etching step, such as the use of oxidation sound tf rat fossil evening layer in the remaining selection ratio of 3 / with the emulsion layer to the unit area 101 Zhiling Chi broadcast # ey The dry etching on the 乂, the remaining time in the shallow trench of the oxide layer in the memory dagger U 1 < fire trench 14 ft, 14 minutes, so that d, for example It is about 0.1 Um. / The predetermined distance of the bottom surface of the soil and then 'see Figure 2d, after the oxide layer is etched to remove the remaining photoresistance sound 1502 /' After the completion of the engraving step, 丄 人 + You layer 1 b U and choose to Phosphoric acid dissolving pan, t, and red ”is a step of removing the silicon nitride layer from the pad.仃 / ”、、 Eclipse

511254 5. Description of the invention (5) " Then step S50 is performed to form a conductive layer of doped ions with a thickness of 1000 to 2000 angstroms on the surface of the isolation layer 14a. The embodiment for realizing the above steps is shown in FIG. 2e. First, a polycrystalline silicon layer of N-type doped ions is deposited in a comprehensive manner. For example, a chemical vapor deposition process is used to form an in-situ doped ion. ) And then etch back the polycrystalline silicon layer to form a planarized doped ion polycrystalline silicon layer 160 on the surface of the oxide layer 140a under the condition that the selection ratio is greater than 10, wherein the doped ions can select phosphorus ions. . Then step S60 is performed, which uses a well region implantation and annealing process to diffuse the dopant ions of the conductive layer 160 to form a plurality of buried bit line regions 160a, wherein any two bit line regions are formed between them. A channel region 1700 in which the above steps are implemented is shown in FIG. 2f, using a double-well or Mitsui implantation process and an annealing process in a standard, CMOS process to form the Shixi substrate in the memory cell region 101. A p-type well region 103 and a P-type well region 103 and an N-type well region 104 are formed on the silicon substrate of the peripheral circuit region 102. The doped ions diffuse from the sidewall of the polycrystalline silicon layer during the annealing process. A plurality of N-type bit line regions 16 0 a are formed, and a channel region 170 is formed between any two N-type bit line regions. Then, step S 70 is performed to sequentially form a gate oxide layer 180 and a gate word line 19a across the bit line regions 160a and the channel regions 170. The embodiment for realizing the above steps is shown in Figs. 2g and 2h. Please refer to Fig. 2g. First, the pad oxide layer 11 is etched and removed to expose the surface of the silicon substrate. Then a thermal oxidation step is performed to form a gate electrode. Oxide layer 丨 8 〇

0725-6804tw »Jessica.ptd Page 8 511254 5. In the description of the invention (6), since the doped ions in the polycrystalline silicon layer 160 can promote the oxidation rate, the gate oxide layer i8〇b on the surface of the doped ion polycrystalline silicon layer 160 The thickness is larger than the gate oxide layer 180a formed on the surface of the silicon substrate in the memory cell region and the peripheral circuit region. Then, referring to FIG. 2h, a gate word process in a standard CMOS process is used to form a gate oxide region 180 on the surface of the gate oxide layer 18 of the memory cell region 101 respectively. And the gate word line 190 in the channel area 17 and the gate oxide layer 180 on the peripheral circuit area 10 & the gate word line 1 90b, and then implement the source / drain ion The implantation step is to form N-type source / drain (S / D) in the P-type well area of the peripheral circuit area, and then implement step 0 in the week, and first select a part of the channel area as the code = 1.7. &, and then implement step S90 to perform ion cloth on the coding regions 1703. The embodiment for realizing the above steps is shown in FIG. 2i. First, a layer of photoresist is coated after exposure, and after exposure = The patterned photoresist layer 200 'This patterned photoresist layer 200 has a surface of the gate word line i9oa in the coding area, and the patterned photoresist layer 2GG is a mask. 170a = 2) Ion implantation of these coding areas to improve the coding area-the Twilight on (), and then form a normally off mask only Read memory. [Effect of the invention] Page 9 0725-6804tw > Jessica.ptd 511254 E. Description of the invention (7) Because of tradition, the desire is flat, and the + # system > present _ i β-type curtain Method for manufacturing read-only memory 'ϋ ν Suddenly, it is complicated or needs to be used only in addition-the simple oxide layer, the process! In this step, a mask-type read-only memory with a high flatness and an early shape can be fabricated in the memory cell region 101 at the same time, and a CMOS transistor structure can be fabricated in the peripheral circuit region 102. % Although the present invention has been disclosed in the preferred embodiment, such as Ji, it is not intended to limit it to the present invention. Any person skilled in this art will not deviate from the spirit and scope of the present invention, but can make some changes and retouches. Therefore, the scope of protection of the present invention should be defined as:

Claims (1)

511254 6. Application scope 1. A method for manufacturing a high-density flat cell read-only read-only memory includes the following steps: a substrate and a shallow trench isolation process to form a plurality of shallow trenches in the substrate to provide an implementation trench; A predetermined distance from the removed sections; a plurality of buried passage areas are implemented on the partition; the sequential shape layer and the gate word selection section only read these 2 as the application of the mask; form a shallow trench for the pad . 3. If an isolation layer is filled in the read-only shallow trench of the curtain type; divide the isolation layer so that the isolation layer is lower than the surface of the substrate and form a conductive layer doped with ions; Annealing and annealing processes to diffuse the dopant ions to form a bit line region, in which any two bit line regions form a gate element line that spans the bit line regions and channel regions; The divided channel region is used as the coding region; and the coding region is ion implanted. Please refer to the high-density flat cell type a memory device manufacturing method described in item 1 of the patent, wherein 'the shallow trench isolation process has a cladding structure on the substrate surface; a layer structure and a substrate implementation / lithographic process, In order to form a plurality of high-density flat cell type memory manufacturing methods as described in item 2 of the patent scope, wherein the pad structure is composed of a pad 511254, a patented oxide layer and a silicon nitride layer . 4. The method of manufacturing a single-screen read-only memory of the high-density flat cell type according to item 3 of the scope of the patent application, wherein the isolation layer is composed of an oxide layer. 5. The method of manufacturing a military curtain read-only memory of a high-density flat cell type as described in item 4 of the scope of patent application, wherein the step of forming the isolation layer includes: forming an oxide layer comprehensively; implementing a planarization step To leave the isolation oxide layer filling the shallow trenches. 6. The method for manufacturing a mask-type read-only memory of a high-density flat cell type as described in item 5 of the scope of the patent application, wherein the step of removing a part of the isolation layer includes: making an oxide layer etching mask; The etched mask of the oxide layer performs a lithography process to remove the isolation oxide layer for the removed portion and make the isolation oxide layer a predetermined distance below the surface of the substrate. 7. The method of manufacturing a mask-type read-only memory of a high-density flat cell type according to item 6 of the scope of the patent application, wherein the micro-view > process includes an etching step, which pads silicon nitride with an oxide layer A dry etching method with a layer etching selectivity of 3 ·· 1 is used to remove part of the isolation oxide layer. 8. The method of manufacturing a mask-type read-only memory of a high-density flat cell type as described in item 丨 of the patent application range, wherein the large-scale system of the isolation layer is lower than the surface of the substrate by 0.1 μm. 0725-6804tw * Jessica.ptd Page 12 511254 VI. Application for patent scope 9 · The manufacturing method of the mask-type read-only memory of the high-density flat cell type described in item 1 of the scope of patent application, wherein the dopant ion The conductive layer is composed of a polycrystalline silicon layer doped with ions in the environment. 1 0. The manufacturing method of a mask-type read-only memory of a high-density flat cell type as described in item 1 of the scope of patent application, wherein the gate oxide layer is formed by a thermal oxidation method, so that the dopant ion is located at the dopant ion. The thickness of the gate oxide layer on the surface of the conductive layer is higher than a portion located on the surface of the substrate. I 0725-6804tw; Jessica.ptd page 13