509986 A7 B7___ 五、發明說明（丨） 發明領域 (請先閱讀背面之注音？事項再填寫本頁) 本發明係關於氧化層的形成方法’尤其係關於在一溝 槽中非等向性形成氧化層的方法。 發明背景 半導體記憶元件，如動態隨機存取記憶體’通常係由 許多包含儲存節點的記億單元所構成。現今較常使用之隨 機存取記憶體，爲了增加縮小之記憶單元的電容量’幾乎 淸一色系採用溝槽形式的構型。而儲存單元的存取’則須 依賴一存取電晶體，如一垂直式電晶體。透過存取電晶體， 即可允許電荷儲存於儲存節點，或可從儲存節點中擷取電 荷。這類的半導體儲存元件的儲存節點都必須與閘極導電 層電性絕緣。 經濟部智慧財產局員工消費合作社印製 一種確保儲存節點的絕緣方法係’於儲存節點的上面 形成一溝槽頂絕緣層。儲存節點通常包括一多晶矽材料部 份塡充於溝槽內。首先沉積一氧化層（二氧化矽）於此半 導體的表面上並沉積充塡於前述多晶矽材料之上。基板上 除溝渠外其他部分的氧化層都以平坦化的方式除去，並以 蝕刻的方式將溝槽中的氧化層部份移除’只留下預定厚度 的氧化層。單單只有此氧化層可能無法提供充足且可靠的 電性絕緣。而且由於氧化層鈾刻的控制不易’也使得殘餘 之氧化層的厚度變化很大，而這是動態隨機存取記憶體製 程所不能容許的。 4PROMOS/200105TW, 90041 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐) " 一 509986 A7 B7__ 五、發明說明（χ) 當垂直電晶體設置於記憶裝置時，儲存節點中作爲埋 入式傳導帶的部份必須向外擴散以與垂直電晶體的通道連 接。所以當垂直電晶體在「ON」的狀態時，一位元線（bit line)即與儲存節點電性導通。此通道必須與閘極導電層電 性絕緣，所以兩者之間必須設置一絕緣層。通常的做法是 氧化部份溝槽中閘極氧化層之多晶矽。 許多先前技術在此方面做過許多努力。如美國專利案 第6184091號中，Ulrike等人提出選擇性沉積氧化層的方 法。請參考圖la，一半導體裝置1〇〇具有一基板1〇1，基 板101上具有一氧化保護層102與一氮化物保護層103。一 溝槽104穿過此氧化保護層1〇2與氮化物保護層103形成 於基板101中。溝槽104中具有一套管105以使溝槽104 的一部份與基板101電氣絕緣。溝槽104中塡充以一導電 材料106。導電材料1〇6延伸突出於套管之外，突出部份 並與基板101接觸。此時溝槽104上方仍保有一凹洞107。 一埋入式導電帶108形成於溝槽中。若以凹洞107的角度 觀之，凹洞107具有一底面1〇9與一周壁110。底面109 即爲埋入式傳導帶108的頂表面。 請參考圖lb，當欲形成一溝槽頂氧化層時，該方法先 形成一氮化層111於周壁110上。形成氮化層111時，必 須先沉積一氮化層111於氮化物保護層103、底面109與周 壁110上。在此氣此層111通常係爲氮化矽所構成。然後 再移除除了周壁110外其他表面上的氮化層111。再以化 學氣相沉積法的方式形成一 SACVD ( sub-atmospheric 4PROMOS/200105TW, 90041 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅2事項再填寫本頁)509986 A7 B7___ V. Description of the invention (丨) Field of invention (please read the note on the back? Matters before filling out this page) The present invention relates to the method of forming an oxide layer, especially to the anisotropic formation of oxidation in a trench Layer approach. BACKGROUND OF THE INVENTION Semiconductor memory elements, such as dynamic random access memory ', are usually made up of a number of hundreds of millions of cells containing storage nodes. Nowadays, the random access memory which is more commonly used today, in order to increase the capacitance of the reduced memory cell ', almost one color is a grooved configuration. The access of the memory cell depends on an access transistor, such as a vertical transistor. By accessing the transistor, the charge can be stored in the storage node, or the charge can be retrieved from the storage node. The storage nodes of such semiconductor storage elements must be electrically insulated from the gate conductive layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. An insulation method to ensure the storage node is to form a trench-top insulation layer on the storage node. The storage node usually includes a portion of polycrystalline silicon material filled in the trench. First, an oxide layer (silicon dioxide) is deposited on the surface of the semiconductor and deposited on the polycrystalline silicon material. The oxide layer on the substrate except for the trench is removed in a flattened manner, and the oxide layer in the trench is removed by etching ', leaving only an oxide layer of a predetermined thickness. This oxide layer alone may not provide sufficient and reliable electrical insulation. Moreover, because the control of the oxide layer is not easy to control, the thickness of the remaining oxide layer also changes greatly, which is not allowed by the dynamic random access memory system. 4PROMOS / 200105TW, 90041 1 This paper size is applicable to Chinese National Standard (CNS) A4 (210 x 297 mm) " One 509986 A7 B7__ V. Description of the invention (χ) When the vertical transistor is set in the memory device, the storage node The part in the middle which is an embedded conduction band must diffuse outward to connect with the channel of the vertical transistor. Therefore, when the vertical transistor is in the "ON" state, a bit line is electrically connected to the storage node. This channel must be electrically insulated from the gate conductive layer, so an insulating layer must be placed between the two. A common practice is to oxidize the polycrystalline silicon in the gate oxide layer in some trenches. Many previous technologies have made many efforts in this regard. For example, in U.S. Patent No. 6,181,091, Ulrike et al. Proposed a method for selectively depositing an oxide layer. Referring to FIG. 1a, a semiconductor device 100 has a substrate 101, and a substrate 101 has an oxide protection layer 102 and a nitride protection layer 103. A trench 104 is formed in the substrate 101 through the oxidation protection layer 102 and the nitride protection layer 103. The trench 104 has a set of tubes 105 therein to electrically insulate a part of the trench 104 from the substrate 101. The trench 104 is filled with a conductive material 106. The conductive material 106 extends beyond the sleeve, and the protruding portion contacts the substrate 101. At this time, a recess 107 remains above the trench 104. A buried conductive strip 108 is formed in the trench. Viewed from the angle of the cavity 107, the cavity 107 has a bottom surface 109 and a peripheral wall 110. The bottom surface 109 is the top surface of the embedded conductive tape 108. Referring to FIG. 1b, when a trench top oxide layer is to be formed, the method first forms a nitride layer 111 on the peripheral wall 110. When the nitride layer 111 is formed, a nitride layer 111 must be deposited on the nitride protective layer 103, the bottom surface 109, and the peripheral wall 110 first. This layer 111 is usually made of silicon nitride. Then, the nitride layer 111 on the other surfaces except the peripheral wall 110 is removed. Then, a SACVD (sub-atmospheric 4PROMOS / 200105TW, 90041 2) was formed by chemical vapor deposition. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back 2) (Fill in this page again)
» ϋ .^1 ·1_ 1 i_i n ϋ —Bi I 經濟部智慧財產局員工消費合作社印製 509986 五 經濟部智慧財產局員工消費合作社印制衣 A7 B7 發明說明（3)»Ϋ. ^ 1 · 1_ 1 i_i n ϋ —Bi I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 509986 Five Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Invention Description (3)
chemical vapor deposition )層 112 於氮化物保護層 1〇3、底 面1〇9與周壁11〇上。此SACVD層1Π通常爲氡化矽或四 乙氣碁矽（tetraethoxysilane，TE〇S)所構成。由於此SACVD 層112於矽上成長的速率比氣北物要快上5倍，所以於底 面109上形成的SACVD層112的厚度約爲氮化物保護層 103與周壁110上SACVD層112的厚度的五倍。也因爲如 此，可以輕易移除p化物保護層103與周壁11〇上SACVD 層；112，而只在底面109上留下SACVD層112，如圖lc所 示。而於後續的製程中，該發明會移除周壁11〇上的氮化 層111，並形成一氧化層113於周壁11〇上，如圖μ所示， 供作爲閘極氧化層之用。 由所提出的前案觀之，先前技術形成溝槽頂氧化層的 手續繁瑣，且先沉積再進行蝕刻的方式，在鈾刻的過程中 變數很多，可靠性不足。閘極氧化層也必須要在先移除氮 化層111之後才能另外進行。爲增進良率、減少製程步驟、 降低生產成本，實有必要存在步驟更少且良率更高的方 法，以形成溝槽頂氧化層與閘極氧化層。 發明目的與槪述 本發明的一目的在於提供一種方法，以用較少的步驟 形成溝槽頂氧化層與閘極氧化層。 本發明的另一目的在於提供一種方法，以同時形成溝 槽頂氧化層與閛極氧化層。 本發明的方法可形成一厚氧化層於~溝槽的一底面 4PROMOS/200105TW, 90041 . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 严---ί ί丨訂------- 509986 A7 __B7__ 五、發明說明（爷） 上，並形成一薄氧化層於溝槽的一周壁上，其中溝槽係位 於一基板上，周壁係與底面垂直。本發明的方法包含下列 步驟：以平行該周壁的方向植入惰性氣體離子於該底面上 的步驟；以及以熱氧化法對該基板進行熱處理，以形成該 厚氧化層於該底面上，並形成該薄氧化層於該周壁上的步 圖式之簡單說明 圖la係爲先前技術一半導體元件之溝槽中尙未沉積 一氮化層的示意圖； 圖lb係爲先前技術一半導體元件之溝槽中沉積一氮 化層與一 SACVD層後之示意圖； 圖lc係爲先前技術一半導體元件之溝槽的底面上具 有一 SACVD層的示意圖； 圖Id係爲先前技術一半導體元件之溝槽的周壁上具 有一氧化層的示意圖； 圖2a係爲依照本發明之方法對一半導體元件進行惰 性氣體離子植入的示意圖； 圖2b係爲依照本發明之方法對一半導體元件進行熱 氧化後的示意圖； 圖3係爲氬離子劑量與氧化層厚度之間關係的示意 圖；以及 圖4係爲本發明之方法的流程圖。 4PROMOS/200105TW, 90041 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)chemical vapor deposition) layer 112 is on the nitride protective layer 103, the bottom surface 109 and the peripheral wall 110. The SACVD layer 1Π is usually composed of trihalide or tetraethoxysilane (TEOS). Since the SACVD layer 112 grows on silicon at a rate five times faster than that of gas-based materials, the thickness of the SACVD layer 112 formed on the bottom surface 109 is approximately the same as that of the nitride protective layer 103 and the SACVD layer 112 on the peripheral wall 110. Five times. Because of this, the pCVD protection layer 103 and the SACVD layer 112 on the peripheral wall 110 can be easily removed, and only the SACVD layer 112 is left on the bottom surface 109, as shown in FIG. In the subsequent process, the invention will remove the nitride layer 111 on the peripheral wall 110 and form an oxide layer 113 on the peripheral wall 110, as shown in FIG. Μ, for use as a gate oxide layer. According to the proposed previous case, the prior art has a complicated procedure for forming the oxide layer on the top of the trench, and the method of depositing and etching first has a lot of variables during the uranium etching process, and its reliability is insufficient. The gate oxide layer must be removed after the nitride layer 111 is removed. In order to improve yield, reduce process steps, and reduce production costs, it is necessary to have a method with fewer steps and higher yield to form a trench top oxide layer and a gate oxide layer. OBJECTS AND DESCRIPTION OF THE INVENTION An object of the present invention is to provide a method for forming a trench top oxide layer and a gate oxide layer with fewer steps. Another object of the present invention is to provide a method for simultaneously forming a trench top oxide layer and a hafnium oxide layer. The method of the present invention can form a thick oxide layer on the bottom surface of the trench 4PROMOS / 200105TW, 90041. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back first (Fill in this page again) Strict --- ί 丨 Order ------- 509986 A7 __B7__ 5. Description of the Invention (Master), and a thin oxide layer is formed on the peripheral wall of the trench, where the trench is Located on a substrate, the peripheral wall is perpendicular to the bottom surface. The method of the present invention includes the following steps: a step of implanting inert gas ions on the bottom surface in a direction parallel to the peripheral wall; and thermally treating the substrate by a thermal oxidation method to form the thick oxide layer on the bottom surface and forming Simple illustration of the step pattern of the thin oxide layer on the peripheral wall. FIG. 1a is a schematic diagram of a semiconductor device in which a nitride layer has not been deposited in the prior art. FIG. 1b is a trench of a semiconductor device in the prior art. A schematic view of a nitride layer and a SACVD layer deposited in the middle; FIG. Lc is a schematic view of a SACVD layer on the bottom surface of a trench of a semiconductor device in the prior art; FIG. Id is a peripheral wall of a trench of a semiconductor device in the prior art Figure 2a is a schematic diagram of an oxide layer; Figure 2a is a schematic diagram of inert gas ion implantation of a semiconductor element according to the method of the present invention; Figure 2b is a schematic diagram of a semiconductor element after thermal oxidation according to the method of the present invention; FIG. 3 is a schematic diagram showing the relationship between the argon ion dose and the thickness of the oxide layer; and FIG. 4 is a flowchart of the method of the present invention. 4PROMOS / 200105TW, 90041 4 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
> ϋ —ϋ ϋ ϋ ϋ 一trjI n ϋ ϋ ϋ 1 I 經濟部智慧財產局員工消費合作社印製 509986 A7 B7五、發明說明（S ) 經濟部智慧財產局員工消費合作社印制衣 圖式之元件符號說明 先前技術 100半導體裝置 101基板 102氧化保護層 103氮化物保護層 104溝槽 105套管 106導電材料 107凹洞 108埋入式傳導帶 109底面 110周壁 111氮化層 112 SACVD 層 113氧化層 本發明 200半導體裝置 201基板 202氧化保護層 203氮化物保護層 204溝槽 205套管 206導電材料 207埋入式傳導帶 208凹洞 209底面 210周壁 211厚氧化層 212薄氧化層 發明之詳細說明 請參考圖2a，一半導體裝置200 (僅部份顯示）包含 一基板201。基板201上具有一氧化保護層202，而此氧化 保護層202上具有一氮化物保護層203。基板201中具有一 溝槽204。溝槽204中具有一套管205。套管205可以多種 4PROMOS/200105TW, 90041 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -售裝 -*^1 ϋ —.1 ϋ 一 0, 1_ II ϋ 1 ϋ I · 509986 A7 B7 五、發明說明（b 材料與方式形成，㈣難本雛㈣所_且實施者。 套管205中充塡以一導電材料2〇6，此導電材料2〇6通常係 爲多晶矽。此導電材料2〇6突出於套管2〇5外，其兩側與 基板201接觸以形成一埋入式傳導帶2〇7。此時溝槽2〇4 於圖式下方的部份被導電材料2〇6塡滿，可是溝槽2〇4上 方仍保有一凹洞2〇8。若以凹洞208的角度觀之，凹洞208 具有一底面209與一周壁210。底面209即爲埋入式傳導帶 207的頂表面。若此半導體裝置2〇〇爲一動態隨機存取記 憶體時，此凹洞208係位於一溝槽電容器（即溝槽204與 導電材料206形成之結構）的上方，且此凹洞208的底面 209位於埋入式傳導帶207的頂部。 本發明的方法首先以平行周壁210的方向（如圖2a中 箭頭所示方向）植入惰性氣體離子於底面209上與氮化物 保護層203的表面上。植入惰性氣體離子的能量約係在 5〜lOOKeV之間，較佳係在15〜40KeV的範圍內。由於惰性 氣體離子植入時的高度方向性，周壁210實質上不受惰性 氣體離子的侵襲。在此所謂之惰性氣體，由於成本與效果 的考量，主要係包括氖、氬與氪，其中又以氬爲最常使用 者。 然後，如圖2b所示，本發明之方法以熱氧化法對周壁 210與底面209進行熱處理。根據經驗與實驗的結果’經 過離子植入的基板與多晶矽’在熱氧化的過程中生成氧化 矽的速率是沒有經過離子植入的二倍到三倍之多。 請參考圖3，大約從氬離子劑量爲l.6E+l4/cm2開始， 4PROMOS/200105TW，90041 6 ^紙張尺度賴巾關家鮮（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)> ϋ —ϋ ϋ ϋ ϋ 1 trjI n ϋ ϋ ϋ I 1 I Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 509986 A7 B7 V. Description of the Invention (S) Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economy Element Symbol Description Prior Art 100 Semiconductor Device 101 Substrate 102 Oxidation Protective Layer 103 Nitride Protective Layer 104 Trench 105 Sleeve 106 Conductive Material 107 Cavity 108 Buried Conductive Tape 109 Bottom Surface 110 Peripheral Wall 111 Nitride Layer 112 SACVD Layer 113 The present invention 200 semiconductor device 201 substrate 202 oxidation protection layer 203 nitride protection layer 204 trench 205 sleeve 206 conductive material 207 buried conductive tape 208 recess 209 bottom surface 210 peripheral wall 211 thick oxide layer 212 thin oxide layer invention details Please refer to FIG. 2 a for description. A semiconductor device 200 (only partially shown) includes a substrate 201. An oxidation protection layer 202 is provided on the substrate 201, and a nitride protection layer 203 is provided on the oxidation protection layer 202. The substrate 201 has a trench 204 therein. The trench 204 has a set of tubes 205 therein. The sleeve 205 can be a variety of 4PROMOS / 200105TW, 90041 5 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -Sale-* ^ 1 ϋ —.1 ϋ 一 0, 1_ II ϋ 1 ϋ I · 509986 A7 B7 V. Description of the invention (b Materials and methods are formed, which is difficult for the company and its implementation. The sleeve 205 is filled with a conductive material This conductive material 206 is usually polycrystalline silicon. This conductive material 206 protrudes out of the sleeve 205, and both sides of the conductive material 206 are in contact with the substrate 201 to form a buried conductive tape 207. This At the time, the portion of the groove 204 below the figure is filled with the conductive material 206, but there is still a cavity 208 above the groove 204. If viewed from the angle of the cavity 208, the cavity is 208 has a bottom surface 209 and a peripheral wall 210. The bottom surface 209 is the top surface of the embedded conductive strip 207. If the semiconductor device 200 is a dynamic random access memory, the recess 208 is located in a trench Above the capacitor (ie, the structure formed by the trench 204 and the conductive material 206), and the bottom surface 209 of the recess 208 is located on the buried conductive strip 20 7. The method of the present invention first implants inert gas ions on the bottom surface 209 and the surface of the nitride protective layer 203 in a direction parallel to the peripheral wall 210 (as indicated by the arrow in FIG. 2a). The energy is about 5 ~ 10OKeV, preferably in the range of 15 ~ 40KeV. Due to the high directivity when inert gas ions are implanted, the peripheral wall 210 is substantially not attacked by inert gas ions. The so-called inertness here Gases, due to cost and effect considerations, mainly include neon, argon, and krypton, among which argon is the most common user. Then, as shown in FIG. 2b, the method of the present invention uses thermal oxidation to treat the peripheral wall 210 and bottom surface 209 Heat treatment. According to the results of experience and experiments, the substrate and polycrystalline silicon undergoing ion implantation generate silicon oxide at a rate of two to three times as high as that without ion implantation. Please refer to Figure 3, Starting from the argon ion dose of 1.6E + l4 / cm2, 4PROMOS / 200105TW, 90041 6 ^ Paper size Lai Jin Guan Jia Xian (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before Write this page)
• n ϋ I n I ϋ ϋ 一 I n 1_1 ϋ I 鲁 經濟部智慧財產局員工消費合作社印製 509986 A7 B7 五、發明說明（7) 氧化層厚度會隨著氬離子劑量的增加而升高。因爲之前底 面209係經過惰性氣體離子植入，而周壁21〇則沒有，所 以當進行熱氧化反應時，可同時形成一厚氧化層211於底 面209上供作爲溝槽頂氧化層，並形成薄氧化層212於該 周壁210上供閘極氧化層之用。 請參考圖4，其係圖示爲本發明方法之流程圖，此方 法使用於如圖2a所示之半導體裝置200。半導體裝置200 (僅部份顯示）包含一基板2〇1。基板201上具有一氧化 保護層202，而此氧化保護層202上具有一氮化物保護層 203。基板201中具有一溝槽204。溝槽204中具有一套管 205。套管205可以多種材料與方式形成。套管205中充塡 以一導電材料206，此導電材料206通常係爲多晶矽。此 導電材料206突出於套管205外，其兩側與基板201接觸 以形成一埋入式傳導帶207。此時溝槽2〇4於圖式下方的 部份被導電材料206塡滿，可是溝槽204上方仍保有一凹 洞208。若以凹洞208的角度觀之，凹洞208具有一底面 209與一周壁210。底面209即爲埋入式傳導帶207的頂表 面。 於步驟401中，以平行周壁210的方向植入惰性氣體 離子於底面209上。接著，於步驟402中，以熱氧化法對 基板201進行熱處理，以形成如圖2b所示之一厚氧化層 211於底面209上，並形成一薄氧化層212於周壁210上。 熟悉本項技術者應該淸楚了解，本發明可以在不脫離 本發明的精神與範圍下，以許多其他特定形式加以實施。 4PROMOS/200105TW, 90041 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 輪裝 訂--------- 經濟部智慧財產局員工消費合作社印製 509986 A7 B7 五、發明說明（X) 因此，現在提供的實施例應該被當作說明性的，而不是限 制性的，此發明不受文中所給細節的侷限，而可以於隨附 申請專利範圍的範圍內作均等的變化與修改。 (請先閱讀背面之注意事項再填寫本頁)• n ϋ I n I ϋ ϋ 1 I n 1_1 ϋ I Lu Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 509986 A7 B7 V. Description of the invention (7) The thickness of the oxide layer will increase with the increase of the argon ion dose. Because the bottom surface 209 was previously implanted with inert gas ions, and the peripheral wall 21 was not, when the thermal oxidation reaction is performed, a thick oxide layer 211 can be simultaneously formed on the bottom surface 209 as a trench top oxide layer, and a thin layer is formed. The oxide layer 212 is used for the gate oxide layer on the peripheral wall 210. Please refer to FIG. 4, which is a flowchart of a method of the present invention. This method is used in the semiconductor device 200 shown in FIG. 2a. The semiconductor device 200 (only partially shown) includes a substrate 201. The substrate 201 has an oxide protection layer 202, and the oxide protection layer 202 has a nitride protection layer 203. The substrate 201 has a trench 204 therein. The trench 204 has a set of tubes 205 therein. The sleeve 205 can be formed in a variety of materials and ways. The sleeve 205 is filled with a conductive material 206, and the conductive material 206 is usually polycrystalline silicon. The conductive material 206 protrudes out of the sleeve 205, and both sides of the conductive material 206 are in contact with the substrate 201 to form an embedded conductive tape 207. At this time, the portion of the trench 204 below the figure is filled with the conductive material 206, but a cavity 208 remains above the trench 204. Viewed from the angle of the cavity 208, the cavity 208 has a bottom surface 209 and a peripheral wall 210. The bottom surface 209 is the top surface of the embedded conductive tape 207. In step 401, inert gas ions are implanted on the bottom surface 209 in a direction parallel to the peripheral wall 210. Next, in step 402, the substrate 201 is heat-treated by a thermal oxidation method to form a thick oxide layer 211 as shown in FIG. 2b on the bottom surface 209, and a thin oxide layer 212 is formed on the peripheral wall 210. Those skilled in the art should understand that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the invention. 4PROMOS / 200105TW, 90041 7 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Wheel binding --------- Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 509986 A7 B7 V. Invention Description (X) Therefore, the embodiments provided now should be regarded as illustrative, not restrictive, and the invention is not limited by the details given in the text , And can make equal changes and modifications within the scope of the accompanying patent application. (Please read the notes on the back before filling this page)
* ·ϋ —ϋ ϋ ·ϋ ϋ 一口 f I t n ϋ I ·ϋ I 經濟部智慧財產局員工消費合作社印製 4PROMOS/200105TW, 90041 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）* · Ϋ —ϋ ϋ · ϋ ϋ ϋ f I tn ϋ I · ϋ I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4PROMOS / 200105TW, 90041 This paper size applies to China National Standard (CNS) A4 (210 X 297) %)