TW508741B - Method for manufacturing dual damascene structure - Google Patents

Abstract

The present invention provides a method for manufacturing dual damascene structure on a surface of a semiconductor chip. The semiconductor chip includes a substrate and a conductive layer formed on the substrate. The method comprises: first, sequentially forming a first passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer on the surface of the semiconductor chip; then, etching the third dielectric layer to form the pattern of an upper trench of the dual damascene structure; next, etching the third passivation layer and the second dielectric layer until reaching the surface of the second passivation layer; forming the pattern of a lower via hole of the dual damascene structure; then, removing the third passivation layer and second passivation layer without being covered by the third dielectric layer and second dielectric layer; next, using the third dielectric layer and second passivation layer as a hard mask to remove the second dielectric layer and first dielectric layer until reaching the surface of the first passivation layer; and finally removing the second passivation layer and first passivation layer without being covered by the second dielectric layer and first dielectric layer until reaching the surface of the conductive layer, thereby completing the manufacture of the dual damascene structure.

Description

508741 V. Description of the invention (1) Field of the invention The present invention provides a method for forming a dual damascene structure on the surface of a semiconductor wafer. Background Description The dual damascene process is a method capable of forming a metal wire and a plug (p 1 ug) stacked structure at the same time. The dual damascene structure is used to connect various layers in a semiconductor wafer. The different components and wires' are separated from other components by inter-layer dielectrics around them. Therefore, as the development of integrated circuits becomes more sophisticated and complex, how to improve the yield of the dual mosaic structure is an important issue in the current integrated circuit manufacturing process. Please refer to FIG. 1 to FIG. 5, which are schematic diagrams of a conventional method for fabricating a double post-mounting structure 36 on the surface of the semiconductor wafer 10 using a via-first dual-mounting process of contact windows. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 12, a conductive layer 14 disposed in a predetermined region of a surface layer of the substrate 12, and a passivation layer composed of silicon nitride (SiN). 16 covers the substrate 12 and the conductive layer 14 horizontally. A first dielectric layer 18 made of silicon oxide (Si 02) is disposed above the protective layer 16 and a second oxide layer. A second dielectric layer 20 made of silicon is provided on the first dielectric layer 18

Page 5 508741 V. Description of the invention (2) Above. Among them, the protective layer 16, the first dielectric layer 18, and the second dielectric layer 20 can all be made from bottom to top by the enhanced plasma chemical vapor deposition method (p 1 asma-enhanced chemical vapor deposition, PECVD). Made by sequential deposition. As shown in FIG. 1, a conventional method for forming a dual damascene structure 36 is to first uniformly coat the surface of the second dielectric layer 20 with a yellow photolithography process—a first photoresist. ) Layer 22, and an opening 24 is formed in a predetermined area of the first photoresist layer 22 directly above the conductive Φ layer 14 to the surface of the second dielectric layer 20, and is used as a pattern defining the plug of the dielectric layer. (Via pattern). Next, as shown in FIG. 2, an anisotropic dry etch process is performed, and the second dielectric layer 2 not covered by the first photoresist layer 22 is removed vertically downward along the opening 24. 〇 and the first dielectric layer 18 ′ to form—holes 26 that reach the surface of the protective layer 16. Subsequently, a photoresist stripping process is performed to completely remove the first photoresist layer 2 2. As shown in FIG. 2, a yellow light process is used again to uniformly coat a first dielectric layer on the second dielectric layer side. The two photoresist layers 28 fill the holes 26, and the first photoresist layer 28 is a positive photoresist. As shown in the figure, when the semiconductor wafer 10 is subjected to the exposure and development steps, the flat light 30 from j passes through a mask 32 mainly composed of glass, and then a second light composed of a photosensitive material is requested. On the photoresist layer 28 to transfer """ on the photomask 32 to the second photoresist layer 28. Since the second photoresist layer 28 is of a positive type

508741 V. Description of the invention (3) Photoresist composition, the second photoresist layer 2 8 in the light receiving part will be decomposed into a kind of structure easily soluble in developing solution after exposure ', and then N a 0 Η or K 0 Η The isotropic solution is used as a developer. The exposed photoresist layer is removed by a neutralization reaction. As shown in FIG. 5, after the exposure and development steps, a linear opening 3 4 is formed on the second photoresist layer 28 to define a wiring line pattern connecting the metal wires between the components. Since the conventional method for manufacturing the dual damascene structure 36 on the semiconductor wafer 10 is to place the semiconductor wafer 10 in a lithographic equipment to perform the exposure and development procedures to define the pattern of the metal wires. However, as the semiconductor process becomes more and more precise, the height and width of the holes 26 are relatively large, making the photoresist layer filled in the bottom of the holes 26 not easily irradiated by a sufficient beam, so the positive photoresist in this part will not dissociate into It is soluble in the structure of the developer, and when the photoresist layer that is chemically reacted by exposure is subsequently removed by the developer, the photoresist layer at the bottom of the hole 26 will not be able to generate an acid-base neutralization reaction with the developer and will be completely removed. except. These residual photoresists, which remain at the bottom of the holes because they have not been exposed to light, may form a polymer layer in the subsequent process of engraving and accumulate at the corners, causing a hole phenomenon in the interposer. 〇 pe η), and then affect the electrical performance of the entire semiconductor integrated circuit. Summary of invention

Page 7 508741 • State clearly (4) to further improve yield. In a preferred embodiment of the present invention, a first protective layer, a first dielectric layer, a second protective layer, a second dielectric layer, a third protective layer, and a The third dielectric layer is then etched to form a pattern of an upper trench of one of the dual damascene structures. Then, the third protective layer and the second dielectric layer are etched up to the surface of the second protective layer to form a pattern of a lower contact hole (v i a h ο 1 e) of one of the dual damascene structures. Subsequently, the third protective layer and the second protective layer not covered by the third dielectric layer and the second dielectric layer are removed, and then the third dielectric layer and the second protective layer are used as a hard mask. Removing the second dielectric layer and the first dielectric layer up to the surface of the first protective layer. Finally, the second protective layer and the first protective layer that are not covered by the second dielectric layer and the first dielectric layer are removed until the surface of the conductive layer is completed to complete the fabrication of the dual damascene structure. In the present invention, a photoresist layer is used to define a pattern of an upper trench and a lower contact hole of a dual damascene structure in a dielectric layer and a protective layer, respectively, and then the dielectric layer and the protective layer are used as a hard mask to A single-engraving process is performed to form the metal wire and the position of the contact plug at the same time. Therefore, there is no problem that the photoresist is left at the bottom of the contact hole in the conventional technology, so the efficiency and throughput of the process can be effectively increased. Detailed description of the invention

Page 8 508741 V. Description of the invention (5) Please refer to FIG. 6 to FIG. 12 'FIG. 6 to FIG. 13 are a first embodiment method for fabricating a dua 1 damascene structure on the surface of the semiconductor wafer 40 according to the present invention schematic diagram. The semiconductor wafer 40 includes a substrate (51 ^ 31 ^ 316) 42 and a conductive layer 44 formed of a copper wire and is disposed on the substrate 42. In the present invention, a first protective layer 46, a first dielectric layer 48, a second protective layer 50, a second dielectric layer 52, a third protective layer 54, and a third protective layer 54 are sequentially formed before the surface of the semiconductor wafer 40. A stack of three dielectric layers 56 and a first anti-reflection layer 58 cover the conductive layers 44. The first and second protective layers 46, 50 are composed of silicon nitride, si 1 icon ~ oxy-nitride, or si 1 icon carbon. The first dielectric layer 48 or the second dielectric layer 52 is made of a low dielectric constant (low-K) material, including FLARETM, SiLKTM, and arylene ether. polymer), parylene compounds, poly i mid e-based polymers, fluorinated polyimide, HSQ, fluorosilica glass (FSG), silicon dioxide, and silica glass ( nanopoorus siHca) or Teflon. The third dielectric layer 56 and the third protective layer 54 are composed of a compound and a silicon nitride, respectively.

Thick = ST-Hthography process, in the first anti-residue flag banner name M々 first resistance (Photoresist) layer 60, to define a double inlaid, one of the structure of the upper trench 61 pattern . Then, a first pattern of the first photoresist layer 60 is removed by Wei Chengyi to remove the first anti-reflection layer 58 and the third dielectric layer 56 not covered by the first photo layer 60, until the first

508741 V. Description of the invention (6) The surface of the protective layer 5 4 is shown in Figure VII. Subsequently, as shown in FIG. 8, the first photoresist layer 60 and the first anti-reflection layer 58 are removed, and a second anti-reflection layer 62 is formed on the surface of the semiconductor wafer 40, and then a second yellow light process is performed. A second photoresist layer 64 is formed on the surface of the second anti-reflection layer 62, and is used to define a pattern of via contact holes (via ho 1 e) 65 in one of the dual damascene structures. As shown in FIG. 9, a second etching process is performed to remove the second anti-reflection layer 62 and the third protective layer 54 that are not covered by the second photoresist layer 64 along the pattern of the second photoresist layer 64 until The surface of the second dielectric layer 52. As shown in FIG. 10, the second photoresist layer 64 and the second anti-reflection layer 62 are removed, and then the third dielectric layer 56 and the third protective layer 54 are used as a hard mask. A third # etch process is performed to remove the second dielectric layer 52 not covered by the third dielectric layer 56 and the third protective layer 54 to the surface of the second protective layer 50. As shown in FIG. 11, a fourth etching process is performed to remove the third protective layer 54 and the second protective layer 50 that are not covered by the third dielectric layer 56 and the second dielectric layer 52. As shown in FIG. 12, a fifth # engraving process is performed, and the third dielectric layer 56 and the second protective layer 50 are used as a hard mask to remove the third dielectric layer 56 and the second dielectric layer. The second dielectric layer 52 and the first dielectric layer 48 covered by the protective layer 50 reach the surface of the first protective layer 46. Finally, as shown in FIG. 13, a sixth etching process is performed to remove the second protective layer 50 and the first protective layer 46 which are not covered by the second dielectric layer 52 and the first dielectric layer 48. Until guide

Page 10 508741

V. Description of the invention (Ό The surface of the electric layer 44 is completed to produce the dual mosaic structure. In the first embodiment of the present invention, the third dielectric layer 54 may also be composed of a gas oxide stone and a carbide stone respectively. Since Shi Xi itself has good reflectivity, the first and second anti-reflection layers 58 and 62 are additionally formed during the manufacturing process, which can save the cost. ^

Please refer to FIGS. 14 to 20. FIGS. 14 to 20 are schematic diagrams of a method for fabricating a dual damascene structure on a surface of a semiconductor wafer 80 according to the present invention. As shown in FIG. 14, the semiconductor wafer 800 has a substrate 82 and a conductive layer 84 formed of a copper wire and is disposed on the substrate 82. The present invention forms a first protective layer in sequence before the surface of the semiconductor wafer 80. 86. A dielectric layer 88, a second protective layer 90, and an anti-reflective layer 2 are covered on the conductive layer 84. The first protective layer 8 6 is composed of silicon nitride or silicon carbide (S i C), the anti-reflection layer 92 is composed of silicon oxynitride (si 1 icon-oxy-nitride), and the second protective layer is composed of The 90 series consists of silicon carbide (SiC). The dielectric layer 88 is composed of a low dielectric constant (low-κ) material, including FLARETM, SiLKTM, poly (arylene ether) polymer, parylene compounds,

Polyimide-based polymer, fluorinated polyimide, HSQ, fluorosilica glass (FSG), stone dioxide, porous stone glass (nan0p0r0us silica), or iron fluoride Made of dragons 0

Page 11 508741 V. Description of the invention (8) Next, a first yellow light process is performed to form a first photoresist layer 9 4 on the surface of the anti-reflection layer 92 to define an upper trench 9 5 of the dual damascene structure. picture of. Then, as shown in FIG. 15, a first etching process is performed, and the anti-reflection layer 92 not covered by the first photoresist layer 94 is removed along the pattern of the first photoresist layer 94 until the surface of the second protective layer 90 is removed. . Subsequently, the first photoresist layer 94 is removed, and a second yellow light process is performed to form a second photoresist layer 96 on the surface of the semiconductor wafer 80 to define the pattern of the lower contact hole 97 in one of the dual damascene structures. As shown in Figure 16. As shown in FIG. 17, a second etching process is then performed to remove the second protective layer 90 that is not covered by the second photoresist layer 96, along the pattern of the second photoresist layer 96, until the dielectric layer 8 8 surface. After that, the second photoresist layer 96 is removed, and an anti-reflection layer 92 and a second protective layer 90 are used as a hard mask to perform a third etching process to remove the non-anti-reflective layer 92 and the second protective layer. The dielectric layer 88 covered by 90 reaches a predetermined depth, as shown in FIG. Subsequently, as shown in FIG. 19, a fourth etching process is performed to remove the second protective layer 90 that is not covered by the anti-reflection layer 92. As shown in FIG. 20, the anti-reflection layer 92 is then used as a hard mask to perform a fifth etching process to remove the dielectric layer 8 8 that is not covered by the anti-reflection layer 92, until The surface of the first protective layer 86 is formed with the dual damascene structure. Finally, a sixth etching process is performed to remove the first protective layer 86 which is not covered by the dielectric layer 88 until it reaches the surface of the conductive layer 84.

Page 12 508741 V. Description of the invention (9) Since the second embodiment of the present invention directly forms an anti-reflection layer instead of the third dielectric layer in the first embodiment, and a trench or a dielectric layer is formed in the dielectric layer When the hole is contacted, a protective layer is not formed as the #etch stop layer, so the dual mosaic structure will have a bowl-shaped or stepped profile (prof i le), so that during the subsequent process of filling the metal layer, Get a better filling effect, and avoid the shortcomings of the poor coverage of the bottom and side walls of the plug hole due to the poor coverage of the metal atoms, which can easily diffuse into the silicon substrate through the barrier layer to improve the process quality. Rate and electrical performance of semiconductor products. Compared with the conventional method of forming a dual damascene structure on the surface of a semiconductor wafer, the present invention uses a photoresist layer to define the pattern of the upper trench and the lower contact hole of the dual damascene structure before the dielectric layer and the protective layer, respectively. That is, a pair of hard masks (dua 1 hardmask) is formed first, and then the dielectric layer and the protective layer are used as hard masks to perform a engraving process, and then the metal wires and the positions of the contact plugs are formed at the same time. Therefore, there is no problem that the photoresist remains on the bottom of the contact hole in the conventional technology, so that the subsequent metal layer can be completely filled into the contact hole to form a good dual damascene structure. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 13 508741 Simple description of the diagrams Simple explanation of the diagrams Figures 1 to 5 are schematic diagrams of the conventional method for forming a dual mosaic structure. FIG. 6 to FIG. 13 are schematic diagrams of a method for fabricating a double-embedded structure on the surface of a semiconductor wafer according to the first embodiment of the present invention. 14 to 20 are schematic diagrams of a method for fabricating a dual damascene structure on the surface of a semiconductor wafer according to a second embodiment of the present invention. Symbol description

10 Semiconductor wafer 12 Base 14 Conductive layer 16 Protective layer 18- First dielectric layer 20 Second dielectric layer 22 First photoresist layer 24 Open π 26 Hole 28 First—Photoresist layer 29 Residual photoresistor 30 Parallel light 32 Photomask 34 Linear opening V 36 Double damascene structure 40 Semiconductor wafer 42 Substrate 44 Conductive layer 46 First protective layer 48 First dielectric layer 50 Second protective layer 52 First _ dielectric layer 54 Third protective layer 56 First dielectric Layer 58 First anti-reflective layer 60 First photoresist layer 61 Upper trench 62 First anti-reflective layer page 14 508741 Short description of drawings 64 Second photoresist layer 65 Lower contact hole 80 Semiconductor wafer 82 Substrate 84 Conductive layer 86 First protective layer 88 Dielectric layer 90 Second protective layer 92 Anti-reflection layer 94 First photoresist layer 95 Upper trench 96 Second photoresist layer 97 Lower contact hole

Page 15

Claims (1)

508741 VI. Scope of patent application 1. A method for fabricating a dual damascene structure on a semiconductor wafer surface. The semiconductor wafer includes a substrate and a conductive layer provided on the substrate. The method includes the following: Steps: on the dielectric layer and the third dielectric layer; perform one of the mosaic structures on the surface of the first radiation layer, perform the first removal to remove the three dielectric layers, and directly remove the first to the semiconductor to perform a first A pattern of a second photoresist layer (hole) is sequentially formed on the surface of the semiconductor wafer to form a first protective layer, a first two protective layer, a second dielectric layer, a third protective layer, and a first An anti-reflection layer covering a conductive lithography process on the first anti-reflection-first photoresist layer to define the pattern of the double upper trench; an etch ) Process, the first anti-reflection layer and the first to the third protective layer surfaces covered by the first photo-resist layer along the pattern of the first photo-resist layer; a photo-resist layer and the first anti-reflection layer; A second anti-reflection layer is formed on the surface of the body wafer; in the second yellow light process, a lower contact hole is formed on the surface of the second anti-reflection layer to define one of the dual mosaic structures (via is not the second light layer until the first Two etching processes, removing the second anti-reflection layer covered by the resist layer and the third protective second dielectric layer surface along the pattern of the second photoresist layer; removing the second photoresist layer and the second anti-reflection layer Performing a third etching process using the third dielectric layer and the third protection layer; Page 16 508741 VI. The patent application scope of the protective layer is used as a hard mask to remove the second dielectric layer not covered by the third dielectric layer and the third protective layer until the first dielectric layer is covered. Two protective layer surfaces; performing a fourth etching process to remove the third protective layer and the second protective layer not covered by the third dielectric layer and the second dielectric layer; performing a fifth #etching process Using the third dielectric layer and the second protective layer as a hard mask to remove the second dielectric layer and the first dielectric layer that are not covered by the third dielectric layer and the second protective layer Up to the surface of the first protective layer; and performing a sixth etching process to remove the second protective layer and the first protective layer that are not covered by the second dielectric layer and the first dielectric layer, until the The surface of the conductive layer completes the fabrication of the dual damascene structure. 2. The method of claim 1 in which the conductive layer is a copper wire. 3. The method according to item 1 of the patent application, wherein each of the protective layers is composed of silicon nitride, silicon-oxy-nitride, or silicon carbon Make up. 4. The method of claim 1, wherein the first dielectric layer or the second dielectric layer is composed of a low-k material. Page 17 508741 VI. Application for Patent Scope 5 · The method according to item 4 of the Patent Scope, where the low dielectric constant material includes FLARETM, SiLKTM, poly (arylene ether) polymer, parylene compounds, polyimide (po 1 yimi de) -based polymers, fluorinated polyimide, HSQ, fluorosilica glass (FSG), silica dioxide, porous silica glass (nanoporous silica) ) Or Teflon. The third protective layer is composed of a nitride nitride layer. The method of claim 1 of claim 1, wherein the third dielectric layer is composed of a silicon oxide compound. I · i, tf—Semiconductor wafers. The half-body wafer includes a substrate. The method includes the following steps: Dielectric 1, a second protective layer, an anti-reflection layer, and a cover are formed on the surface of the semiconductor wafer and covered. A first-yellow light process is performed, and the photoresist layer is subjected to a first etching process to fix the dual damascene junction. The first photoresist layer covers the surface; the first to photoresist layer is removed; -A second yellow light process, a method of fabricating a double damascene structure and a conductive layer disposed on the substrate to sequentially form a first protective layer, a second dielectric layer, and a third protective layer conductive layer; A pattern of a first upper trench is formed on the surface of the anti-reflection layer; the anti-reflection layer is removed along the pattern of the first photoresist layer until the third protection & the semiconductor wafer surface is formed 508741 VI. Patent application scope Two photoresist layers to define the pattern of one of the lower contact holes of the dual damascene structure; a second etching process is performed to remove the second photoresist along the pattern of the second photoresist layer Layer covering the third protective layer to the surface of the second dielectric layer; removing the second photoresist layer; performing a third etching process, using the anti-reflection layer and the third protective layer as a hard mask, Removing the second dielectric layer not covered by the anti-reflection layer and the third protective layer until the surface of the second protective layer; performing a fourth etching process to remove the non-reflective layer and the second dielectric The third protective layer and the second protective layer covered by the electric layer; performing a fifth etching process, using the anti-reflection layer and the second protective layer as a hard cover to remove the anti-reflection layer and the first protective layer; The second dielectric layer and the first dielectric layer covered by two protective layers up to the surface of the first protective layer; and a sixth etching process is performed to remove the non-second dielectric layer and the first dielectric layer Covered by electrical layers A first protective layer and the second protective layer until the conductive surface layer, to complete the production of the dual damascene structure. 8. The method according to item 7 of the patent application, wherein the conductive layer is a copper wire. 9. The method according to item 7 of the patent application, wherein each of the protective layers is composed of nitride carbon or silicon carbon (Si C). Page 19 508741 Sixth, the scope of patent application is 10. The method of item 7 of the patent scope, wherein the anti-reflection layer is composed of silicon-oxy-nitride, and the third protection layer is made of silicon carbide. (S i C). ° 1 1 · The method according to item 7 of the scope of patent application, wherein the first dielectric layer $ and the second dielectric layer are made of a low dielectric constant (low-K) material. 1 2 · The method according to item 11 of the scope of patent application, wherein the low dielectric constant material includes FLARETM, SiLKTM, poly (arylene ether) polymer, parylene compounds, and polystyrene Amine (ρ ο 1 yimide) based polymer, fluorinated polyimide, HSQ, fluorspar glass (FSG), spar dioxide, porous spar glass (nanoporous silica) or Teflon. 1 3. —A method for making a double damascene structure on the surface of a semiconductor wafer. The semiconductor wafer includes a substrate and a conductive layer provided on the substrate. The method includes the following steps: sequentially forming a semiconductor wafer surface A first protective layer, a dielectric layer, a second protective layer, and an anti-reflection layer, and covering the conductive layer; performing a first yellow light process to form a first photoresist on the surface of the anti-reflection layer Layer to define a pattern of an upper trench of the dual damascene structure; performing a first etching process to remove the anti-reflection layer not covered by the first photoresist layer along a pattern of the first photoresist layer, Up to the second protective layer 508741 VI. Patent application surface; remove the first photoresist layer; perform a second yellow light process to form on the surface of the semiconductor wafer; a second photoresist layer to define one of the lower contact holes of the dual damascene structure A pattern; performing a second etching process, removing the second protective layer not covered by the second photoresist layer along the pattern of the second photoresist layer, up to the surface of the dielectric layer; removing the second photoresist layer Performing a third etching process, using the anti-reflection layer and the second protective layer as a hard mask to remove the dielectric layer not covered by the anti-reflection layer and the second protective layer up to a predetermined depth; A fourth etching process is performed to remove the second protective layer not covered by the antireflection layer; a fifth etching process is performed to use the antireflection layer as a hard cover to remove the area not covered by the antireflection layer. A portion of the dielectric layer covered up to the surface of the first protective layer and forming the dual damascene structure; and a sixth etching process is performed to remove the first protective layer not covered by the dielectric layer until Surface of the conductive layer. 14. The method according to item 13 of the scope of patent application, wherein the conductive layer is a copper wire. 15. The method according to item 13 of the scope of patent application, wherein each of the protective layers is composed of silicon nitride or silicon carbide (S i C). Page 508 741 6. Scope of applying for patent 16. The method according to item 13 of the scope of applying for patent, wherein the anti-reflection layer is composed of ilicon-oxy-nitride), and the fifth evening (S i C) is composed. ^ 4 Nitrogen layer silicon oxide (s_______ is composed of carbonite (S i C). 17. The method according to item 13 of the patent application, wherein the dielectric layer is composed of a low dielectric constant (1 0w- K). The method according to item 17 of the scope of patent application, wherein the low dielectric constant material includes FLARE I Si LKI poly (arylene ether) polymer. , Paryiene compounds, polyimide-based polymers, fluorinated polyimide, HSQ, gas-silica glass (FSG), silica dioxide, porous silica (nanoporous silica) Or Teflon. Page 22