TW508651B - Deep sumicron MOS device fabrication method - Google Patents

Abstract

A method for fabricating metal-oxide semiconductor (MOS) devices. It includes the steps of forming a plurality of active regions in a first dielectric layer on a silicon substrate, followed by conformably deposited a second and third dielectric layers on the silicon substrate. The third dielectric layer is anisotropically and selectively etched to form a plurality of sidewall spacers. These sidewall spacers are used as a mask to form a plurality of through holes in the base portion of the second dielectric layer. The through holes are filled with a filler dielectric layer, which is then etched back to form a plurality of dielectric columns. After the removal of the first and second layers, the dielectric columns serve as a hard mask to form a plurality of conductive gates. This process allows the conductive gates to be fabricated which have a critical dimension finer than that allowed by the underlying photolithographic technique.

Description

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 508651 C7 D7

This creation is a deep sub-micron MOS device and its manufacturing method. You Caiyou said that using the limits of the current optical development process technology to extend it to the deep-person-breaking dimension, the MOS device can be used. The gate pattern size has become more precise. In the semiconductor industry, manufacturers of semiconductor devices are under pressure because the design of electrical circuits in integrated circuits is getting smaller and smaller, which is followed by upgrading processes and their equipment. In order to use the existing process technology for the transistor in the manufacturing process, the transistor achieves a sub-micron majesty in the manufacturing process. As a result, the yield of the transistor will become difficult to control. … The focus of improving conventional optical development technology is to focus on the use of shorter wavelengths, sources, improved photoresistors, phase-shift masks, and so on. These technologies have their own independent and individual advantages; however, it is important to explore other optical development equipment that is still in use today, and conductor manufacturers do not have to bear the cost and interruption of new equipment. Current production issues. The main object of the present invention is to develop an improved method for manufacturing deep submicron MOS devices. The main advantage is that the present invention is to develop an improved process method. This method is to use the limit value of the current optical development process technology to extend it to the dimension of deep sub-micron, so that the closed-pole pattern in the · s device can be made. The dimensions have become more precise. The method reveals that the present invention can enable a manufacturer of a semiconductor device to delay the upgrading of the process equipment and eliminate one or more intermediate manufacturing processes in the process equipment upgrade requirement. If this-comes again, you can reduce the capital and operating costs of buying equipment. The following is a preferred embodiment to explain the process of the current invention, its system

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This paper size applies to China National Standard (CNS) A4 (210 X 297 Public Love 508651

V. Creation Instructions (>-) The summary of the printing process of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is summarized as follows: (1) The majority of the __active area is formed on μ 11, and the insulation area is separated from each other (2) sequentially forming a pad dielectric layer, a conductive layer, and a first dielectric layer; (3) using optical development_the first-dielectric layer to make the majority correspond to the first The two active regions are exposed; the second and third dielectric layers are fully deposited on the wafer, and the etching rate of the second dielectric layer is different from that of the first and second dielectric layers, and -And the total thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer; (5) the third dielectric layer is selectively etched to form a plurality of pairs of sidewall spaeers, and then the sidewall (sidewan ... Forming a majority of perforations in the second dielectric layer as a photomask; (6) depositing a filling dielectric layer and filling the above-mentioned perforations formed in the second dielectric layer, and then back-etching the filling dielectric layer until the sidewall spacer ) To the bottom; (7) selectively etch and remove the first and second dielectric layers to make the pad dielectric Until the layer is not covered by the filled dielectric layer; (8) using the remaining filled dielectric layer system as an etching mask, so that the conductive layer is transformed to form most conductive gates; and, (9) the filled dielectric layer and the pad are removed Layer dielectric layer, and then use the conductive gate as a mask to perform source and drain implantation in the first active area. As mentioned above, the main advantage of the present invention is to extend the limits of the conventional optical development process and use This method can produce more precise than usual -------- ^ --------- (Please read the precautions on the back before filling this page)

V. Creation instructions (today) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. f. A number of additional dielectric layers are sequentially and comprehensively deposited on each of the comprehensively deposited dielectric layers. The cross-sections of the dielectric layers are mostly hat-shaped knots. The convex part is the first 4 layers, and the initial part is presented. The side walls of each comprehensively deposited dielectric layer can fine the gap between two adjacent dielectric protrusions. The necessary conditions for this month The total dielectric layer of all m is equal to the degree, and must not exceed the thickness of the _th dielectric layer. In addition, the necessary condition is that after the removal, the comprehensively deposited dielectric layer at the outermost layer is different from the retained one. Dielectric rate of the dielectric layer. Multiple steps are performed on the fully deposited dielectric layer, which can make the base of the adjacent dielectric layer closer to each other, so that the fabricated semiconductor device can provide a more familiar optical development process. The limit value is more excellent in precision size. Taking the outer layer of each of the deposited dielectric layers can be selectively and anisotropically engraved to form a pair of side walls (the side wall is located at the base of the second comprehensively deposited dielectric layer), and then jUsing the δHai sidewall as a photomask to leave the remaining comprehensive deposition below the sidewall Electrical layer to form a perforation. Finally, a filling dielectric layer that is different from the etch rate of the fully deposited dielectric layer is deposited and fills the gap between the perforation and the two fully deposited dielectric layers. The sidewall is used as a photomask. Reverting the filled dielectric layer makes the base of the comprehensively deposited dielectric layer into most short vertical lines (below the bottom of each side wall). The selective deposition is removed to remove the comprehensively deposited dielectric layer and the first dielectric layer. After the electrical layer and the pad dielectric layer, the width of each short vertical line is smaller than the active area defined by the conventional optical development process. &Quot; Then use the short dielectric layer as a mask for the MOS device to be formed later --- ----- tr --------- > ^ · (Please read the notes on the back before filling this page)

C7 D7 V. Creative Instructions (0) Steps to understand the aforementioned creative purpose and details In order to make your reviewing committee more structured, please attach a diagram to explain the following (a) Schematic part: The first picture: It is one of the invention The part of the circular argon is not intended, and it reveals that: the active area is the first active area with most well areas, where the active area is separated by an insulating area. ° σ Second image layer and a first dielectric sound · %%, where the first dielectric layer is active at the first ^. The optical development process is used to form most of the cross-sectional schematic diagrams of most of the second active opening part of the manufacturing process, which reveals the third figure of the dielectric structure of the conductive layer on the circle, the conductive layer, and the dielectric layer. A schematic cross-sectional view showing that the Z dielectric layer is fully deposited on the wafer, wherein each of the fully deposited dielectric layers is composed of a hat-shaped structure, and each hat-shaped structure includes a shoulder on the fully-deposited dielectric layer Part of the convex part (formed by the first dielectric layer). The fourth figure is a schematic cross-sectional view of part of the invention, which reveals that the most surface layer of the deposited dielectric layer selectively and anisotropically forms opposite sidewalls, and the etching is located below the sidewalls. A comprehensive dielectric layer is deposited to form the majority of perforations. The fifth figure j is a schematic cross-sectional view of another part of the process of the present invention, which reveals that-a filled dielectric layer is deposited on the crystalline Li_LiU and the hole is filled. This paper is in good time Guan Jia Xian (CNS) A4 specification (2ΐ〇Τ ^ Γ ^

C7 Fifth, creative description K Sixth figure Seventh figure Eighth figure Ninth figure Another part of the process is anisotropically etched to remove the filled dielectric layer 1: Another aspect of the present invention is to remove the comprehensiveness After the deposition reveals the plutonium dielectric layer, the number of the first dielectric layer and the number of ^ u below; | Electrical rows are formed on the filled dielectric y and the underlying dielectric layer. = Another part; a schematic cross-sectional view of Cheng, which reveals electricity :: using dielectric vertical lines as a photomask to form most dielectric / conducting systems, another section of the present invention, a cross-sectional schematic of the process, which reveals the removal of dielectric After the layered part, most of the conductive vertical lines form a majority of the consumer property cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to print MOS devices. (2) Part number: (1) Silicon substrate (3) Active area (5) Conductive layer (7) First dielectric layer (9) Third dielectric layer (1 2) Filled dielectric layer (21) Source / drain region (2 3), second active region (2 5), bottom (2) insulation region (4) gate dielectric layer (6), pad dielectric layer (8), second dielectric layer (11) Fill the dielectric layer (2 0), the dielectric sidewall (2 2), the perforation (2 4), the convex portion (2 6), the sidewall ----------- order--line ^ ιρ · (Please read the phonetic on the back? Matters before filling out this page) Dimensions ㈣ Guan Shi (cns) A4 (2iq7 297 mm) 508651 C7

V. Creative Instructions (") Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (29) Dielectric / conductive layer (30) M0S device The present invention does not reveal a new method, which enables deep sub-micron Xia (metal emulsion, Semiconductor) devices have more precise manufacturing dimensions than conventional optical development processes. This method can allow semiconductor manufacturers to postpone the need to upgrade process equipment under the constant upgrade requirements for manufacturing equipment in the present invention, or to upgrade requirements in general The use of one or more multi-intermediate procedures is omitted in the process to save operating costs and investment costs. As mentioned above, one of the main advantages of the present invention is to extend the limit value of the optical development technology when applied to the production of MOS devices. This makes the combustion device better than the Mos device made by the original optical development process technology. The main requirements of the present invention are summarized as follows: (1) To achieve the purpose of the present invention, firstly, a multi-active layer is formed in the __dielectric layer. Area (ie, the through hole is located in the first dielectric layer system above a conductive layer), these active areas are shaped "with the device (such as the gate) and perpendicular to the host of the MOS device in the silicon substrate" Moving region; ^ (2) a number of additional dielectric layers (or "comprehensively deposited dielectric layers,") are sequentially and comprehensively deposited on the wafer surface, and each comprehensively deposited dielectric layer has a plurality of cap shapes The structure includes a convex portion (formed by the first dielectric layer) located on both shoulders of the comprehensively deposited dielectric layer; and a sidewall layer of each of the comprehensively deposited dielectric layers may be formed between The gap between the insulating layers of the two dielectric layers is gradually reduced. Another requirement of the present invention is that the thickness of the comprehensively deposited dielectric layer must not exceed the thickness of the first dielectric layer. (3) Another requirement of the present invention is the comprehensiveness at the end and the outermost layer ------- ^ -------- (Please read the precautions on the back before filling this page) Specifications (210 x; public director) 508651 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs C7 D7 5. Creation instructions (j) The etch rate of the deposited dielectric layer must be different from the rest of the underlying dielectric layer. The outermost fully deposited dielectric layer is selectively and anisotropically etched to form a pair of side walls, which are located on the shoulders of the second fully deposited dielectric layer. Then, using the side wall as a photomask to etch the residuals under the side wall = a full-scale deposition of the dielectric layer can form most of the perforations. (4) Finally, a filled dielectric layer has an etch rate different from those of the comprehensively deposited dielectric layers (except the outermost dielectric layer), which deposits and fills the perforations and is between the fully deposited dielectric layers. In the gap between the electrical layers, the side wall is used as a mask to etch back the filled dielectric layer, and the base layer of the comprehensively deposited dielectric layer is transformed into a plurality of short vertical rows (which is lower than the bottom of each side wall). After shortly etching the fully-deposited dielectric layer, the first dielectric layer, and the pad dielectric layer, each short vertical row (converted from the remaining portion of the fully-deposited dielectric layer and the pad oxide layer) The width is smaller than the optical development process dimension of the active region used in the first dielectric layer. That is, these short dielectric layers are then used as a mask for the MOS device to be formed later, that is, the manufacturing process of the present invention can use a conventional optical development process to manufacture a MOS device. A -preferred embodiment is used to describe the current invention process, and the following steps are summarized: (a) forming a plurality of first active regions on a wafer, and two adjacent first active regions are blocked by an insulating region; (b ) Sequentially forming a pad dielectric layer, a conductive layer, and a first dielectric layer on the wafer; (c) using optical development to etch the above-mentioned first dielectric layer to form most paper-scale paper towels Standard (CNS) A4 specification (χ ------------ ------------------- order --------- line up- (Please read the note on the back? Matters before filling out this page) 5. Creation Instructions (p) The first in the first dielectric layer vertically above the first active area. (d) Comprehensiveness on the wafer The second and eighth regions of ground deposition; where the rate of the third dielectric layer is different from that of the first and second dielectric layers, and the total thickness of the third dielectric layer is smaller than that of the first dielectric layer. ： 'And the second such comprehensively deposited dielectric sound is ancient and gone, and the U layer has a plurality of hat-shaped structures including a convex portion above the base portion; the sub-structure is anisotropic and Selectively etch the On the side of the convex portion of the second dielectric layer; its :: number: using side walls as light [form multiple (g) at the base of the second dielectric layer to deposit a filled dielectric layer between the perforations; Dielectric layer up to the bottom of the sidewall; ⑴ Selectively etch and remove the first and second dielectric layers, and the pad dielectric layer will not be covered by the filled dielectric layer; 7 ^ u) Use the remaining filled dielectric layer As the _ mask layer is transformed into most conductive gates; ⑴ Remove the filled dielectric layer and the pad dielectric layer, and then use the conductive implant area; #Active area pre-formed-the source and drain electrodes will be as follows Refer to several examples to describe its more features. The purpose of the description of the present invention is described in the preferred embodiment of the present invention, that is, the purpose to be achieved by the present invention is fully and correctly expressed. Figures 9 to 9 show the main process of the device that is not in the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs.

= The picture reveals—the wafer forming the simplified device (B rtr first active area (3) (ie, in the Xixi base manhole area) = the first active area (3) is separated by each insulating layer (2). The two figures show that the gate dielectric layer (4), the pad dielectric layer, a life-saving electrical layer (b), a ": 6" and a first-dielectric layer (7) are formed on the wafer; "预 发展 制 程 # is engraved on the first-dielectric layer to form a gold layer above the active area (3). Chu Jielei ... Diyi active area (23); the question eight: the layer is a silicon oxide Layer, the conductive layer is a polycrystalline silicon layer, the " electrical layer is a stone oxide layer, and the first dielectric layer is a nitride stone layer. Refer to the third figure to reveal a second dielectric The electrical layer (8) and the third dielectric layer are fully deposited on the wafer. Each comprehensively deposited dielectric has several hat-shaped structures, and the hat-shaped structure includes a base located at the base!) Department (24). The shape of the convex portion (24) is formed by a high-dielectric layer, wherein the material of the second layer is more suitable for the rat fossil layer and the material of the third dielectric layer is TEOSaetraethylorthosilicate). ...... Please refer to the fourth figure, which shows a pair of side walls (2 6). The outermost comprehensive dielectric layer is deposited with selectivity and anisotropy. A comprehensive dielectric layer is deposited to form a plurality of perforations. As shown in the fifth figure, a filled dielectric layer (1 1) is described above as perforations. The material of the filled dielectric layer (1): suitable for the third dielectric layer (9) TE0S. -------------------— Order --------- Line (Please read the note on the back? Matters before filling out this page) This paper size applies China National Standard (CNS) A4 Regulations; X 297 Public Love · _ 1 Printed by JVQODi C7 D7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Creation Instructions (/ 〇) Refer to the sixth figure to show that the filled dielectric layer is The product 1 can be selected as follows: a short vertical line (27) (this is defined by the shoulder (28) of the comprehensively deposited "electrical layer, will be short vertical lines (2 degrees below the bottom of the side wall, due to the filling medium) The electrical layer and the sidewall layer are made of the same material ^ 'so the sidewall layer is also removed in the remaining process. Please refer to the seventh figure does not reveal that removing the comprehensively deposited dielectric layer: the dielectric layer and the underlying dielectric layer ( The vertical rows (2 7) are vertical, and each dielectric vertical row (2 7) includes a filled dielectric layer portion (12) and a pad dielectric layer portion (6) below. The eighth figure shows that the conductive layer (5) uses a dielectric vertical row (2 7) as a photomask to form a plurality of dielectric / conductive vertical rows (29) by etching. After the dielectric material is partially removed, That is, a dielectric sidewall is formed to form a drain / source region through ion implantation (2 1), and a plurality of conductive vertical rows form a plurality of MOS devices (30). The specific description issued is not intended to limit the scope of the patent application for this creation. Furthermore, the present invention does have the aforementioned advantages, and it is based on the existing semiconductor manufacturing method and has a significant effect improvement. Therefore, the present invention The design meets the requirements of the invention patent, and the application is filed according to the law.

This paper size Gu towel _ house standard (CNS) A4 specifications (2 ^ 297 mm)

Claims (1)

508651 508651 Year of A8 B8 C8 D8 < month / ¾ " Amendment / Li Zheng / # Jt Application Patent Scope No. 90111944 Patent Application Application Scope Amendment 1, a manufacturing method of deep sub-micron MOS device, which includes the following steps ( a) forming a plurality of first active regions on the wafer, separated by a plurality of insulating regions', and then forming a pallium dielectric layer, a conductive layer, and a first dielectric layer on the Shixi substrate; (b) Optical development is used to etch the first dielectric layer to form a plurality of second active regions perpendicular to each of the first active regions; (c) fully depositing a second and a third dielectric layer on a silicon substrate, of which the third The dielectric layer has an etch rate different from that of the first and second dielectric layers; (d) the third dielectric layer is selectively and anisotropically etched to form most sidewalls; (e) the sidewall is used as a photomask To form a plurality of perforations at the base of the second dielectric layer; (f) depositing a filled dielectric layer to fill the perforations, and then selectively engraving the filled dielectric layer to form a plurality of dielectric longitudinal lines; (g) selective etching to remove the first and second dielectrics Layer until the pad dielectric layer is not covered by the remaining filled dielectric layer; and (h) using the dielectric row as an etch mask to transform the conductive layer into most conductive gates. 2 · The method for manufacturing a deep sub-micron MOS device as described in item 1 of the scope of patent application, further comprising removing the filled dielectric layer and the pad dielectric layer at the conductive gate, and then using the conductive gate As a photomask, a source and a drain implanting region are formed in the first active region. ------------------------- 0 ^ ------ (Please read the notes on the back before writing this page) -έ 297 Mm) 丄 C8 ---—_____ ^ __ D8 6. Scope of patent application (please read the notes on the back before writing this page) ”1 3 Deep submicron M as described in item i of the scope of patent application. s Device manufacturing method, the total thickness of the second and third dielectric layers is the thickness of the electrical layer. $;, ^ 4. The deep submicron% device manufacturing method described in item (1) of the scope of patent application Among them, the comprehensively deposited dielectric layers are formed by most hat-shaped structures. Composition 'Each hat-shaped structure includes a convex portion located above the base. Remaining 4 5 · Deep sub-micron as described in item 4 of the scope of patent application The method for manufacturing a MOS device, wherein the sidewall is formed on the sidewall of the convex portion of the second dielectric layer and above the base of the second dielectric layer. 6 · The deep sub-micron as described in item 1 of the scope of patent application In the manufacturing method of the Mos device, the gate dielectric layer is a stone oxide layer, the conductive layer is a polycrystalline stone layer, the pad dielectric layer is a stone oxide layer, and the first: Electricity It is a fragmentation layer. 7, The method for manufacturing a deep sub-micron MOS device as described in item 1 of the patent application scope, wherein the second dielectric layer is a silicon nitride layer and the third dielectric layer. The electrical layer is a TE0S layer. 8 · The manufacturing method of the deep sub-micron MOS device described in item 7 of the scope of patent application, wherein the filled dielectric layer is a TE0s layer, and the etching rate is similar to that of the first layer. Three dielectric layers 9. A deep sub-micron MOS device, comprising: a wafer on which a first active region separated by a plurality of insulating regions is formed, a pad dielectric layer, a conductive layer, and a The first dielectric layer; most of the second active regions are perpendicular to the first active regions, respectively, and are obtained by etching the above-mentioned first dielectric layer by optical development; This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) 6. Scope of patent application-the second and third dielectric layers are sequentially formed on the wafer; the number side i 'is formed on the upper end surface of the second dielectric layer to selectively and directionally rhyme The third dielectric layer is obtained by engraving; a plurality of perforations are formed at the base of the second dielectric layer. Obtained as a photomask on the side wall of the second dielectric layer;-filling the dielectric layer formed in the perforations of the second dielectric layer; most of the dielectric rows are formed on the conductive layer to sequentially and selectively The ground layer is filled with the dielectric layer, the second and the first dielectric layers until the pad dielectric layer is not covered by the remaining filled dielectric layer; and most conductive gates are formed on the wafer. The dielectric vertical row serves as a lithographic mask, so that the conductive layer is transformed into the majority of conductive gates. 10. The deep-micron MOS device as described in item 9 of the patent application, each of the -active regions of the wafer further includes a The source electrode implantation area and the non-electrode implantation area are formed by removing the filling dielectric layer and the pad dielectric layer at the conductive gate, and using the conductive gate as a photomask. District planted. 1 1 _ The deep sub-micron device described in item 9 of the scope of the patent application, wherein the total thickness of the second and third dielectric layers is smaller than the thickness of the first dielectric layer. " 1 2 · The deep sub-micron device described in item g of the patent application scope, wherein the second and second dielectric layers include a plurality of cap structures, and each cap structure includes a protrusion above the base . 1 3 · The deep sub-micron MOS device as described in Item 12 of the scope of patent application, wherein the sidewall is formed on the sidewall of the convex portion of the second dielectric layer and the Chinese national standard (CNS) is applied at the paper size. A4 size (21,297 mm) Above the base of the second dielectric layer. 1 4 · The deep sub-micron MOS device as described in item 9 of the scope of the patent application, wherein the gate dielectric layer is a Shi Xi oxide layer, and the conductive layer is a complex layer: a silicon layer, and the pad layer The electrical layer is a silicon oxide layer, and the first dielectric layer is a nitrided layer. 15. The deep sub-micron hall device according to item 9 of the scope of the patent application ', the second dielectric layer is a silicon nitride layer and the third dielectric is a TEOS. 1, 16 · As described in the scope of the patent application, the first sub-micron MOS device described in item 1 b ^^^, the filled dielectric layer is a TEOS 屛, f > a layer, and its etching rate is similar The second dielectric layer. ------------------------ f! (Please read the notes on the back before filling in this page) 、 \ Two paper sizes are applicable to Chinese national standards (CNS) A4 size (210 X 297 mm)