TW507209B - Asynchronous FIFO controller - Google Patents

Abstract

Provided asynchronous FIFO controller includes a FIFO buffer for registering the exchange data operated among devices of different clock domain frequency, and two interface controllers for being operated to different clock domain frequencies for reading or writing the exchange data among devices out or into the FIFO buffer and using valid read-write status that the valid vector record device with respect to the FIFO buffer. The two interface controllers synchronously receive each valid vector to make the device effectively read and write the FIFO buffer.

Description

507209

V. Description of the Invention (l) [Technical Field of the Invention] The present invention relates to the technical field of a FIFO controller. Special explanation. The present invention relates to a method that operates in different clock frequency domains (Cloc Domain). A non-FIFO controller that can maintain the read and write integrity of FIFO buffer data. v [Background of the Invention and Prior Art] In the information age, data is stored, processed, and transmitted almost digitally. Bits such as speech, music, video, and images are all digitized and represent a series of bit information (Bit Infomation) in the form of 0 and 1. The computer system contains a plurality of integrated circuits (Int egra ted

Circuit), and each integrated circuit is composed of millions of transistors. These transistors can be turned off by the signal of "〇" or turned on by the signal of "丨" to complete Tasks planned by computer programs. In the operation of the integrated circuit, the "clock" (cloc) determines the speed of its arithmetic processing. With the advancement of semiconductor process technology, the performance of computer systems and processing speeds have also increased significantly. Similarly, peripheral devices that support computer systems such as hard disks, modems, printers, etc. have become faster. Even for transmission media used in computer networks such as coaxial cables and optical fibers, the transmission speed of data transmission Quickly improving. In fact, the entire environment is moving towards clock speed. In order to increase the clock speed, the situation is that many devices and transmission media operate at different clock speeds. For example, one electronic device may operate at a slower clock speed (such as 400 MHz), while another electronic device may operate at a faster clock speed (such as 1 GHz). In many applications,

01P0064.ptd Page 4 507209 V. Description of the invention (2) '--- These two electronic devices need to be connected to each other. Therefore, the interface connection between the two electronic devices will cause problems. This is due to incompatibility caused by the different clock speeds executed by each other, especially the speed of transmitting and receiving each other on the wheel data. Therefore, there must be some way to deal with the data exchange between devices with different clock speeds and transmission lines. One of the factors of the above problems is due to the many different industry standards and regulations (Protto). These standards and communication protocols usually specify a specific clock frequency domain. Furthermore, the clock frequency domain specified by one standard is usually incompatible with the clock frequency domain of another standard. In addition, the system upgrade (Upgrade) may also cause clock conflicts (connHcts). In addition, a multi-purpose computer system must be able to adapt to different clock processing so that it can connect devices operating in different clock frequency domains. In order to make the devices with different clock speeds compatible, upgradeable and adaptable, an interface controller should be used to handle the data exchange between these electronic devices. As shown in Figure 1, the method of transferring data with different clock speeds is shown in the conventional techniques. A FI F0 memory 3 is between the transmission interface of system 1 and system 2 'System 1 writes data 11 into fifo memory 3 at clock CLK1' and system 2 writes data 12 at clock CLK 2 Read the FIFO memory 3 ° In this conventional technique, the problem is that the phase difference (Phase Difference) between the two clocks CLK1 and ^^^ may cause the data 12 of the system 2 to be read incorrectly. Generally, the data is sampled at the leading edge of each clock. If CLK2 is ahead of CLK1 in phase, a phase difference will occur at some time points, and the phase difference will cause the data to be latched at different times.

01P0064.ptd Page 5 Fifth, the description of the invention (3) (Latch), resulting in data reading errors. On the other hand, the data t = in Aihua, so the data at time 11 may be different from that of another conventional art department at time t 2 using the valid vector (Valid Vector) for the bank of memory. State, and use the setting ', ΐ〇Γ) and clear vector ⑻ such as VeCt〇r) to indicate the validity of the other 2. Although this method can achieve simultaneous read / write performance. 1 When the number of lean material groups is large, configuring the vector setting and eliminating the amount of θ will cause additional costs for the controller. I also knocked down the FIFO :: Crying Wu: 明明 Patent No. 5, 95 1,6 35 disclosed-a kind of non-synchronization and read: control ;; device :: capacity for use, where :: Counts can be expressed in 9 bits in FiF0 memory. It is easy to cause misjudgment of data due to the read / write indicator of the master controller. Therefore, there is a competition phenomenon (-Effect), which can handle different ^: =; there are 3 reductions, cost and design complexity, and the read and write integrity of the medium ^ B's parent material to maintain F IF 〇 memory Physical progress. The ~ face controller 'will have industrial applicability and [inventory of the invention] The main purpose of the present invention is to set vectors and clear 6 f for one type only-FIFO buffer and not to deal with the two; :: t indicates the validity of the asynchronous FIF_ data exchange between the π domain of the present invention. , I provide an interface controller

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V. Description of the invention (4) Ring F IJ? The present invention provides a FIFO controller that can effectively read and write. Each bit as an interactive system provides a buffer for each F 1 F 0 buffer, which is implemented in the FIF0 control Skew of the Cross-interface. In order to avoid signal skew (Signal is connected to the embodiment, a non-synchronous FIFO controller, the second device operates separately; at first; on the input path, and f and the synchronous FI F0 controller include · 1 slowly planting one person a day in the pulse frequency domain 'the exchange of information between the aforementioned non-position; the first temporary storage of the first-and the second installment of the day to prosecute a strong young man, tied to theft, operating in the first The clock frequency D t is used to read and write the exchange data at the first clock speed, and use the effective vector to record the effective read / write status of the first device to the buffer in a circular FIF0 manner; and Two interface controllers, which operate in the second clock frequency domain, and control the second device to read and write the exchanged data at the second clock speed to the buffer, and use the second effective vector to record the second device = buffer in a cyclic fifo manner The effective read-write status of each interface controller, wherein each interface controller synchronously receives each other's effective vectors in the clock frequency domain of its own operation, thereby controlling the first and second effective read-write buffers. 9 " Synchronous FIFO controller and its many advantages and features will be from below Detailed description and the accompanying drawings further understanding obtained [FIG numeral described formula] I, 2 --~ system 3 - Memory II, 12 - ~ Profile

01P0064.ptd 507209 V. Description of the invention (5) 13 --- First effective vector 14 --- Second effective vector 15 --- First device 16-Second device 17 --- Data bus 10- -The first interface controller 20 --- The second interface controller 30-A buffer [Detailed description of the invention] First, please refer to FIG. 2 'which is a circuit block showing the asynchronous F IF control of the present invention and the simultaneous reading and writing of data. Illustration. In the first type of the present invention, the "asynchronous F IF 0 controller is electrically connected to the data bus 17 between the first device 15 and the device 16", so that the two devices can exchange funds between the first device 15 and the first device. The two devices 16 operate in different time and second clock frequency domains respectively. The non-synchronous FIFO control (Buffer) is electrically connected to the data exchange device 1 to exchange data between the devices 1 and 16. The device adopts the circular F 丨 F〇 frame 1 〇, which is operated in the first clock frequency domain, and the material control reads and writes the buffer at the first clock CLK1 speed = the volume 13 records the first load in a circular FIFO manner :: Write state; and the second interface controller 20 and control the second device 16 to obtain the data exchange domain device from a different device package row 17, in the present structure; the first system 30, juxtaposed 15 pairs of 'system The second quantity 14 can be used to implement the second loading of the embodiment, and the pulse frequency domain includes: a buffer 3 0 for temporarily storing the first and Ming preferred embodiments. An interface controller device 15 will be used. The third buffer 3 0 is used for the second clock CLK2. The cycle F IF0 exchanges a valid effective clock frequency and speed. Mode write buffer 30 and use the second valid direction

〇lP〇〇64.ptd page 8 507209 watts, description of the invention (6) Record the effective reading and writing state of the buffer 30 by the second device 16; among them, the first medium: Ξ ϋ Γ, 1. ? Further-step synchronously receives the second effective vector 14 from the second two + f20 at the speed of the first clock CU1, and controls the first-device 15 to be effective according to the comparison result of the first effective vector 13 ^ Ϊ to $ 14. "5." At first, in addition, the second interface controller 20 further received the first-clock pulse from the first interface controller 10: the amount of vector? Compared with the second effective vector " The main brother fj set aside 16 for effective reading and writing. For example, the second and second examinations in Figure 2 are schematic diagrams showing the invalid vectors 1 3, 1 and 4 in a circular F I F0 mode =, 'Effective reading and writing state of the data exchanged in the friend punch 30. Each == has a pointer pointer (Head p〇inter) and a tail pointer: 113, 14 :) 'The head pointer points to the effective vector 13, = Yingqiao 3 " written areas ·, The tail pointer refers to the next read area in buffer 30, corresponding to 113,14. : Each-position of the two 'effective vectors 13, 14 corresponds to the areas A, B, c, D, E, F 1 planned in the buffer state 30, respectively. A pointer and a tail pointer point to the same bit of the effective vector, then : There is no "effective," read or write action in the head buffer 30. ♦ When the L and j table are not pointing to the same position of the effective vector, then: 1 X, the index has performed an effective write action, so Interface controller :: The position of the effective vector in $ 冲 器 30, which will read the position of the tail indicator field, such as ^^ region C, after that, the tail indicator will be read next to the pointer 30. Take the position of the area, for example, to: When the slow controller wants to control the device to perform the paired sound of the sound "Jiao" on the buffer 30, it will introduce

01p〇〇64.Ptd Page 9 5. Invention means that / ____ The surface controller will enter the corresponding buffer 3 according to the head pointer. d: the position of the quantity, write the data and the pointer points to the embroidery 2 in the effective vector, for example: area Η, after that, the head position, for example: area A. Because the buffer V; 30 / a bit written to the area, when the head and tail indicators point to the right-cycle FIF0 group structure in sequence, they will point to the last position of the effective vector η! Again. A position. In the present invention, the non-synchronous FIF0 second interface controller 20 has the phase-first interface controller 10 and work content. These tasks include the circuit layout and perform the same at the same time. Synchronization ... Second: Surface 2: Control state η synchronously receives the second effective vector from the 2.4-plane, the second effective vector "2" at the speed of the-clock CU1, and the second interface control = the speed-received synchronous reception of the ~~ buffer from the-interface controller 10 Valid read and write actions: Content :: 5 ϋ is based on the time of the first effective vector 13 and the second effective vector ", F η that can be effectively written in the position of the two effective vectors pointed by the § master indicator is not currently combined. No device to buffer 30 in the second by the pointer indicator

•: f effect write operation; otherwise, it means that another interface controller I τ _ 30 has performed a valid write operation. Effectively read this 2 'When the tail pointer points to two effective vectors, there can be pointers to ^ ^' means that there is currently no device to perform a valid read of the "^^" field in the buffer 30 by the tail pointer. Action; on the contrary, it means that another interface control, Ling Chongyi 30 has performed an effective reading action.

° 1Ρ0064. Ptd Page 10 507209 V. Description of the invention (8) III. Effective reading of the device: When one interface controller performs the reading action, it will recognize that the other interface controller has corresponding to the tail indicator. After the effective writing operation is performed in the buffer 30 area, the interface controller will control the device to read the data in the area corresponding to the buffer 30 according to the tail pointer and set the effective vector at the same time. This position is effectively read, and the tail pointer is directed to the position of the next read area of the buffer 30 in its effective vector. Fourth, the device performs effective writing: When one interface controller performs a write operation, it will confirm that the other interface controller has performed a valid read on the buffer 30 area corresponding to the head pointer, and then according to the head pointer Point to the position of the effective vector itself. This interface controller will control the device to write data to the area corresponding to the buffer 30. At the same time, set the position to be effectively written and make the head pointer point to the buffer in the effective vector itself. 3 The position of the next written area. Among them, the position of the effective vector is a setting that is effectively read or written, and only needs to be expressed by one bit, and a value set to 1 or 0 indicates that the data in the area corresponding to the position 30 is valid. Write or read effectively, therefore, the embodiment of the present invention can avoid the race phenomenon from affecting FI ρ 〇 read and write performance. The controller can be set to 15 for the second type. Finally, please refer to FIG. 4, which is a block diagram showing a circuit for asynchronously reading and writing data in the synchronous F 丨 F0 controller of the present invention. FIG. 4 is an embodiment of the present invention, in which the asynchronous FIFO controller is electrically connected to the data bus 17 of the first to second devices 16 to make the first attack

0lP0064.ptd Page 11

507209 V. Description of the invention (9) Ring FIF 0 group architecture of the first device 15 and the second and second clock frequency domain, (Buffer), electric device one and 15, 16; frequency domain, and control the first impulse The device 30 reads the data and records the first device 15. The interface controller 20, the system 16 uses the second clock CLK2 vector and 14 cycles of the FIF square-in state; among them, the second speed receives the second effective vector 1 4 synchronously. And the second medium synchronously receives the comparison of the first effective vector 14; the device 16 operates the asynchronous FIFO and exchanges data between the data sinks; the first interface control device 15 stores the data and uses the first pair The buffering operation is performed at the second time of the speed writer 30, and the second controller is installed. As a result, the controller 20 enters the “parallel control formula” to record an interface that is effective to compare the control vector 13 with the result. The second device 16, which is used for different first clock frequency domain controllers, includes: a buffer 30 streamer 17 for temporarily storing the first data, and this set of buffers uses a cycler 10, Operating on the first clock to the first clock CLK1 The self-slowing effective vector 13 reads the state effectively in the circular FIFO side; and the second pulse frequency domain, and controls the second device 3 0 ′ and uses the second valid set 16 to effectively write the buffer 30 to 10 further to the first The clock CLK1 is effectively read according to the first effective vector 1 3 and the first device 15 for one step at the second clock CLK2 speed. The effective writing is performed according to the first effective vector 13 and the second two device 16 in detail. After a preferred embodiment of the present invention, those skilled in the art can clearly understand it, and can make various changes and modifications without departing from the scope and spirit of the patent application described below, and the present invention is not limited to the embodiments of the description. Implementation. [Effect of the invention] Asynchronous F I F 〇 controller implemented according to the preferred embodiment of the present invention,

01P0064.Ptd Page 12 507209 V. Description of the invention (ίο) Only the effective vector is needed to record the buffer) I (λ — 1 ηΗ " Λν * · Ρο / ^^ The interface letter is one ring, and the complexity is reduced to cost. The control group F IF 0 comprehensive operation in practice, complete value, review and give the number (cross-interface bit indicates that the indicator has a circular FIFO structure and other low-speed interface clock interface can be obtained by the simultaneous clock frequency domain As described above, the present invention has a practical and reliable system that is practically and practically lacking, and has been in line with the invention patent < (Interactive signal) For each buffer, only read and write operations are required to avoid the characteristics of the race phenomenon, so that the complex signal of the FIFO controller is also simplified. In the case of asynchronous performance, only a lot of excellent characteristics are needed in its architecture, and it solves the conventional problems and inconveniences, and proposes effective solutions to achieve novel and economically beneficial application requirements. For more favorable to the people's livelihood will be a real sense of ethics.

507209 Brief description of the diagrams Figure 1 is a block diagram of a conventional technique for processing data transmission between different clock speeds. Figure 2 is a circuit block diagram of the asynchronous F I F0 controller of the present invention that can simultaneously read and write interactive data. Figure 2 is a schematic diagram of the effective vector recording buffer in a cycle F I F 0 manner. Fig. 4 is a circuit block diagram of the second embodiment of the asynchronous F I F0 controller of the present invention.

01P0064.ptd Page 14

Claims (1)

507209 6. Scope of patent application 1. A FI F0 controller is electrically connected to the first device and the second device, and the first device and the second device operate in different first and second clock frequency domains respectively. The FI F0 controller includes: a buffer for temporarily storing the exchange data between the first and second devices; a first interface controller for controlling the first device and reading and writing the exchange data at the first clock speed Buffer, and the first effective vector is used to record the effective read / write status of the first device to the buffer in a circular FIF 0 manner; and a second interface controller is used to control the second device and exchange data with the second clock Read and write the buffer at a speed, and use a second effective vector to record the effective read and write status of the buffer to the buffer in a circular FIF 0 manner; wherein the first interface controller synchronously receives the first buffer at a first clock speed. Two effective vectors to control the effective read and write actions of the first device; and the second interface controller synchronously receives the first effective vector at a second clock speed, Effective to control the write operation of the second device. 2. A FIFO controller electrically connected to the first device and the second device, and the first device and the second device operate in different first and second clock frequency domains respectively. The FI F0 controller includes: A buffer for temporarily storing data exchanged between the first and second devices; a first interface controller for controlling the first device and transferring data to the first device; 01P0064.ptd Page 15 ^ / 209 ^ / 209 Six 'application for patent scope Daily guarding speed reads data from the aforementioned buffer, and uses the first amount to record the first device to the aforementioned buffer in a circular F IFO manner: effective to And a valid read second interface controller for controlling the second device and writing to the buffer at a speed, and using the second valid vector in a two-clock manner. The effective writing of the first device to the buffer has been recorded. F IF 〇 Wherein, the first interface controller captures the first clock with the first clock =: receives the second effective vector, and according to the first effective direction ^ = ^ Connect the comparison result of the effective vector to control the first device to perform = two second actions; 'Political reading and the aforementioned second interface controller synchronously connects to the lack of an effective vector at the second clock speed, and according to The comparison result between the first effective vector and the second directional f is used to control the second device to perform an effective write operation. Setting 3. The F IF0 controller described in item 1 or 2 of the scope of patent application, its φ &, Eqi /, τ Gangmei, each position of the consistent vector and the second effective vector corresponds to the area of the front punch. & Edge 4. The FIFO controller as described in item 1 of the scope of patent application, wherein the first effective vector has a pointer indicator to point to the writeable buffer area under the first device; and a tail Pointer to point to the buffer area that can be read by the second device next time. 5. The FIFO controller according to item 1 of the scope of the patent application, wherein the second effective vector has a head pointer to point to a buffer area that the second device can write to next time, and a tail pointer. To point to the buffer area that the second device can read next time. 0lP0064.ptd Page 16 6. Scope of Patent Application ___ 6: As described in the fourth item of the patent scope, the controller controller: when the interface controller controls the first device to perform the writing action, it should be fair: the air controller Will confirm the second interface controller header; the first-position of the effective vector described above, the first ticket set the position corresponding to the area of the buffer at the same time,-in the effective vector, the aforementioned '= indicator points to the aforementioned seventh , ^ ^ A position of the next written area in the buffered state. The first application: the FIFO controller described in item 5 of the patent scope, device / No .: the interface controller controls the second device to perform the reading action; The surface controller will confirm the aforementioned first interface control: Valid write was performed on the aforementioned buffer area corresponding to the first one, and its tail index is based on the bit of the tail index pointer pointing to the aforementioned second effective vector.]: 'The root surface controller controls the second device to read the second medium: the internal data, and at the same time set the aforementioned second effective direction; the area of the punch 8 .: ::, and the tail pointer points to the aforementioned second effective direction ^: Ϊ, it is beneficial to read the next area Location. Here is a buffer: a F⑽ control method for controlling the reading of the fine buffers that operate on the square and the second device ;: The knife provides the device pair η that the first device and the second device have an interface controller to receive the connection ς = controller, the number; 1 field read and write letter uses an effective vector in each interface controller to cycle _ square 0iF0064.ptd Page 17 DU / ZUy VI. Patent application scope _ type record effective reading action; the amount of information between the aforementioned interface controllers to judge the foregoing; effective control to the aforementioned interface to cry according to the previous ^ Fetch; and Qtil, the buffer performs a valid read operation. •: = The FI F0 control method described in item 8 of the Tianli range, wherein the aforementioned effective orientation is the position of the FIFO buffer with one finger. The position of 乂 入 入 入 ^^, and a tail indicator to Pointing the device _ times may = read the position of the aforementioned FIFO buffer. The following a I 0. As described in the application of the May 9th patent scope ^ 丨 F 〇 control method, which: ϋ t 仃 write action, its interface controller refers to the position of @ ί vector according to the head indicator, Control the first device to write data to this area and describe the area of the FI F0 buffer. At the same time, set the position to be entered, and make the head pointer point to its effective vector. One of the aforementioned ^^ F0 buffers is written. Into the area. II · As mentioned in item 9 of the scope of patent application?丨 F 〇 Control method, when the first device performs a reading operation, its interface controller controls the second device to read the data in the area corresponding to the aforementioned FI F0 buffer according to the position of the tail pointer pointing to its effective vector. At the same time, set this position to be read effectively and make the tail pointer point to the position of the next read area of the aforementioned F 丨 F0 buffer in its effective vector. 1 2 · — + ρ IF0 control method for controlling the first device to pass the second device to the second device, and the first device and the second device operate in different first and second clock frequency domains. The control The method contains: 507209 6. The scope of the patent application provides a circular FIFO buffer between the first device and the second device; the read interface controller and the write interface controller are provided for the first device and the second device, respectively, for separately Receive the read signal from the first device and the write signal from the second device; use the first effective vector in the aforementioned read interface controller to record the valid read action of the first device in a circular FIFO manner; control in the aforementioned write interface The processor uses the second effective vector to record the effective writing action of the second device in a circular FI F0 manner; the read interface controller synchronously receives the second effective vector in the first clock frequency domain, and judges the FIF 0 buffer according to the foregoing. Whether the reader can be effectively read to control the first device to perform an effective read operation on the FIF 0 buffer; and the write interface controller synchronously receives the first valid vector in the second clock frequency domain, and judges accordingly Whether the FIF 0 buffer can be effectively written to control the second device to perform an effective write operation on the FIF 0 buffer. 1 3. The FI F0 control method as described in Item 12 of the scope of patent application, wherein the first and second effective vectors each use a pointer to point to the first and second devices. The next time F IF can be written 0 buffer position; and a tail pointer to point to the position where the first and second devices can read the F IF 0 buffer next time. 1 4. The F I F0 control method as described in Item 13 of the scope of patent application, wherein when the first device performs a reading action, its reading interface controller 01P0064.ptd Page 19 507209 6. The patent application scope marker points to the position of its effective vector, controls the first device to read data to the position corresponding to the area of the FI F0 buffer mentioned above, and sets the position to be effectively read, and The head pointer is pointed to the position of the next read area of the aforementioned F IF 0 buffer in its effective vector. 15. The FI F0 control method as described in Item 13 of the scope of patent application, wherein when the second device performs a write operation, its write interface controller controls the second device according to the position of the tail pointer pointing to its effective vector. The device writes the data in the area corresponding to the aforementioned FI F0 buffer, and sets the position to be effectively written, and makes the tail pointer point to the position of the next written area of the aforementioned F IF 0 buffer in its effective vector. 01P0064.ptd Page 20