TW506112B - Electrostatic discharge protection circuit with latch-up prevention function - Google Patents

Abstract

The electrostatic discharge (ESD) protection circuit, which is electrically connected with the interface terminal and the device region, at least contains the first bipolar junction transistor, the second bipolar junction transistor, the first metal oxide semiconductor (MOS) transistor and the second MOS transistor. These two bipolar junction transistors are used to form the conventional silicon controlled rectifier (SCR). The first MOS transistor is located between the interface terminal and the second bipolar junction transistor. The second MOS transistor connects the base of the second bipolar junction transistor to a relatively low point of the voltage. In addition, both gates of these two MOS transistors are electrically connected to a voltage reference point that has a voltage equal to the operation voltage of the device region. When the device region is not turned on, the SCR is latched to provide ESD protection function. When the device region is turned on, the second MOS transistor is conducted to make part of the current that flows toward the second MOS transistor flow toward a relatively low point of the voltage such that the positive feedback between both bipolar junction transistors is decreased and the latch-up of the SCR is eliminated.

Description

506112 V. Description of the invention α) 5 -1 Field of the invention: The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit having a function of preventing a blocking phenomenon. 5-2 Background of the Invention: In order to protect the integrated circuit from being damaged by high current or voltage, for example, to prevent the integrated circuit from being damaged by large current caused by noise or improper insulation, as shown in the first figure A, Existing integrated circuits include at least interface terminals 1 1 (such as pads, PADs) for output and input signals and the component area 1 2 where most electronic circuits are located, and are generally electrically coupled to electrostatic discharge protection circuits 1 3 to The interface end 1 1 and the component area 12. Here, the electrostatic discharge protection circuit 13 is normally open, but when a large current or high voltage external signal (usually noise) appears at the interface terminal 1, if the voltage of the external signal exceeds the electrostatic discharge protection circuit 13 When the triggering voltage is triggered, the electrostatic discharge protection circuit 13 will be activated by this external signal and turned into a path, so as to guide the additional signal to a relatively low voltage of 14 so that the component area 12 will not be excessively large. Harm from foreign signals. Of course, in order to avoid that the external signal has affected the component area 12 before the electrostatic discharge protection circuit _ 1 3 comes into play, there is usually a buffer between the interface end 11 and the component area 12 to delay or isolate the large signal entry 15.

506112 V. Description of the invention (2) P passer integrated circuit is thin, light and short. The current-saving high-efficiency current collector :: 2 :: = Electrical discharge prevention RECTmER ’SCR) has become widely used. … The flow generator is usually formed by the deletion structure, such as: two: no, which is directly located in the N-type well region 193-the P-type doped region 17 is electrically coupled to the interface terminal 域 1 £ domain 16 严The second swollen doped region in the first 9/6 is directly located at the relatively low voltage of the noisy substrate and is switched to a relatively low voltage i. Double-carrier connection = electricity = two-second-carriers ... body T1 is replaced by the -P type for γ-; the zone 193 is formed with the P substrate 196, and the second double-carrier table is ^ 'Well-shaped well area' 3, P-type substrate, second N-type load / hybrid connection "connected to the seven transistor T2, there are N resistors_Qingbei represent P-type substrate with type region = resistance. ≫, Obviously, caused by the well region 1 3, when the voltage applied to the first type doped region 16 by the interface end 11 exceeds the N-type well region 丨, the region 17 and the first>, a large number of electron hole pairs will be generated, When the electrical breakdown voltage (...), High-potential electrons flow into the doped region 16/2 (resistance in the hard-well region). The P-type doped region i 9 flows into a low potential. When (1 (P-type substrate Resistance) and will produce a -voltage drop, and when this voltage drop is large ΐ When passing R2 / R1, the dynamic bi-carrier is connected to the transistor T1 / T2. As long as it is cold, it will further start the current from the crystal T 1 to the ρ-type substrate 丄 9 6 and a bi-carrier is connected to the transistor. T2, because the second double-carrier connection is called two = the double-carrier connection is called body T 2 can also start the first

506112 V. Description of the invention (3) " ~~ 一 ~ " ---- = Carrier connection transistor τ 丨 'Therefore, these two double carrier connection transistors will form a positive feedback loop (P0STIVITE FEEDBACK L 〇〇p), so that the boundary is Ξ 3 ΐ and a little more voltage can make the Shi Xi controlled rectifier-directly maintained at all ί ί. A vtri ^ table makes two bi-carriers connected to the start-up voltage of the transistor while Itrig is the start-up voltage corresponding to the start-up voltage, and Vh represents the minimum voltage that keeps the silicon controlled rectifier on. Machine, because the generation of electric dust determines that the electrostatic discharge protection circuit will separate the following: the incoming signal is separated from the component area 12 :: 电 ， 相 # (or greater than the working voltage; ^ Qianwei) to make any work External signals with high voltage (or around Zhao ^) will not enter the change of the queen to prevent the static electricity protection; and dagger: as shown in the second a picture Part of it will not change: or between the region 18 and the a-type doped region 17 and between the second N-type doped region and the P-type substrate ^ 2 1 so that the auxiliary N-type doped does not form an auxiliary N-type doped F 彳 9 ridges, or as shown in Figure 2B Figure 14 Gates 2 2 in N-type wells ^ Electrically coupled to a relatively low voltage pip connected to the diode voltage The voltage is higher than those of the two doped doped regions 23 instead of the auxiliary doped 疋 region. As shown in the figure C, the auxiliary P-type non-electricity 14 is used as the gate interface terminal 11 connected to the relatively low point 24 of the electric dust. The gate 24 is not electrically, and the sub-form is electrically coupled to

506112 V. Description of the invention (4) 2 2 'By assisting P-type doped regions 2 3 _ total F 1 Q h P sun soil ^ Lei Kuang Kang & k A as a dagger 4 Xing Yan Kai 1 1 93 The voltage of the low silicon-controlled rectifier is lower than the trigger voltage of the low silicon controlled rectifier. The static electricity of the circuit will affect the operation of the flow device. When the power is lost, it will obviously provide a closed discharge, but once the signal is phase-to-ground, as long as the interface At two double-load voltages greater than Vh, use silicon rectifiers to keep them conductive, that is, use latch-up. If the voltage of the integrated circuit's electrical protection circuit changes and the integrated circuit is operated again, such as If the voltage is higher than Vh, a serious start will occur, and its operation signal will be adjusted to the low point, which will cause the integrated circuit to malfunction due to the relatively low point. (The static circuit of the electrostatic bleeder connected to the transistor has been There will be no serious fruit area and the consequence is that only the body of the electrostatic discharge protection operation signal is turned on to protect the electrical discharge protection from being operated. The heavy bad interface should be controlled by silicon. ^ Protection circuit drains (flow of course ' Immediate solution It is changed * The structure of the protection circuit (Configuratic) = using the f rectifier electrostatic discharge signal voltage or increasing its initiation voltage / the user makes Vh significantly larger than the operation affecting VBD, Itrig, and then | changes. Due to the structural change will also The performance of the discharge protection circuit. Therefore, Jing Lei II's use of Shixi Rectifier's static electricity is an urgent problem to be solved. The latching of the electric discharge protection circuit is still 5-3 Purpose and summary of the invention:

506112 V. Description of the invention (5) One of the main objects of the present invention includes at least proposing an electrostatic discharge protection circuit using a silicon rectifier which can reduce or even eliminate the blocking phenomenon. The equivalent circuit diagram of the present invention includes at least a first bi-connected transistor, a second bi-connected transistor, a first metal-oxide semiconductor and a second metal-oxide semiconductor. Two of the two diodes are connected to the transistor to form a conventional silicon controlled rectifier. The first metal-oxide semiconductor is located at the interface end and is connected to the base of the second diode (that is, the collector of the first diode). ), And the second metal-oxide-semiconductor is connected to the second bipolar connection transistor base to a relatively low voltage, and the gates of the two metal-oxide-semiconductor are electrically coupled to work with the component area Voltage reference point with equal voltage. When the component area is not activated, as in the conventional technology, the silicon controlled rectifier provides electrostatic discharge protection and may be blocked; when the component area is activated, the second metal-oxide-semiconductor is turned on by an operating voltage greater than zero, so that Part of the current flowing to the second bipolar metal-oxide-semiconductor transistor is reflowed to a relatively low voltage, which reduces the positive feedback between the bipolar-connected transistor and eliminates the blocking of the silicon controlled rectifier. 5-4 Detailed description of the invention: According to the first C diagram and related discussions, this case indicates that the main reason for the lock-up of the conventional technology is that only the mechanism for activating the positive feedback loop between the two dipoles to connect the transistors is not cut off. Mechanism of positive feedback loop. Therefore, when the signal appears on the interface (whether it is a normal operating signal or noise)

506112 V. Description of the invention (6) After the positive feedback loop is activated to maintain the positive feedback loop, the circuit is blocked, causing the current to flow into the component area when the integrated circuit is not operating; and the circuit must not affect the operation. When the circuit is not in operation, make sure; find: hold-a small voltage can be used to prevent the circuit from being electrostatically charged. However, in general, Dangdang integrated circuits: operation: should be prevented as much as possible from the signal in the component area ^ ^, electrostatic discharge protection, blocking phenomenon-transmission. Therefore, the latch-up phenomenon can be eliminated; and when the integrated circuit is said to have strong electrostatic discharge protection function, according to the previous discussion, the operation of the integrated circuit has been blocked and locked ^ = person, the following concepts are developed to solve the problem caused by the integrated circuit During operation, the problems affected by the circuit are as follows: zero, and when the integrated circuit is not powered, the operating voltage of the component area is greater than the voltage is close to zero. The base of the crystal is a low point when the breast semi-electric crystal is connected to the liver tumor carrier-connected working electrode when the working voltage is greater than zero, and this gold-oxygen semi-transistor is apparent, even when the product fails to work. Devotion is closed when less than zero. The integrated circuit circuit is operated :: The blocking phenomenon occurs when it is not in operation, and the voltage from 1 to the body is relatively low ^, at least part of the current will be the base of the metal-oxygen half-connected crystal, so it is not The conduction to the di-carriers is preferred in the present invention to be eliminated. Without protection circuit. Such as the first = garden can realize the above concept V. Description of the invention (7) Connected to the interface terminal 31 and the component area (there is a carrier connected to the transistor ^, and the second one) and includes a gold Oxygen semi-transistor 35, first-connected crystal 34, first low point 37, voltage reference point 38, Brother Dianbao relative 391 and second resistor 392. Brother Dianbao relatively low 39, first resistance first pair, The first double carrier is coupled to the interface through the second resistive carrier to connect the base of the electric body 3 3 to the pole of the metal oxide semiconductor semi-transistor 35 of the first double carrier crystal 3 4, and the first element region 3 2 The crystal 3 6 has no 'second metal oxygen point 3 9' and the first quasi-point 38. And the first metal oxygen half is the emitter of the first double carrier connection transistor 33 and the transistor is connected to the transistor. = Weighed to the 31 end of the interface ί = Electrically connected to the transistor 3 3 I 3 9 2 through the first resistor 391, a pair of carriers, and electrically connected to the first electricity: 33 collectors are through the animal husbandry Wang Le * The pressure is relatively low at 37. The collector of the 耦 -cavity crystal 34 is electrically coupled [尚 锸 # 乐 一双 着 ， 第-雔 韵; the double-carrier connection transistor = —and the carrier-connection transistor 34 base The electrical plum is connected to the collector of the transistor 33, and the second biconductor connection 2 is also electrically connected to the first electrical a relatively low. The source of the point body 35 is electrically connected to the i-terminal 31,金 —Gold ^ = The electrode g is electrically connected to the gate of the first bipolar connection transistor 33 and the gate of the oxygen-collecting semi-transistor 35, which is electrically coupled to the voltage reference point 38 having the same operating voltage. The second metal-oxygen half / electrical f is electrically coupled to the second bipolar connection transistor 3 4 and the source of the base semi-transistor 36 is electrically coupled to the second voltage which is relatively low by one $ oxy-half transistor 3 The gate of 6 is electrically coupled to the voltage base and the drain of the second metal-oxide semiconductor transistor 36 is often electrically coupled to the drain of transistor 35. Incidentally, although the third figure The connection transistor 33 is a PNP and the second bipolar connection transistor is °

Page 10 506112 V. Description of the invention (8) The body 34 is NPN, while the first metal-oxide semiconductor 35 is a P-type metal oxide semiconductor and the second metal-oxide semiconductor 36 is an N-type metal oxide semiconductor Crystal, but the present invention can also be changed to the first amphibian-connected transistor 33 is an NPN and the second amphibian-connected transistor 34 is a PNP, and the first gold-oxygen semi-transistor 35 is an N-type gold-oxygen half Transistor, and the second metal-oxide semiconductor transistor 36 is a P-type metal-oxide semiconductor transistor. In addition, the first metal-oxide semiconductor transistor 35 can reduce the initiation voltage, and the second metal-oxide semiconductor transistor 36 can draw the current to a relatively low second voltage 39, so that the positive feedback loop cannot be maintained. The effect of this is controlled by the voltage of the reference point 38. Another preferred embodiment of the present invention is an electrostatic discharge protection circuit with a prevention and blocking function, which is also a possible specific configuration of the previous preferred embodiment. As shown in FIG. 4A, the preferred embodiment is electrically coupled to the interface terminal 415 and the device region (not shown in FIG. 4A) at the same time, and includes at least: a well region 40 and a first doped region. 4 1. Second doped region 4 2. Gate 4 3. Third doped region 4 4. Fourth doped region 4 5. Fifth doped region 4 6. Gold-oxygen semitransistor 4 7. First The voltage is relatively low at 4 8, the second voltage is relatively low at 4 9 and the voltage reference is 4 9 5. The well area 40 is located in the substrate 405, and the well area 40 has a first conductivity and the substrate 405 has a second conductivity. Here, the first conductivity is opposite to the second conductivity. When the conductivity is P-type conductivity, the second conductivity is N-type conductivity, and when the first conductivity is N-type conductivity, the second conductivity is P-type conductivity. Of course, in order to increase the reaction rate, the first conductivity is usually N-type.

Page 11-… .. One by one .. — V. Description of the invention (9) __ while the second conductivity is Du '40 and is electrically coupled to the boundary. The first doped region 41 is located in the well region and is electrically conductive and has a high impurity concentration. The first doped region 41 has the second region 42 and the doped concentration is partially located in the well region 40. The second doped second doped region 4 2 is not directly in contact with the first doped region. The second doped region 42 also has the first and second conductive regions 41 in direct contact, and the second doped region is doped. The density is large. The gate electrode 43 is usually doped at a higher voltage than the well 40 reference point 4 95, and the voltage is beautiful; the well 40 is electrically coupled to the same voltage, and the gate 43 is also at the voltage of point 495. And the working voltage of the component area. The third doped region 4 f, the hetero region 41, and the second doped region 42 415. The third doped region 40 is not invited to the puppet region 40 and is electrically coupled to the interface end. The second doped region 42 is located at, The first doped region 41 is in direct contact and the first doped region 44 has both sides of the first conductivity = a doped region 41, and the third doped region has a large doping concentration. The fourth doping machine and its doping concentration is generally lower than the coupling of the well region 40 to the first voltage.] The 4 doping mechanism is located in the substrate 405 and the electrical heterogeneous region 42 is in direct contact and the fish 8 'fourth. The doped region 45 is not on both sides of the second doped region 42. The fourth doped region 41 is located at the second doped concentration, which is generally higher than the doped substrate 45 or 45 with the first conductivity and Its doping is located in the substrate 405 and is electrically coupled to each other. The fifth doped region 46 is directly doped region 46 is not in contact with the fourth doped voltage to a relatively low point 4 8, and the fifth region 42 is located in the fourth doped region :) 45 is in pure contact with the second doped region ( It has the second conductivity and its two doped sides, and the fifth doped region 46 is large. The doping concentration of the gold-oxygen semi-transistor substrate 40 5 is the largest of the gold-oxygen semi-transistor 47. First The doping area 42 is electrically coupled, and is relatively lightly connected to the second low voltage point 49,

Page 12 ----- 5. Description of the invention (I0)

The metal oxide semi-electric transistor 4 7 M and the metal oxide semi-electric 0 0 I # 47 / and the electrical light connection to the voltage reference point 4 95, and the voltage is relatively low 48 and 23 and the drain has a-conductive Sex. No.-Electricity to low point, this real miscellaneous is # "[relatively low point 4 9 can be the same electricity> 1 phase details. 1" does not limit these two voltages to relatively low point of 48/49

Obviously, the _IAth parasitic double-carrier region, the second hybrid region 4, the well region 40, and the substrate 405 form a hybrid region 45 to form another "crystal, and the well region 40, the substrate 405, and the fourth doped region 40 At the same time, it is a cone-shaped parasitic and carrier-connected transistor. Because a parasitic dual-phase +, 40-type carrier is connected to the base of the transistor and the latter one: the collector of the crystal 'and the substrate 405 At the same time, the front transistor collector and the last-parasitic dipole are connected to the first electron, and the current appearing at the interface terminal 415 is passed to the second doped region 48. However, due to the source of the gold-oxygen semi-transistor 47 The polarity is coupled to the well :: 0, 21, or “Goldoxy” is generated through the second doped region 42. Point 49 549 Part of the current will be lacking. The crystal ^ 40, and the metal oxyhydroxide transistor 47 is turned on to the second voltage relative to the point 4 9 without the electric power to the base and the base. The base of the carrier-connected transistor is filled with two parasitic bi-carrier-connected transistors. Because of the snow, the blood can maintain a positive feedback loop, thereby eliminating latch-up = electricity-continuous omission. A sub-function is formed and the well region are set 4 ° ligated Λ source / base and the other - said base member said parasitic bipolar source / collector, and is predominantly adjacent to the well region 4〇 first

Page 13 " " -......... V. Explanation of the Invention (11) Bottom 2 Miscellaneous Area 42, ^^ Substrate 4 05 participated in the reaction. Miscellaneous region 45 and the ^ case: additional well region 4 = the embodiment can also be modified: Zunfen 3 is a region such as a domain, Zou Fen 3 5. The fifth doped region is next to well region 40 and contains the fourth beta map ^ ^ 4 984f ^. ^. 4〇t11-; the degree of indifference in each area. It has the second conductivity and its second song is doped with the additional well area%. The additional well area 498 is connected to the transistor with the fourth carrier, and the plant is connected to the transistor. The impurity region 45 forms another situation as shown in the figure C. The well + M is further modified to this embodiment as the bottom # 405 美 = 廿 1 well area 4 98 completely contains the well area 40, this It was formed by Weng, and η Tuben was not doped with any parasitic double-carrier connection transistor #. Therefore, the substrate 405 may have the first conductivity or a neutral substrate. ”太太 上The descriptions are only the preferred embodiments of the present invention, and are not intended to limit the scope of the patent application for the invention; all other equivalent changes or modifications made without departing from the disclosure of the present invention shall be included in the following In the scope of patent application.

Page 506112 Brief description of the diagrams Figures A to C are the location diagrams of the ESD protection circuit, the basic structure and equivalent circuit diagram of the ESD protection circuit using silicon controlled rectifiers; the second A to the second Figure C is a schematic cross-sectional view of several conventional electrostatic discharge protection circuits using silicon controlled rectifiers in the conventional technology; the third figure is an equivalent circuit diagram of a preferred embodiment of the present invention; and the fourth A to fourth Figure C is a schematic diagram of three possible φ cross sections of another preferred embodiment of the present invention. Symbols of the main parts: 11 Interface end 12 Element area 13 ESD protection circuit 14 Relatively low voltage 15 Buffer area 16 First N-type doping region 17 First P-type doped region 18 Second N-type doped region 19 Second P-type doped region 193 N-type well region 196 P-type substrate

Page 15 506112 Brief description of the diagram 21 Auxiliary N-type doped region 22 Gate 2 3 Auxiliary P-type doped region 2 4 Gate 31 Interface terminal 33 First bi-carrier transistor 34 Second bi-carrier transistor Crystal 35 The first metal-oxide semiconductor transistor 36 The second metal-oxide semiconductor transistor 3 7 The first voltage is relatively low 38 The voltage reference point 3 9 The second voltage is relatively low 391 The first resistance 3 9 2 The second resistance 40 Well area · 4 0 5 substrate 41 first doped region 4 1 5 interface end 42 second doped region 4 3 gate 44 third doped region 45 fourth doped region 46 fifth doped region 4 7 gold and oxygen half Transistor

Page 16 506112

Page 17

Claims (1)

506112 VI. Scope of patent application 1. An electrostatic discharge protection circuit with prevention and blocking function, the electrostatic discharge protection circuit is electrically coupled to an interface end and a component area, and the electrostatic discharge protection circuit includes at least: a well area, The well region is located in a substrate, the well region has a first conductivity and the substrate has a second conductivity; a first doped region, the first doped region is located in the well region and Electrically coupled to the interface end, the first doped region has the second conductivity and a second doped region, the second doped region is partially located in the well region and partially located directly on the bottom In the material, the second doped region is not in direct contact with the first Φ-doped region, and the second doped region has the second conductivity; a gate electrode is located on the well region, and the gate electrode A pole is also located between the first doped region and the second doped region; a third doped region 'domain, the third doped region is located in the well region and is electrically coupled to the interface end, The third doped region is not in direct contact with the first doped region and And the second doped region is located on both sides of the first doped region, the third doped region has the first conductivity; a fourth doped region, the fourth doped region is directly located on the bottom Material and does not directly contact the second doped region, the fourth doped region and the first doped region are located on both sides of the second doped region, and the fourth doped hetero region is electrically coupled Connected to a first low voltage point, the fourth doped region has the first conductivity; a fifth doped region, the fifth doped region is directly in the substrate and is not doped with the fourth doped region; The impurity region is in direct contact with the fifth doped region and Page 18 506112 VI. Patent application scope The second doped region is located on both sides of the fourth doped region, and the fifth doped region is electrically coupled to the relatively low point of the first voltage, and the fifth The doped region has the second conductivity; a voltage reference point, the voltage of the voltage reference point is equal to the operating voltage of one of the element regions; and a gold-oxygen semi-transistor, the wave of the gold-milk semi-transistor is extremely cool The second miscellaneous region is electrically coupled, the source of the metal-oxide-semiconductor is electrically coupled to a relatively low second voltage point, and the gate of the metal-oxide-semiconductor is electrically coupled to the At the voltage reference point, both the source and the drain of the metal-oxide semiconductor have the first conductivity. 2. If the electrostatic discharge protection circuit of the first patent application scope, the first conductivity is opposite to the second conductivity. 3. As for the electrostatic discharge protection circuit of the first patent application scope, the first conductivity is P-type conductivity and the second conductivity is N-type conductivity. 4. As for the electrostatic discharge protection circuit of the first patent application scope, the first conductivity is N-type conductivity and the second conductivity is P-type conductivity. 5. For the electrostatic discharge protection circuit of the first patent application scope, the doping concentration of the first doped region, the second doped region, and the third doped region is greater than the doped concentration of the well region. Page 19 506112 6. Scope of patent application 6 · If the electrostatic discharge protection circuit of the first patent application scope, the doping concentration of the fourth doped region and the fifth doped region is greater than the doping concentration of the substrate. 7. If the electrostatic discharge protection circuit of the first patent application scope, it may further include an additional well region, which is located beside the well region and includes the fourth doped region, the fifth doped region and the A portion of the second doping region 5 located in the well region has the second conductivity and the doping concentration is less than that of the doped regions. 8. If the electrostatic discharge protection circuit under the scope of patent application No. 7 is applied, the well area can still be completely located in the additional well area. 9. If the electrostatic discharge protection circuit of the patent application item No. 8 is used, when the well area is completely located in the attached well area, the substrate may have the first conductivity. 10. If the electrostatic discharge protection circuit of item 8 of the patent application scope, when the well area is completely located in the additional well area, the substrate is a neutral undoped substrate. 11. If the electrostatic discharge protection circuit of the first scope of the patent application, the first doped region, the well area, and the substrate form a parasitic double carrier connection transistor 1 2. As the first scope of the patent application, Electrostatic discharge protection circuit, the well area, Page 20 Scope of patent application ____ Substrate and No. Γ potential Μ The fourth doped region forms a parasitic double-carrier connection transistor. 1 3 · If you declare that the electrostatic discharge protection circuit of the main area, the miscellaneous area / Xizhiliganwei item 7, this-transistor. The X region and the additional well region can form a parasitic bicarrier connection. The additional V 'region has a scope of 7 electrostatic discharge protection circuits, the well region, and the transistor. w The fourth doped region may form an electrostatic discharge protection circuit of the first range of the parasitic double-carrier connection voltage at a relatively low point of interest. The first electric voltage (. ",,,, and the second voltage The relatively low point is the same low voltage point 1 6 · — an electrostatic discharge protection circuit with a right discharge lockout function. The electrostatic discharge protection is electrically defeated = electrically coupled to an interface end and a component area. The electrostatic package mainly includes: · _ ^ ^ w of the emitter system, i ϊ Ϊ: Connected to the base of the 11 H double carrier connected to the transistor through a = 5 Hai interface end, the first Bipolar-connected transistor carrier-connected: two ::: and electrically connected to the world, and the -dual-th voltage phase is electrically connected to the-set through a second resistor: connect The transistor 'stomach second bipolar connection transistor' is electrically coupled to the base of the first bipolar connection transistor. Page 21 506112 VI. Scope of patent application One of the bases of the second bi-connected transistor is electrically coupled to the collector of the first bi-connected transistor, and the second bi-connected transistor is electrically connected. The emitter is electrically coupled to the relatively low point of the first voltage; a first metal-oxide-semiconductor, and the source of the first metal-oxide-semiconductor is electrically coupled to the interface, and the first The drain of a metal oxide semiconductor is electrically coupled to the base of the second bipolar transistor, and the gate of the first metal oxide semiconductor is electrically coupled to a voltage reference. Point, the voltage at the voltage reference point is equal to the operating voltage of one of the element regions; and a second metal-oxide semiconductor transistor, the second metal-oxide semiconductor transistor, and the second pair are electrically coupled to the second pair. The carrier is connected to the base of the transistor, the source of the second metal-oxide half-Φ transistor is electrically connected to a relatively low second voltage, and the gate of the second metal-oxygen half-transistor is electrically coupled. To this voltage reference point. 1 7. If the electrostatic discharge protection circuit according to item 16 of the patent application scope, the first metal oxide semiconductor is a P-type metal oxide semiconductor and the second metal oxide semiconductor is an N-type metal oxide semiconductor Crystal. 1 8. According to the electrostatic discharge protection circuit of item 16 of the patent application scope, the first metal-oxide semiconductor is an N-type metal oxide semiconductor and the second metal-oxide semiconductor is a P-type metal oxide semiconductor . ⑩ 19. If the electrostatic discharge protection circuit according to item 16 of the patent application scope, the drain of the second metal-oxide semiconductor transistor is also electrically coupled to the electrode of the first metal-oxide semiconductor transistor. Page 22 506112 VI. Patent application scope 20. For example, the electrostatic discharge protection circuit of item 16 of the patent application scope further includes a first between the interface end and the base of the first bipolar connection transistor. resistance. 2 1. The electrostatic discharge protection circuit according to item 16 of the scope of patent application, further comprising a second resistor between the base of the second bipolar connection transistor and the relatively low point of the first voltage. Page 23