TW506051B - Method for forming gate dielectric material layer in silicon nitride ROM - Google Patents

Abstract

The present invention relates to a method for increasing the coupling ratio of a gate dielectric material and increasing the reliability of a silicon nitride ROM-type flash memory device by forming a zirconium oxide layer with a high dielectric constant on a substrate. The invented method at least comprises: providing a substrate; using a reactive magnetically-controlled sputtering method to form a zirconium oxide layer on the substrate; forming a silicon nitride layer on the zirconium oxide layer; forming a silicon oxide layer on the top layer, thereby forming an ONO (oxide-nitride-oxide) layer. The high coupling ratio using zirconium oxide as a gate dielectric material can reduce the control gate voltage while better controlling the on/off capability of a gate and the time-dependent dielectric breakdown properties of the gate.

Description

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5-1 Field of the Invention: The present invention relates to a method for forming a gate dielectric layer in a read-only memory cell using zirconia instead of traditional silicon oxide, and particularly to a method for increasing the coupling of the gate dielectric layer. Rate method.疋 5-2 Background of the Invention: According to the first figure, it illustrates a typical conventional technique of silicon nitride, recalling the unit cell. This unit cell includes a substrate, a silicon oxide-nitride oxide silicon oxide (ONO) structure. In the structure, a silicon layer 122 is on two silicon oxide layers 12. A polycrystalline silicon layer 150 is formed between silicon oxide and silicon nitride-oxidized silicon by a low-pressure chemical vapor deposition (LpcvD, Low Carbon Vapor DepOsiti) method. Then, the polycrystalline silicon layer 50 and the silicon oxide-nitrogen as / second-silicon oxide layer are sequentially etched in a wide etching step to form a gate. Then, the side walls of the gates form the partition walls 126 and 128. Furthermore, a source electrode 101 and a drain electrode 02 are implanted in the substrate ιOO. h a is in Programmable Memory (EPROM). The memory structure includes a gate ^ X and a drain electrode 102. At the bottom of the gate is a silicon oxide layer 120. The thickness of the silicon oxide layer 120 is thin enough to allow Fowler-Nordheim tunneling (could, nneHng, abbreviated as FN tunneling) to occur. The silicon oxide layer 1 2 0 w and the silicon oxide layer 1 2 0 can be regarded as a tunnel 506051.

Oxide layer (tuning oxide layer). In the write mode, the question pole is grounded and the high voltage is connected to the pole 102. When erasing the program, the high voltage is connected to the gate, and the drain 102 is grounded. According to the hot electron injection (HEI, hot electrc) n injectiQn), when the bottommost silicon oxide layer 120 is thin, some hot electrons will penetrate the bottom silicon oxide layer 120, and the electrons are concentrated in the nitride. In the silicon layer 122. In the conventional art, the region of the charge electrode 102 received by the silicon nitride layer 122 is. The traditional method for forming a gate dielectric layer is to form it on the substrate U by a thermal oxidation method. The dielectric constant of silicon oxide 12 is 38 to 39 mol per cubic meter, and the temperature of the thermal oxidation method is high. In addition, the coupling rate of the gate dielectric layer is 2 ^ 'For the gate dielectric layer, if a high voltage is introduced to the gate / drain to transform the cell more than a hundred times, the tunnel It is easy for the oxide oxide to collapse, and the leakage current will increase, and the reliability of the tunnel oxide layer 12 will decrease. 3 Purpose and summary of the invention: According to the dielectric layer method of the present invention, it is provided to form a gate in a nitride read-only memory, wherein a hafnium oxide layer is used to replace the traditional tunnel oxide layer.

Page 5 Month: A correction i No. 8Q1 舛 Qq_ V. Description of the invention (3) The target county of the present invention, the temperature of sputter deposits is lower than the temperature of the formation of oxidation faults, and the thermal budget. The method of thermal emulsification of 冋, 冋, and 皿 makes it possible to reduce the gate dielectric layer of the present invention. 2. The substrate has a high coupling rate and low leakage. The purpose is to form on the substrate. The ancients formed a mouth layer. This hafnium oxide layer can reduce the oxygen content of the electric explosion and the number of electric charges. In order to show a lower secondary threshold voltage and a good gate 2 charge gain, another purpose of the present invention is to increase the c property of the gate dielectric layer. Body component reliability. The flash memory mainly annihilates the purpose of the flash: in one embodiment, the structure of the most ingenious blade of the present invention is read in silicon nitride, and the structure is extremely contained in a substrate ~ ^ A gate W electrical layer is formed. A gate oxide layer was formed on the substrate of the gate s 户 兮 #, and a servant layer formed a polycrystalline silicon sound at the lice-forming fault layer and the gate of the silicon oxide # Lapu. Then, a photoresist layer is defined on the silicon oxide layer in order to etch s 1 μm. Moreover, the gate is formed! Conveniently, the nitrogen-cut layer and the oxidized layer are formed into a source and a drain. The previous method of ion implantation in the substrate is described in detail in the 5-4 invention. Page 6 506051 ---- Case No. 89125961 _ Year, Month, and Day Article 5. Description of the Invention (Magic " " " '' ^ Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely applied in other embodiments, the scope of the present invention is not limited, and the scope of the following patents For reference, please refer to the second figure, which is a direct-flow sputtering system. A reaction chamber 2 θ 〇 is mainly composed of a cathode electrode placing a metal target 21 〇, and a crystal base 10 3 00 (can be grounded), and a baffle 2 220. The gas required for holding the plasma and sputtering is provided by the gas supplier 240 at the other end of the reaction chamber, and the other end leads to the reaction chamber 2 〇〇 The degree of vacuum; (pump) 280. The energy required for the operation of the plasma is provided by a group of DC power supplies 250. Among them 'ground shields (gr 0 und, shield) 230A, 230B , 230C and 230D are located on both sides of the crystal base 300 and the metal target 210. In order to make electricity The positively charged ions in the slurry can hit the surface of the metal target 210, and the electrode on which the metal target 210 is placed will be connected to the DC power supply 250. Because the sputtering of metal does not have a high tolerance for impurities, especially It is oxygen and water gas, so before the metal sputtering, the pressure of the reaction chamber 200 is usually used to cryopump (Cryopump) 270 to extract these gases that have strong oxidation ability to the metal. The low pressure required before performing sputtering is the base pressure, which is usually 10-6 or even 10-7 Torr. After the reaction chamber 200 has reached the base pressure, the next step is to pass in the reaction gas to prepare for metal sputtering. Plating. Metal target before performing sputtering

The deposition and film have been contaminated. In order to avoid these impurities from forming certain plastics, and =, and to prevent the composition of the alloy metal at the initial stage of sputtering, it is not 210iJ ^ a #. The baffle plate 22 separates the metal target Si wafer 10 ′, so that the deposition at the initial stage of demineralization is carried on the seeding plate M0, and it will directly be on the surface of the substrate wafer 10. Wait until the metal target 2 1 0. j: The fender 220 is removed after the f pieces have stabilized to allow the metal to sink. /, In the ground shield (grOUnd shield) 23A and 230D are located on both sides of the wafer base 300 and the dry metal 21o.

In Ben Lemming's method, 诰 (; 2 丨 1 «(: 〇] 1 丨 11111) is used as the metal culprit 21〇 'on the wrong metal target 21 〇 and a DC power supply 2 5 〇 provides approximately 丨The power of 0.0000 watts makes the rhenium metal target 21 to ionize, and the reaction reaches a total pressure of 40 mTorr within 1000. Argon is used as the inert gas in the reaction chamber 2000, Oxygen is passed in to make oxygen and krypton ions form an oxide layer 2 Q on the substrate 丨. The dielectric constant of the yttrium oxide layer 20 is about 25, and the thickness is about 20 to 70 angstroms. , The temperature is about 250 to 450 ° C, and the pressure is about 20 to 70 mTorr. After the hafnium oxide layer 20 is formed on the substrate 10, the substrate 10 is removed from the reaction chamber 200 and tempered. The hafnium oxide layer 20, wherein the treatment time is between 20 and 50 seconds, and the treatment temperature is between 650 and 1000 C, and the total pressure is 40 mTorr. The purpose of the tempering treatment is to reduce The interface of the zirconia layer 20 sinks into the concentration of charge and can reduce the leakage current problem of the conventional silicon oxide layer 120. At the same time, the hammer oxide layer 20 can In consideration of better time-dependent dielectric breakdown characteristics, however, other money plating methods such as reactive magnetron sputtering can also be used in the present invention.

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^ According to the second figure, a silicon nitride layer 22 is formed on the zirconia layer 20. The silicon nitride layer 22 is used to replace a conventional floating gate for storing electric charges. Generally speaking, the silicon nitride layer 22 is respectively formed by low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical

(Vapor Deposition) or plasma-enhanced chemical vapor deposition (pECVD) method is formed on the hafnium oxide layer 20. However, the low-pressure chemical vapor deposition method has an operating temperature that is too high between about 650 and 800 t: Therefore, in the application of the protective layer, the silicon nitride layer 22 is formed by a plasma-promoted chemical deposition method, in which The temperature is about 250 to 400 C, and the thickness of the deposition is about 20 to ι80 Angstroms. Generally speaking, the reaction materials for forming the silicon nitride 22 include silane (SiH4) and tetraoxyethyl silicon (TEOs, Tetra —Ethyl —

Oi ^ tho-Siljcate) is formed after reacting with oxygen (02) and nitrogen oxide (N2O), respectively. Next, a chemical vapor deposition (CVD) method is used to form a silicon oxide layer 24 on the silicon nitride layer 22. The silicon layer is then formed by low pressure chemical deposition (LPCVD, Low Pressure Chemical Vapor Deposition) on the oxide layer 24 to form e 50, where the polycrystalline silicon layer 50 is decomposes by heating with silicon methyl chloride. A desired polycrystalline silicon layer 50 is formed on the silicon oxide layer 24. . Generally, when the polycrystalline silicon layer 50 is formed, the temperature is mostly controlled between 600 and 650 ° C, and the reaction pressure is about several hundred mTorr. The thickness of the polycrystalline silicon layer 50 is about 80 to 20. 〇〇Angels. Next, the image transfer photoresist layer is on the polycrystalline silicon layer 50 and the image transfer pattern is a gate. Then, a photoresist mask is used to sequentially etch the polycrystalline silicon layer 50, the silicon oxide layer 24, and nitride.

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The silicon layer 22 and the oxide layer 20 are oxidized to form a gate structure, and then the optical layer is removed. With reference to the fourth figure, lightly doped drain regions r and 14 (Light-Doped Drain, LDD) are implanted on the substrate 10 by ion implantation. Next, a uniform layer of silicon is deposited on the substrate and gate structure. This wafer is covered with an oxide layer, and a gap is formed on the side of the gate structure by using anisotropic | insect etching (an n s 〇 t Γ 〇 p i C a 1 etching). Because this anisotropy = the thickness of the oxide oxide layer to be etched, the oxide oxide layer is at the gate junction

The degree of drought is greater than other parts, but this etching step will not remove you a, stone 9. Therefore, the spacers 26 and 28 are on the side of the gate structure, and 28 and 28 serve as one and the drain 12. Or high solids and deep ions. According to the fifth figure, all gate structures and spacers 2 6 masks are used, and ion source implantation is used to form the source regions 1 1 to 1. The seeds are heavily doped and I = resolution. Arsenic can be ionized to perform higher concentrations and the ion implantation concentration is about 1015 cm 2. In this traditional zirconia, the thermal budget is lowered due to the lower heat budget, which can reduce the crystal layer oxygen and the cell strength. In addition to the actual method, it is applied in the form of a sputter shape. The oxide hammer is formed in a tunnel manner, and the temperature of the inter-temperature oxide layer formed by the hammer is used. Therefore, the high dielectric constant of hafnium oxide is beneficial. Furthermore, the high coupling rate plus the complete oxidation of the gated dielectric layer greatly controls the oxygen integrity layer. The voltage drop below is reduced due to the trap

Page 10 506051 _Case No. 89125961_ Year Month Revision _5. Description of the invention (8) The reliability of flash memory has been increased. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 11 506051 _Case No. 89125961_ 年月 日 __ Brief description of the drawings The first diagram is a cross-sectional view of a semiconductor wafer to illustrate the traditional schematic diagram of forming a gate dielectric layer in a conventional silicon nitride read-only memory; The second figure is a schematic diagram showing a device for forming a gate dielectric layer method; the third figure is a cross-sectional view of a semiconductor wafer according to the present invention to explain the steps of forming a gate dielectric layer on a substrate; The fourth figure is a cross-sectional view of a semiconductor wafer according to one of the present invention to illustrate the steps for forming a spacer according to the present invention; the fifth figure is a view of forming a gate dielectric layer in a silicon nitride read-only memory according to the present invention. schematic diagram. Representative symbols of the main parts: 10 substrate 11 source 12 drain 13 N well 14 N well 20 zirconia layer 22 silicon oxide layer 24 nitrided layer 26 gap wall

506051 Amendment number 89125961 Brief description of the drawing 2 8 Spacer wall 5 0 Polycrystalline silicon layer 1 0 0 Substrate 1 0 1 Source 1 0 2 Drain 103 N Well 104 N Well 1 2 0 Silicon oxide layer 1 2 2 Silicon nitride Layer 124 Silicon oxide layer 1 2 6 Gap wall 1 2 8 Gap wall 2 0 0 Reaction chamber 210 Metal target 2 2 0 Baffle 2 3 0 A ground shield 2 3 0 B ground shield 2 3 0 C ground shield 2 3 0 D ground shield 240 Gas supply source 2 5 0 DC power supply source 2 6 0 Isolation valve 270 Freezing pump 2 8 0 Mechanical pump 2 9 0 Ground wire

Page 13 506051 Case No. 89125961_Year Month and Day Amendment Brief description of the drawing 3 0 0 Wafer support See page 14

Claims (1)

six Amendment ^: A method for forming a gate dielectric layer in a silicon nitride read-only memory, the method at least includes: " A substrate provided by the patent application scope of electrical increase; and a substrate on the substrate; A sputtering layer is used to form a monolayer of oxide. A is formed. The dielectric layer in the read memory is U. The shape of U is H. The shape of P is φ. Hemp ^^ ^ On the edge of the silicon wafer. Read memory 8000 between it. The temperature for forming the tick hammer in Bazhong is about 200 to 200 ° C. The above zirconia layer system is beneficial. The above-mentioned shape on the substrate further includes a tempering step. 2. If the method according to item 1 of the scope of patent application is applied, use reactive magnetron sputtering to form the substrate on the substrate 3. If the method according to item 1 of the scope of patent application, the thickness of the oxidized layer is about 20 to 70 Angstroms. 4. According to the method in the scope of patent application, the zirconia layer is treated. 6 · The gas environment is the inert gas as described in the 4th patent application. Item method, wherein the tempering Method for forming a gate dielectric layer in nitride nitride read-only memory Page 15 506051 Case No. 89125961 6. The scope of the patent application The method at least includes: providing a substrate; forming a zirconia layer on the substrate by a sputtering method to form the ^ fossil evening read-only memory The gate dielectric layer in the 'forms the gate dielectric layer in the silicon nitride read-only note; and' ° ~ a tempering step is performed on the zirconia layer. 8. The method according to item 7 of the scope of patent application, wherein the zirconia layer is formed on the substrate by a reactive magnetron subtraction: plating method. 9. The method according to item 7 of the scope of patent application, wherein the temperature at which the oxide layer is formed is between about 200 and 800 ° C. I 0 · The method according to item 7 of the scope of patent application, wherein the thickness of the oxide layer formed on the substrate is about 20 to 70 angstroms. II. The method according to item 7 of the patent application range, wherein the tempering step is performed at a temperature of about 6500 to 100 ° C and a time of about 20 to 50 seconds. 1 2 · The method according to item 7 of the scope of patent application, wherein the gas environment of the above-mentioned tempering treatment is an inert gas. 1 3 · The method according to item 7 of the scope of patent application, wherein the environment during the tempering treatment is selected from the group consisting of argon, nitrogen and nitrogen oxide. li Page 16 506051 8912RQR1 Amendment VI. In the scope of patent application 〇14 · —A method of forming silicon nitride only green # 卜 立 _ 士 & VII, also X, Mo Shi contains ·% item g memory The method provides at least one substrate; $ :, a zirconia layer is formed on the material by sputtering; a tempering step is performed on the oxidized oxide layer; and a silicon nitride sound is formed on the oxidized oxide layer. In the Forming a silicon oxide layer on the silicon nitride layer; forming a polycrystalline silicon layer on the silicon oxide layer; forming a photoresistor pattern on the polycrystalline silicon layer to form a photoresist mask; the light The resistance system is defined as a gate that uses the photoresist as a mask to etch. The silicon nitride layer and the oxide layer are shaped as :: silicon layer, and the silicon oxide layer removes the photoresist layer; ^ — A gate electrode; forming a gap wall on a side wall of the gate electrode; and in the substrate, both sides of the gate electrode-a source electrode and a drain electrode. 15. The method according to item 14 of the patent application, which uses the reactive magnetron sputtering method to form the above-mentioned gaseous rhenium layer on the substrate. 16. The method according to item 14 in the patent application, wherein zirconium The temperature of the layer is between 2000 and 800 ° C. '、 The above-mentioned formation of the oxidation page 17 506051 _ case number 89125961 _ month_day_ charm _ 6. Application for patent scope 17. The method of applying for the scope of patent application No. 14 wherein the above-mentioned oxide file layer is formed on the substrate The thickness is between 20 and 70 Angstroms. 18. The method according to item 14 of the scope of patent application, wherein the temperature of the above-mentioned tempering treatment of the zirconia layer is about 6 50 to 100 ° C and the time of the tempering is about 20 to 50. Between seconds. 19. The method according to item 14 of the scope of patent application, wherein the environment during the tempering treatment is selected from the group consisting of argon, nitrogen and nitrogen oxides. Page 18