505845 Α7 Β7 五、發明說明（1 ) 本發明與控制電子系統之操作狀態的裝置有關，特別 是低功率的電子系統，由電源供應電力，此電子系統特別 包括一微處理器，能在一最低保證工作位準下操作。此裝 置特別是意欲用來供應信號，稱爲"重置"信號，只要電源 所供應的電壓低於一決定的電壓位準，即將微處理器保持 在一決定的狀態，稱爲"重置"狀態。 本發明也與配置上述電子系統的裝置以及用以控制此 種電子系統之操作狀態的方法有關。 本文中的"灰色區"意指一個區域，在此區域中，電子 系統中的至少一個微處理器被低於微處理器之最低保證工 作位準的供應電壓位準供電，且其中該微處理器不再在一 決定的重置狀態。從以下的描述將可瞭解，當此微處理器 在此"灰色區"時，微處理器有可能產生錯誤的操作或執行 錯誤的指令。 當微處理器被接通時，爲使微處理器保持在重置狀態 ，通常會配置一接通-重置電池，它的門檻高於微處理器可 以操作的最低保證工作位準。因此，當電源接通時，可以 確保微處理器保持在決定的重置狀態，直到供應的電壓到 達高於此最低保證工作位準的位準。 不過，在低電力的應用中，無法採用上述方法，βρ， 使用門檻高於微處理器之最低保證工作位準的接通-重置電 池。考慮所有溫度漂移及製造的公差，高於微處理器之最 低工作位準的保證重置門檻通常會太高，且會大幅縮短電 源（如電池）的壽命。 ----II------裝 * II (請先閱讀背面之注意事項再填寫本頁) 訂·· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- 505845 A7 B7 ................. ......... .............. ......................... ......... w -m 丨丨 11111111——................................. 五、發明說明（2 ) 舉例來訴、由大約5伏之電源供電且包括一微處理器 的低電力電子系統，它的最低保證工作門檻大約1.9伏。此 種低電力電子系統的例子特別如申請人（Ε Μ M i c r 〇 e 1 e c t r ο n i c -Marin SA公司）所售的EM6640 M位元微控制器"。 前述方法在於使用一門檻高於微處理器之最低保證工 作門檻的接通-重置電池，加上製造公差及溫度的變化，其 門檻至少等於2伏。當此系統被接通時，電源的壽命會大 幅縮短，基本上是由接通-重置電池所致。 爲克服此問題，按照本發明，一種選擇是使用門檻低 的接通-重置電池，或至少可以變得比微處理器的最低保證 工作位準低。此即出現前所述的"灰色區"，其範圍由接通-重置電池的門檻與微處理器的最低保證工作位準間的電壓 定義。在此區域中，微處理器有可能執行錯誤的指令，系 統的操作可能會發生不合宜的結果。特別是，錯誤的資料 可能被當成碼，例如密碼，寫入系統的非揮性記憶體 (EEPROM)中 〇 本發明的目的是允許使用重置門檻低的接通-重置電池 ，同時保證它在"灰色區"時不會執行指令。 因此，本發明與控制低電力電子系統之操作狀態的裝 置有關，具有如申請專利範圍第！項所列舉的特徵。 本發明也與低電力電子系統有關，具有如申請專利範 圍第7項所列舉的特徵。 本發明也與控制低電力電子系統之操作狀態的方法有 關，具有如申請專利範圍第8項所列舉的特徵。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------I----^ 裝·！ {請先閱讀背面之注意事項再填寫本頁) 訂. %· 經濟部智慧財產局員工消費合作社印製 -5- 505845 A7 B7 ... -- — —1_11 II - —.... ’ ' . 五、發明說明（3 ) 申請專利範圍附屬項的主題是實施例的優點。 本發明的優點之一在於使用重置門檻低的接通-重置電 池以增加電源的壽命。 本發明的另一優點在於可防止微處理器執行錯誤的指 令。 本發明還有另一優點在於使用--簡單的邏輯裝置延長 微處理器的重置狀態。這些邏輯裝置可完全直接地整合到 系統中，不需要額外的製造成本。 經由閱讀以下對非限制之實例的詳細說明並配合附圖 ，將可明瞭本發明的其它特徵及優點，其中： -圖1顯示按照本發明之電子系統的模組圖，特別包 括一微處理器，它的操作狀態被控制； 一圖2顯示圖1之電子系統之操作模組的實施例，按照 本發明’允許產生微處理器所要的重置信號；以及 一圖3顯示圖1之電子系統的供應電壓隨時間演化的時 間圖，顯示本電子系統之操作狀態的控制過程。 主要元件對照表 1 電子系統 10 微處理器 5 電源 40 供電模組 20 時計系統 33 延時操作模組 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） IIIIIII —---* I I (請先閱讀背面之注音？事項再填寫本頁) 訂： %· 經濟部智慧財產局員工消費合作社印製 -6- 505845 A7 ____B7 五、發明說明（4 ) 30 重置裝置 32 接通-重置電池 34 檢知模組 35 第一正反器 36 第二正反器 37 NAND 閘 (請先閱讀背面之注意事項再填寫本頁) 圖1顯示構成本發明之實施例的低電力電子系統1的模 組圖，以參考編號1指示。電子系統1由電源5供電。爲說 明，此電源5是供應低電壓的典型電池，爲說明，其電壓 大約5.5伏。電源5連接到供電模組40，它的第一端40.1 供應相對於定義在第二端40.2之接地電壓VSS的供應電壓 V DD。 經濟部智慧財產局員工消費合作社印製 圖1所說明的電子系統1包括至少一個中央處理單元或 微處理器1 0以及一組周邊單元（未顯示），特別是包括記憶 體裝置（ROM、RAM、EEPROM)、輸入閘與輸出閘。微處 理器1 0適合從最低保證工作位準Vdd, „…,開始正確地操作。 爲說明，微處理器1 0可以正確操作的最低保證工作位準 V D D , m i η 大約 1.9 伏。 電子系統1還包括時計系統2 0，其內例如包括一個R c 振盪器（未顯示），它至少供應一個時計信號給系統的組件。 時計系統20例如包括輸出20.1及20.2，每一個分別供應時 計信號CLK 1及CLK2。因此，時計系統的輸出20.1連接到 微處理器10的輸入或時計輸入10.1。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮) ""^ 經濟部智慧財產局員工消費合作社印製 505845 A7 ____ B7 五、發明說明（5 ) 時計信號的基頻例如大約600kHz，但時計系統20也可 供應次分於基頻的時計信號。因此，典型上，以分頻鏈（未 顯示）從時計系統2 0的上述基頻中得到所要的頻率。特別是 ，如後文中所述，時計系統20例如供應頻率大約1 kHz的時 5十is號給圖1之電子系統1的模組3 3。不用說，本描述中 所提及的頻率數値僅是用於說明。 電子系統1也包括重置裝置，整體以虛線包圍並以參 考編號30指示。這些重置裝置30確保微處理器丨〇保持在 決定的重置狀態。因此，微處理器1 〇包括·一重置輸入1 〇. R ’重置邏輯信號C P U R S T施加於該點。只要施加於微處理 器10之重置輸入的信號ςρυ RST爲"高"邏輯位準，它就保 持在重置狀態。當施加在重置輸入的信號CPU RST變爲，•低 "邏輯位準時，微處理器1 0即從它的重置狀態釋放。 更明確地說，重置裝置3 0可分成兩個次總成。第一個 次總成是由接通-重置電池3 2構成。第二個次總成是由第一 及第二操作模組所構成，分別編號爲33及34 ,以下將進一 步詳細描述。505845 Α7 Β7 V. Description of the invention (1) The present invention relates to a device for controlling the operating state of an electronic system, especially a low-power electronic system powered by a power source. This electronic system includes a microprocessor, which can Ensure that the operating level is maintained. This device is especially intended to supply a signal, called a "reset" signal, as long as the voltage supplied by the power supply is lower than a determined voltage level, that is, the microprocessor is maintained in a determined state, referred to as "quote". Reset " status. The present invention also relates to a device for configuring the above-mentioned electronic system and a method for controlling an operating state of such an electronic system. The "grey area" herein means an area in which at least one microprocessor in an electronic system is powered by a supply voltage level lower than the minimum guaranteed operating level of the microprocessor, and wherein the The microprocessor is no longer in a determined reset state. It will be understood from the following description that when this microprocessor is in the "grey area", the microprocessor may produce wrong operation or execute wrong instructions. When the microprocessor is turned on, in order to keep the microprocessor in the reset state, a switch-on reset battery is usually configured, and its threshold is higher than the minimum guaranteed operating level at which the microprocessor can operate. Therefore, when the power is turned on, it can be ensured that the microprocessor remains in the determined reset state until the supplied voltage reaches a level higher than this minimum guaranteed operating level. However, in low-power applications, the above method cannot be adopted. Βρ uses the on-reset battery with a threshold higher than the minimum guaranteed operating level of the microprocessor. Considering all temperature drift and manufacturing tolerances, the guaranteed reset threshold above the minimum operating level of the microprocessor is usually too high and will significantly reduce the life of power supplies such as batteries. ---- II ------ Installation * II (Please read the precautions on the back before filling out this page) Order ·· Printed on the paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to Chinese National Standards (CNS) A4 specification (210 X 297 mm) -4- 505845 A7 B7 ..................... ............................. w -m 丨 丨 11111111 ——... .............. 5. Description of the Invention (2) For example, it is powered by a power supply of about 5 volts and includes A microprocessor-based low-power electronic system with a minimum guaranteed operating threshold of approximately 1.9 volts. An example of such a low-power electronic system is, in particular, the EM6640 M-bit microcontroller " sold by the applicant (EM M i c r 0 e 1 e c t r n n c -Marin SA). The foregoing method consists in using a switch-on reset battery with a threshold higher than the minimum guaranteed operating threshold of the microprocessor, plus manufacturing tolerances and changes in temperature, the threshold being at least equal to 2 volts. When this system is turned on, the life of the power supply is greatly reduced, which is basically caused by turning on-resetting the battery. To overcome this problem, according to the present invention, one option is to use a switch-on battery with a low threshold, or at least it can become lower than the minimum guaranteed operating level of the microprocessor. This is the "grey area" described earlier, whose range is defined by the voltage between the threshold for turning on-resetting the battery and the minimum guaranteed operating level of the microprocessor. In this area, the microprocessor may execute the wrong instruction, and the operation of the system may cause undesired results. In particular, erroneous information may be treated as a code, such as a password, which is written into the non-volatile memory (EEPROM) of the system. The purpose of the present invention is to allow the use of a reset-on battery with a low reset threshold while guaranteeing it Instructions will not be executed in the "gray area". Therefore, the present invention is related to a device for controlling the operation state of a low-power electronic system, and has the same scope as the scope of patent application! Items listed. The present invention is also related to low power electronic systems, and has the features as listed in item 7 of the patent application range. The present invention is also related to a method of controlling an operating state of a low power electronic system, and has the features as listed in item 8 of the scope of patent application. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------- I ---- ^ Loading ·! (Please read the precautions on the back before filling out this page) Order.% · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -5- 505845 A7 B7 ...-— — 1_11 II-—.... '' V. Description of the invention (3) The subject matter of the appended item of the patent application scope is the advantage of the embodiment. One of the advantages of the present invention is to use an on-reset battery with a low reset threshold to increase the life of the power supply. Another advantage of the invention is that it prevents the microprocessor from executing erroneous instructions. Yet another advantage of the invention resides in the use of simple logic means to extend the reset state of the microprocessor. These logic devices can be integrated directly into the system without additional manufacturing costs. Other features and advantages of the present invention will be made clear by reading the following detailed description of non-limiting examples in conjunction with the accompanying drawings, of which:-Figure 1 shows a block diagram of an electronic system according to the present invention, including in particular a microprocessor , Its operating state is controlled; FIG. 2 shows an embodiment of the operation module of the electronic system of FIG. 1 according to the present invention, “allows generation of a reset signal required by the microprocessor; and FIG. 3 shows the electronic system of FIG. 1 The time chart of the supply voltage evolution over time shows the control process of the operating state of the electronic system. Comparison table of main components 1 Electronic system 10 Microprocessor 5 Power supply 40 Power supply module 20 Timepiece system 33 Time-delay operation module The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) IIIIIII ----- * II (Please read the note on the back? Matters before filling out this page) Order:% · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy-6- 505845 A7 ____B7 V. Description of the invention (4) 30 Reset device 32 On- Reset battery 34 Detection module 35 First flip-flop 36 Second flip-flop 37 NAND gate (please read the precautions on the back before filling this page) Figure 1 shows the low-power electronic system that constitutes an embodiment of the present invention The module diagram of 1 is indicated by reference number 1. The electronic system 1 is powered by a power source 5. For illustration, this power supply 5 is a typical battery supplying a low voltage, and for illustration, its voltage is about 5.5 volts. The power supply 5 is connected to the power supply module 40, and its first terminal 40.1 supplies a supply voltage V DD relative to the ground voltage VSS defined at the second terminal 40.2. Printed in Figure 1 by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the electronic system 1 includes at least one central processing unit or microprocessor 10 and a set of peripheral units (not shown), especially including memory devices (ROM, RAM , EEPROM), input gate and output gate. Microprocessor 10 is suitable to operate correctly from the lowest guaranteed operating level Vdd,… ,. To illustrate, the lowest guaranteed operating level VDD, mi η at which microprocessor 10 can operate correctly is approximately 1.9 volts. Electronic system 1 It also includes a timepiece system 20, which includes, for example, an R c oscillator (not shown), which supplies at least one timepiece signal to the system's components. The timepiece system 20 includes, for example, outputs 20.1 and 20.2, each of which provides a timepiece signal CLK 1 And CLK2. Therefore, the output of the timepiece system 20.1 is connected to the input of the microprocessor 10 or the timepiece input 10.1. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297) issued " " Printed by the Consumer Cooperative of the Property Bureau 505845 A7 ____ B7 V. Description of the Invention (5) The fundamental frequency of the timepiece signal is, for example, about 600kHz, but the timepiece system 20 can also supply the timepiece signal subdivided to the fundamental frequency. Therefore, typically, A frequency chain (not shown) obtains a desired frequency from the above-mentioned fundamental frequency of the timepiece system 20. In particular, as described later, the timepiece system 20 supplies, for example, a frequency of about 1 kH z 时 50 十 is number is given to the module 3 3 of the electronic system 1 in Fig. 1. Needless to say, the frequency number 提及 mentioned in this description is only for illustration. The electronic system 1 also includes a reset device, and the overall The dashed line is enclosed and indicated by reference number 30. These reset devices 30 ensure that the microprocessor stays in the determined reset state. Therefore, the microprocessor 1 〇 includes a reset input 1 〇 R 'reset logic signal CPURST is applied at this point. As long as the signal ρρRST applied to the reset input of the microprocessor 10 is "high" logic level, it remains in the reset state. When the signal applied to the reset input CPU RST changes Because, when the logic level is low, the microprocessor 10 is released from its reset state. More specifically, the reset device 30 can be divided into two sub-assemblies. The first sub-assembly is composed of The on-reset battery is composed of 3.2. The second sub-assembly is composed of the first and second operation modules, numbered 33 and 34, respectively, which will be described in further detail below.
接通-重置電池3 2典型上被安排系統1只要被接通，即 供應重置信號或更正確地說是接通-重置信號P〇R。當電池 5發生改變時，即系統的供應電壓Vdd從實質的零位準（從 Vss)增力卩，此電池32即產生重置信號POR。更明確地說， 只要供應電壓Vdd沒有超過稱爲接通-重置門檻vPQR的門檻 ’此接通··重置電池3 2即供應在第一邏輯位準的接通-重置 信號POR，只要此供應電壓VD〇超過此接通-重置門檻Vp()R 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I * I I (請先閱讀背面之注意事項再填寫本頁) 訂· 505845 s. 齊 t % !才 t h % A7 __B7____五、發明說明（6 ) ，它即進入第二邏輯位準。 重置信號POR供應到接通-重置電池32的輸出32.1， 供應給各組件的重置輸入，特別是時計系統20的重置輸入 20.R及第一與第二操作模組33及34的重置輸入33.R及 3 4.R。在以下的描述中，對系統各組件的重置輸入的標示 ，將在對應組件的參考編號後加一個"R"。 接通-重置電池32被連續地供電以便供應重置信號POR ，當電池5的供應電壓VDD不超過決定的接通-重置門檻V_ 時，重置信號POR即在第一邏輯位準，例如"低"的邏輯位 準。當超過接通-重置門檻Vpodlf，它在第二邏輯位準，例 如”高"的邏輯位準。習慣.上，當"高"邏輯信號施加到它們的 重置輸入時，各組件被設定到零或保持在重置狀態。因此 ，時計系統20與2個操作模組33及34的重置輸入20. R、 3 3.R及34.R被反轉，如圖1所示，只要接通-重置信號P〇R 仍保持在"低"邏輯位準，就使對應的組件設定到零。 按照本發明，接通-重置電池32的接通-重置門檻VP〇R ，設定在等於，或特別定義在比微處理器10可以正確操作 之最低保證工作位準Vdd,…更低。爲說明，接通-重置門檻 VP〇R定在大約是1.5伏，即低於前述1.9伏的最低保證工作 位準 Vdd, min。 如在本描述的前言中提及，在接通-重置電池3 2的接通 -重置門檻VP〇R(超過此，微處理器10不再被該電池32保持 在重置狀態）與微處理器10的保證最低工作位準Vdd, ηιι„間， 出現一稱爲"灰色區"的區域。在此H灰色區"中，如果微處理 -*裝 (請先閱讀背面之注意事項再填寫本頁) . ?! 本紙張尺度適用中國國家標準（CNS)A4規格（2J0 X 297公釐） 經濟部智慧財產局員工消費合泎；*1印_ 505845 ' A7 B7 五、發明說明（7 ) 器沒有保持在重置狀態，微處理器1 0有可能產生錯誤的操 作，特別是給予系統之記億體錯誤的寫入指令。因此，現 在將描述按照本發明如何避免此情況。 從以上的描述可瞭解，當接通-重置電池32所供應的重 置信號POR從第一邏輯狀態轉換到第二邏輯狀態時，時計 系統20、第一及第二操作模組33、34以及所有其它未顯 示但重置輸入都連接到接通-重置電池32的組件，都從它們 的重置狀態釋放，並開始操作。 一方面，圖1的第一操作模組33被安排成能延遲釋放 系統重置狀態一決定的最小周期，特別是微處理器1 0 之重置狀態的釋放。此周期經過選擇，特別是爲了使 時計系統20被起動時，允許它的RC振盪器到達穩定。 典型上，此周期Δ^ΤΑβ例如大約1毫秒。因此，第一模 組33也可稱爲延時操作模組。此延時操作模組33特別包括 --時計輸入33.C連接到時計系統20的輸出20.2，它供應第 二時計信號CLK2，頻率例如爲1kHz。延時操作模組33在 它的輸出33.2產生微處理器10的重置信號CPU RST。 另一方面，按照本發明，此第一模組33被安排成只要 電池5所供應的供應電壓Vdd未超過微處理器的最低保證工 作位準VDD, ，即延遲微處理器10之重置狀態的釋放。電 子系統1還包括第二模組或檢知模組，以參考編號34表示 。此檢知模組被安排成監視電池5所供應的供應電壓VDD， 並提供至少·一個代表供應電壓Vdd之位準的邏輯控制信號。 特別是，檢知模組34被安排成，如果供應電壓Vdd低於所 本紙張尺度適用中國國家標準（CNS)A4規格(幻0 X 297公釐） ^ .1Π - (請先閱讀背面之注意事項再填寫本頁)The on-reset battery 3 2 is typically arranged so that as long as the system 1 is on, a reset signal or more precisely a on-reset signal POR is supplied. When the battery 5 is changed, that is, the supply voltage Vdd of the system is increased from the substantial zero level (from Vss), the battery 32 generates a reset signal POR. To be more specific, as long as the supply voltage Vdd does not exceed a threshold called the on-reset threshold vPQR 'this on ·· resetting the battery 32, the on-reset signal POR at the first logic level is supplied, As long as the supply voltage VD〇 exceeds the on-reset threshold Vp () R, the paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I * II (Please read the precautions on the back before filling This page) Order · 505845 s. Qi t%! Only th% A7 __B7____ 5. Description of the invention (6), it enters the second logical level. The reset signal POR is supplied to the output 32.1 of the on-reset battery 32, and to the reset input of each component, especially the reset input 20.R of the timepiece system 20 and the first and second operation modules 33 and 34. The reset inputs are 33.R and 3 4.R. In the following description, the reset input of each component of the system will be marked with "" R " after the reference number of the corresponding component. The on-reset battery 32 is continuously powered to supply a reset signal POR. When the supply voltage VDD of the battery 5 does not exceed the determined on-reset threshold V_, the reset signal POR is at the first logic level. For example, " low " logic level. When the on-reset threshold Vpodlf is exceeded, it is at a second logic level, such as the "high" logic level. Conventionally, when the "high" logic signal is applied to their reset inputs, each The components are set to zero or remain in the reset state. Therefore, the reset input 20. R, 3 3.R and 34.R of the timepiece system 20 and the two operation modules 33 and 34 are reversed, as shown in Figure 1. It is shown that as long as the ON-reset signal POR remains at the "low" logic level, the corresponding component is set to zero. According to the present invention, the ON-RESET of the ON-RESET battery 32 The threshold VP0R is set equal to, or is specifically defined to be lower than the minimum guaranteed working level Vdd, ... at which the microprocessor 10 can operate correctly. To illustrate, the on-reset threshold VP0R is set to approximately 1.5 Volts, which is lower than the minimum guaranteed operating level Vdd, min of the aforementioned 1.9 volts. As mentioned in the foreword of this description, the on-reset threshold VP0R of the on-reset battery 32 is greater than this The microprocessor 10 is no longer kept in the reset state by the battery 32) and the guaranteed minimum working level Vdd, ηι of the microprocessor 10 appears, Referred to as " gray zone " region. In this H gray area ", if micro processing-* installation (please read the precautions on the back before filling this page).?! This paper size is applicable to China National Standard (CNS) A4 (2J0 X 297 mm) Consumption of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs; * 1 印 _ 505845 'A7 B7 V. Description of the invention (7) The device is not kept in the reset state, and the microprocessor 10 may cause incorrect operation, especially for the system. Billion body wrong write instruction. Therefore, how to avoid this according to the present invention will now be described. As can be understood from the above description, when the reset signal POR supplied by the on-reset battery 32 transitions from the first logic state to the second logic state, the timepiece system 20, the first and second operation modules 33, 34 And all other components not shown but with the reset input connected to the on-reset battery 32 are released from their reset state and operation begins. On the one hand, the first operation module 33 of FIG. 1 is arranged to delay the release of a minimum period determined by the reset state of the system, in particular the release of the reset state of the microprocessor 10. This period is chosen, in particular to allow the chronograph system 20 to start to stabilize when its RC oscillator is activated. Typically, this period Δ ^ ΤΑβ is, for example, about 1 millisecond. Therefore, the first module 33 can also be referred to as a delayed operation module. This delayed operation module 33 includes in particular a timepiece input 33.C connected to the output 20.2 of the timepiece system 20, which supplies a second timepiece signal CLK2, for example, a frequency of 1 kHz. The delay operation module 33 generates a reset signal CPU RST of the microprocessor 10 at its output 33.2. On the other hand, according to the present invention, the first module 33 is arranged to delay the reset state of the microprocessor 10 as long as the supply voltage Vdd supplied by the battery 5 does not exceed the minimum guaranteed operating level VDD of the microprocessor. Release. The electrical subsystem 1 also includes a second module or a detection module, which is denoted by reference number 34. The detection module is arranged to monitor the supply voltage VDD supplied by the battery 5 and provide at least one logic control signal representing the level of the supply voltage Vdd. In particular, the detection module 34 is arranged so that if the supply voltage Vdd is lower than the size of the paper, the Chinese National Standard (CNS) A4 specification (magic 0 X 297 mm) is applied ^ .1Π-(Please read the note on the back first (Fill in this page again)
經濟部智慧財產局員工消費合作社印製 505845 A7 B7_____ 五、發明說明（8 ) 決定的參考門檻VReFI，則它在第一輸出34.1供應第一邏輯 位準的第一邏輯控制信號CPU ENBL >例如是"低"邏輯位準 ，以及，如果供應電壓Vdd高於所決定的參考門檻VREF1， 則它供應第二邏輯位準，例如是"高"邏輯位準。此第--參 考門檻VREF^f過選擇，高於或等於微處理器1〇的最低保證 工作位準VDD, _。此第一控制信號CPU ENBL供應給延時 模組33的輸入33.1。 按照本發明，第一模組或延時模組33因此釋放微處理 器1 0的重置狀態，即，在所決定之允許時計系統20之RC 振盪器到達穩定的時間周期Δ^ταβ之後，致使重置信號CPU RST從"高"邏輯位準到”低"邏輯位準。如果，在此決定的時 間周期Mstab結束後，檢知模組34指示供應電壓VDD還未到 達所定義之高於微處理器10最低保證工作位準Vdd, 的參 考門檻VkEFI，則只有在檢知模組供應"高"邏輯位準的控制 信號CPU ENBL時才會釋放重置狀態。 現在梦考圖2說明能做到上述功能之延時模組3 3的實 施例。不過，此例純粹是爲說明，並非用於限制。熟悉此 方面技術之人士應注意，有極多的邏輯方式都能做到相同 的功能。 1 圖2顯示可以用來完成圖1之延時模組33功能的延時 模組例。此延時模組也以參考編號33指示，它包括第_及 第二正反器35及36，每一個都分別包括時計輸入35χ、 36.C，重置輸入35.R、36.R，資料輸入35.1、36·1，以及 輸出35.2、36.2。延時模組33也包括NAND閘37，配置有· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives 505845 A7 B7_____ V. The reference threshold VReFI determined by the invention description (8), it supplies the first logic control signal CPU ENBL > at the first output 34.1, for example Yes " low " logic level, and if the supply voltage Vdd is higher than the determined reference threshold VREF1, it supplies a second logic level, such as " high " logic level. This threshold--the reference threshold VREF ^ f is too high, which is higher than or equal to the minimum guaranteed operating level VDD, _ of the microprocessor 10. This first control signal CPU ENBL is supplied to the input 33.1 of the delay module 33. According to the present invention, the first module or the delay module 33 therefore releases the reset state of the microprocessor 10, that is, after the determined RC oscillator of the timepiece system 20 reaches a stable time period Δ ^ ταβ, causing The reset signal CPU RST goes from the "high" logic level to the "low" logic level. If, after the determined time period Mstab ends, the detection module 34 indicates that the supply voltage VDD has not reached the defined level Above the reference threshold VkEFI of the minimum guaranteed working level Vdd of the microprocessor 10, the reset state will only be released when the module supplies the "high" logic level control signal CPU ENBL. Now the dream test Figure 2 illustrates an embodiment of the delay module 33 that can achieve the above functions. However, this example is purely for illustration, not for limitation. Those familiar with this technology should note that there are many logical ways to do it. To the same function. 1 Figure 2 shows an example of a delay module that can be used to complete the function of the delay module 33 of Figure 1. This delay module is also indicated with reference number 33, which includes the first and second flip-flops 35 and 36, each one includes Timepiece inputs 35χ, 36.C, reset inputs 35.R, 36.R, data inputs 35.1, 36 · 1, and outputs 35.2, 36.2. The delay module 33 also includes a NAND gate 37, which is equipped with this paper size. China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the notes on the back before filling this page)
-11 - 經濟部智慧財產局員工消費合作社印製 505845 A7 B7___ 五、發明說明（9 ) 2個輸入，分別連接到第一及第二正反器35及36的輸出 35.2、36.2，它的輸出產生重置信號CPU RST，經由延時 模組33的輸出33.2輸出。NAND閘37滿足NO AND的邏輯 功能，即，唯有它的兩個輸入都在"高"邏輯位準 > 它的輸 出才會產生"低"邏輯信號。 正反器35及36的重置輸入35.R、36.R在延時模組的 反相重置輸入33.R連接在一起，因此，當接通-重置電池32 占於"低"邏輯位準產生重置信號P0R時，正反器35及36同 時被設定到零。 "高"邏輯位準的信號持續地施加在正反器35及36的資 料輸入35.1、36.1。時計系統20的時計信號CLK2供應到 延時模組33的時計輸入33.C，並施加到第一正反器35的 時計輸入35.C。此時計輸入35.C在此被反相。習慣上，此 指示，正反器35的輸出35.2在時計信號CLK2的尾緣成爲" 高"邏輯位準，此"高"邏輯位準是施加在資料輸入35.1上的 邏輯位準。如前所述，時計信號CLK2典型的頻率爲1 kHz ，因此，第一正反器35的輸出35.2是在時計信號CLK2的 尾緣，大約1毫秒的周期（AtSTAB)結束時，到達"高"邏輯位準 〇 來自檢知模組34的控制信號CPU ENBL經由延時模組 的輸入33.1施加到第二正反器36的時計輸入36.C。此時計 輸入36.C並未被反相，因此，習慣上，第二正反器36的輸 出36.2是在施加到它的時計輸入的時計信號（即控制信號 CPU ENBL的前緣）的前緣成爲"高"邏輯位準，此"高"邏輯位 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------Μ--- (請先閱讀背面之注意事項再填寫本頁) . •-線 -19 - 經濟部智慧財產局員工消費合作社印製 505845 A7 ___ Β7____ 五、發明說明（10 ) 準是在施加資料輸入36.1上的邏輯位準。 須瞭解，只要時計信號CLK2的尾緣及控制信號CPU ENBL的前緣分別出現在時計輸入35.C及時計輸入36.C , 則輸出35.2及36.2都變成並保持在"高"邏輯位準。當兩個 輸出35.2、36.2都爲"高"邏輯位準時，出現在NAND閘之 輸出的重置信號CPU RST因此成爲“低"邏輯位準，釋放微 處理器的重置狀態。 較佳的情況是，檢知模組34所選擇的參考門檻VREF1低 於但接近與電子系統1連接之電源5所能供應的最大供應電 壓，如此，如果電源故障或終止，例如電池衰竭，可使微 處理器1 0保持在重置狀態。因此，可防止衰竭之電源的連 接 > 它的供應電壓剛好足夠觸發微處理器1 0的重置狀態， 並迅速地降到最低保證工作位準VDD, 以下。 經由改良，如圖1的槪圖所示，檢知模組34也可以供 應另一個輸出34.2，即第二個控制信號CPU DISBL，如果 供應電壓Vdd高於決定的第二參考門檻VREF2，它在第一邏 輯位準，例如"低"邏輯位準，如果供應電壓V DD低於第二參 考門檻VREF2，則它在第二邏輯位準，例如"高"邏輯位準。 此第二參考門檻VREF2也經過選擇，高於或等於微處理器10 的最低保證工作位準VDp, 。 所選擇的檢知模組34第二參考門檻VREF2接近但高於最 低保證工作位準Vdd, ，以便告知系統電池所供應的供應 電壓Vdd已降到一低位準，在此位準以下，微處理器1〇可 能再度進入"灰色區"。因此，第二控制信號CPU DISBL例 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)-11-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 505845 A7 B7___ V. Description of the invention (9) 2 inputs, which are connected to the outputs 35.2 and 36.2 of the first and second flip-flops 35 and 36, respectively. Its output The reset signal CPU RST is generated and output through the output 33.2 of the delay module 33. The NAND gate 37 satisfies the logic function of NO AND, that is, a logic signal of "low" is generated only when its two inputs are at "high" logic level and its output. The reset inputs 35.R and 36.R of the flip-flops 35 and 36 are connected together at the inverting reset input 33.R of the delay module, so when the on-reset battery 32 accounts for " low "; When the logic level generates the reset signal P0R, the flip-flops 35 and 36 are set to zero at the same time. The "high" logic level signal is continuously applied to the data inputs 35.1, 36.1 of the flip-flops 35 and 36. The timepiece signal CLK2 of the timepiece system 20 is supplied to the timepiece input 33.C of the delay module 33 and is applied to the timepiece input 35.C of the first flip-flop 35. The meter input 35.C is now inverted here. Conventionally, with this instruction, the output 35.2 of the flip-flop 35 becomes the "high" logic level at the trailing edge of the timepiece signal CLK2. This "high" logic level is the logic level applied to the data input 35.1 . As mentioned earlier, the frequency of the clock signal CLK2 is typically 1 kHz. Therefore, the output 35.2 of the first flip-flop 35 is at the trailing edge of the clock signal CLK2. At the end of the period of about 1 millisecond (AtSTAB), it reaches "High" " Logic level. The control signal CPU ENBL from the detection module 34 is applied to the timepiece input 36.C of the second flip-flop 36 via the input 33.1 of the delay module. At this time, the clock input 36.C is not inverted. Therefore, by convention, the output 36.2 of the second flip-flop 36 is the leading edge of the clock signal (ie, the leading edge of the control signal CPU ENBL) applied to the clock input applied to it. Become a "high" logical level, this "high" logical standard paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- -Μ --- (Please read the notes on the back before filling this page). • -line-19-printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 505845 A7 ___ Β7 ____ 5. The invention description (10) must be applied Data entry logic level on 36.1. It must be understood that as long as the trailing edge of the clock signal CLK2 and the leading edge of the control signal CPU ENBL appear at the timepiece input 35.C and the timepiece input 36.C, respectively, the outputs 35.2 and 36.2 become and remain at the "high" logic bit. quasi. When the two outputs 35.2 and 36.2 are at the "high" logic level, the reset signal CPU RST appearing at the output of the NAND gate therefore becomes the "low" logic level, releasing the reset state of the microprocessor. The best case is that the reference threshold VREF1 selected by the detection module 34 is lower than but close to the maximum supply voltage that the power supply 5 connected to the electronic system 1 can supply. In this way, if the power supply fails or is terminated, such as battery failure, the The microprocessor 10 remains in the reset state. Therefore, it can prevent the connection of the depleted power supply. Its supply voltage is just enough to trigger the reset state of the microprocessor 10, and it quickly drops to the minimum guaranteed working level VDD. After the improvement, as shown in FIG. 1, the detection module 34 can also supply another output 34.2, which is the second control signal CPU DISBL. If the supply voltage Vdd is higher than the determined second reference threshold VREF2 , It is at the first logic level, such as " low " logic level, if the supply voltage V DD is lower than the second reference threshold VREF2, it is on the second logic level, such as " high " logic level . The second reference threshold VREF2 is also selected, which is higher than or equal to the minimum guaranteed working level VDp of the microprocessor 10. The selected reference module 34 second reference threshold VREF2 is close to but higher than the minimum guaranteed working level Vdd, In order to inform the system battery that the supply voltage Vdd has dropped to a low level, below this level, the microprocessor 10 may enter the "gray area" again. Therefore, the second control signal CPU DISBL exemplifies this paper Dimensions are applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
-13 - 505845 A7 B7 五、發明說明（11 ) 如用來迫使微處理器1 〇進入重置狀態，以防止在"灰色區" 中執行錯誤的指令° 須注意，也可以提供其它的參考門檻，告知供應電壓 V DD已到達一臨界門檻’此門檻不保證系統的組件能正常操 作，也都在本發明的範圍內。 圖3的時間圖說明圖1之系統的操作，其中顯示電池所 供應之供應電壓VDD的演化’以及系統的不同門檻，即接通 -重置電池32的接通-重置門檻Vp〇r、最低保證工作位準 Vdd,以及檢知模組34的兩個參考門檻VREFi及VREF2。圖中 也顯示形成在接通-重置門檻與最低保證工作位準 Vdd,…„間的"灰色區"。. 在圖3中的瞬時tO，供應電壓Vdd開始增加，接通-重 置電池32供應"低"邏輯位準的重置信號POR，且時計系統 20、延時模組33及檢知模組34都保持在零。在此階段，延 時模組33產生"高"邏輯位準的重置信號CPU RST，並使微 處理器1 0保持在重置狀態。 在瞬時tl，供應電壓Vdd到達接通-重置電池32的接通 -重置門檻，重置信號P0R到達"高"邏輯位準，因此，時計 系統20延時模組33及檢知模組34都開始操作。在此瞬時 tl，延時模組33仍供應"高"邏輯位準的重置信號。 在瞬時11 + △ t s T A B，特別是在時計系統2 0之R C振邊器穩 定結束後，重置信號CPU RST仍被延時模組33保持在"高" 邏輯位準，因爲供應電壓Vdd尙未到達第一參考門檻Vrefi 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------^--- (請先閱讀背面之注意事項再填寫本頁) - .線 經濟部智慧財產局員工消費合作社印製 -14- 經濟部智慧財產局員工消費合作社印製 505845 A7 B7 ___ 五、發明說明（12 ) 在瞬時t2，當供應電壓Vdd到達檢知模組34的第一參 考門檻VREF,，控制信號CPU ENBL變爲"高"邏輯位準，且 延時模組33在輸出33.2的重置信號CPU RST變爲"低"邏輯 位準。微處理器1 〇因此從它的重置狀態釋放。 在電池5供應之供應電壓Vdd下降期間，如圖3之時間 圖中第二部分的說明，在圖3中所示的瞬時t3，只要供應 電壓Vdd變爲低於第二參考門檻VREF2，檢知模組34監視此 供應電壓Vdd並供應”高"邏輯位準的控制信號CPU DISBL。 如前所述，此第二控制信號CPU DISBL用來將微處理器10 設定到重置狀態，以防止微處理器在"灰色區"中執行錯誤 的指令。. 也是經由改良，檢知模組34可以根據電池5所供應的 供應電壓Vdd位準供應其它的控制信號，以允許起動或關閉 微處理器10的周邊單元。因此，也可想像檢知模組34也提 供一控制信號，以阻止或允許微處理器1 0對系統之 EEPROM的寫入操作。因此，可從以上與微處理器1 0相關 的描述中汲取靈感，以控制EEPR0M的控制邏輯。 須瞭解，本描述中所描述的控制裝置可各種的修改及/ 或改變，不會偏離本發明所附申請專利範圍所定義的範圍 。特別是，熟悉此方面技術之人士可回憶各種可用的邏輯 解答以完成按照本發明之電子系統之延時模組的功能。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------1 M- i I (請先閱讀背面之注意事項再填寫本頁) 打°J· 線- -15--13-505845 A7 B7 V. Description of the invention (11) If it is used to force the microprocessor 10 into the reset state to prevent the execution of wrong instructions in the "grey area" ° Please note that other With reference to the threshold, it is informed that the supply voltage V DD has reached a critical threshold. This threshold does not guarantee that the components of the system can operate normally, and are all within the scope of the present invention. FIG. 3 is a time chart illustrating the operation of the system of FIG. 1, which shows the evolution of the supply voltage VDD supplied by the battery and different thresholds of the system, namely the on-reset threshold Vp0r of the on-reset battery 32, The minimum guaranteed working level Vdd and the two reference thresholds VREFi and VREF2 of the detection module 34. The figure also shows the "gray area" formed between the on-reset threshold and the minimum guaranteed working level Vdd, ... At the instant tO in Fig. 3, the supply voltage Vdd starts to increase and the on-reset The battery 32 supplies the "low" logic level reset signal POR, and the timepiece system 20, the delay module 33 and the detection module 34 are kept at zero. At this stage, the delay module 33 generates a "high" " Reset signal of the logic level CPU RST and keep the microprocessor 10 in the reset state. At instant t1, the supply voltage Vdd reaches the on-reset threshold of the on-reset battery 32, reset The signal P0R has reached the "high" logic level. Therefore, both the time delay system 33 and the detection module 34 of the timepiece system 20 start to operate. At this instant t1, the delay module 33 still supplies the "high" logic level. The reset signal is instantaneous 11 + △ ts TAB, especially after the RC edger of the timepiece system 2 0 is stable, the reset signal CPU RST is still held at the "high" logic level by the delay module 33 , Because the supply voltage Vdd 尙 has not reached the first reference threshold Vrefi Standard (CNS) A4 specification (210 X 297 mm) -------------- ^ --- (Please read the precautions on the back before filling out this page)-Wisdom of the Ministry of Economics Printed by the Consumer Cooperative of the Property Bureau-14- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 505845 A7 B7 ___ V. Description of the Invention (12) At instant t2, when the supply voltage Vdd reaches the first reference threshold of the detection module 34 VREF, the control signal CPU ENBL changes to the "high" logic level, and the delay module 33 outputs a reset signal of CPU 33.2. The CPU RST changes to the "low" logic level. The microprocessor 1 〇 Its reset state is released. During the period when the supply voltage Vdd supplied by the battery 5 drops, as shown in the second part of the time chart of FIG. 3, at the instant t3 shown in FIG. 3, as long as the supply voltage Vdd becomes lower than the first With reference to the threshold VREF2, the detection module 34 monitors this supply voltage Vdd and supplies the control signal CPU DISBL with a "high" logic level. As mentioned earlier, this second control signal CPU DISBL is used to set the microprocessor 10 to the reset state to prevent the microprocessor from executing erroneous instructions in the "grey area". Also through improvement, the detection module 34 can supply other control signals according to the supply voltage Vdd level supplied by the battery 5 to allow the peripheral units of the microprocessor 10 to be turned on or off. Therefore, it is also conceivable that the detection module 34 also provides a control signal to prevent or allow the microprocessor 10 to write to the system's EEPROM. Therefore, we can draw inspiration from the above description related to the microprocessor 10 to control the control logic of EEPROM. It should be understood that the control device described in this description may be variously modified and / or changed without departing from the scope defined by the scope of the patent application attached to the present invention. In particular, those skilled in the art can recall various available logical solutions to complete the function of the delay module of the electronic system according to the present invention. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------- 1 M- i I (Please read the precautions on the back before filling this page ) Hit ° J · line- -15-