TW503623B - Delay lock circuit using bisection algorithm and related method - Google Patents

Abstract

A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

Description

FIELD OF THE INVENTION: The present invention provides a method and a related circuit for delay locking, and more particularly, a method and a related circuit for locking a clock to synchronization in a one-point method. Background note: In today's information-developed society, digital information processing, communication, and assistance are gaining momentum.

Personal Digital Assistant), Internet-connected digital devices (IA ’Information Applicant), and even digital devices such as computers are used to facilitate the processing and broadcasting of digital information. When people use digital devices to propagate, exchange, and process digital information, they must be equipped with a clock trigger to process digital signals in a sequence. For example, the central processing unit in a computer needs to trigger the clock to coordinate the data access and processing of the digital circuits of the central processing unit. In addition, when a mobile phone ’s clock is used to trigger the sending and transmission of digital information, it is necessary to use the mobile phone as a receiver to receive digital signals.

The clock of the digital information is first established on the receiving side to synchronize the clock, so that the digital information can be sent and received correctly during the subsequent exchange of digital information & fL 〇

Page 5 503623

Please refer to the figure for the phase-locked electric method. Delay synchronizer 16, delay buffer • end device 22, to the root (—, Figure 1 Delay lock Step 1 Delay 2 Receiving control The circuit that generates another synchronous clock according to one clock is usually called

Phase Lock Loop circuit). The implementation of the phase-locked circuit is a Delay-Lock Loop (DLL, Delay-Lock Loop) circuit. Figure 1 shows the function of a conventional delay lock circuit. The circuit 10 is used to input a first clock 12 according to an input, and a second clock 14. The delay lock circuit 10 includes a delay buffer 20, a comparator 24, and a controller 22 16 electrically connected to the buffer 20, and has a plurality of delay units. The output terminal of the delay unit u feeds back to one end of the comparator 24. The first clock of J of the device 24 1 2. The output terminal 2 5 of the comparator 2 4 is electrically connected to the controller, and the comparator 2 2 will control the delayer 16.

Page 6 503623 V. Description of the invention (3) The operation of the delay lock circuit 10 can be described as follows. After the first clock 12 is input to the delayer i 6, the delayer 16 can delay the _th clock 丨 2 by a certain time to generate another clock, which is the second clock 14. After the second clock 14 generated by the delayer 6 is input to the buffer 20, the current output capability of the buffer 20 will be increased and output. In order to synchronize the second clock 4 with the first clock 12, the delay lock circuit 丨 0 has a feedback correction mechanism. In this mechanism, the first clock 12 and the second clock 14 are input to the comparator 24 again, and the comparator 24 compares whether the corresponding periods of the first clock and the second clock are synchronized, and the comparison result is output. To the controller 2 2. The controller 22 can control the delayer 6 according to the comparison result of the comparator 2 4 to change the delay time of the second clock 14 with the delay unit 8 and modify the time between the second clock H and the first clock 12 The delay, between. In the plurality of delay units 18 in the delay unit 16, each delay f18 can delay the second clock 丨 4 a fixed delay unit time; the delay 16 enables a different number of delay units 18, so Can change the delay time of the second pulse i 4. The above method of modifying the second clock 14 to synchronize it with the first clock 12 'can be further described by using the flowchart of FIG. Please refer to Figure 2. FIG. 2 is a flowchart of the conventional delay lock circuit 10 changing the delay time of the second clock 14 so that it _ locks on the first clock 2 and synchronizes with it. The process in Figure 2 has the following steps: Step 2 6. Start the process of delayed lock. That is, the process of adjusting the delay time of the second clock 14 to lock the first clock 12 and synchronize with it.

V. Description of the invention (4) At the beginning, after controlling the trigger of each clock cycle (initial value), the lock circuit 10 is generated, and the delay time during the initial cycle of the delay time is also synchronized. Step 28 · • Generates the second clock 14 and sends it to the comparator 24. The clock 24 can determine the two clock pairs 1 21-period and the second clock. After the comparison, the comparator 22 will control the delayer 16 to delay the corresponding clock period according to the first clock 12 by a fixed time (called the two clocks 14 of the delay time. Because the delay has an unknown system delay (systen) dehyj The initial value, the correspondence between the first clock 12 and the second clock 14 is unknown; neither can the first clock or the second clock

I device 22 indicates the first clock response period. This step is to receive the instructions for the week period corresponding to 14 and go to step 30; if not, after pulse 14, you can compare the relationship between the two clock periods corresponding to the first clock 2 and the second clock. Compare the sequential relationship during the week, that is, the first time hand pulse 1 4 corresponds to the leading / lagging gate 2 during the week 2 4 can send a corresponding comparison signal to the control 1 2-whether the cycle is ahead of the second clock 丨 4 The middle pair compares the first clock 12 and the second clock advance / lag relationship by the comparator 24. If the first clock 12 is leading, go to step 32. Step 30: After receiving the comparison signal from the comparator 24, the controller 22 determines how to adjust the delay time of the second clock 14. From step 30 to this step, the controller 24 will reduce the activated delay unit 18 by one. As mentioned previously, 'Each delay unit 18 can delay the second clock and delay a unit time (hereinafter referred to as d t; for example, 1 d t can be one hundred millionth of a second). Starting the delay unit 18 less often reduces the delay time of the second clock 14 by a delay unit time (d t). After completing this step and adjusting the delay time of the second clock 1 4, the whole process will be returned to step 2 8 and then compared again.

503623 V. Description of the invention-------- = the first clock 12 and the second clock 14. ί 5 It is similar to step 30. This step is also to make corresponding adjustments according to the delay time of φ 枷 f clock 1 14 compared in step 28. In this step, the controller 22 will control the delayer 16 to enable one more delay unit, and increase the delay time of the first day of the day by a delay unit time. Same as step 30, after completing = step, the whole process will be re-transmitted to step 2 8 again, repeat the "ratio adjustment" process, and successively modify the delay time of the second clock 14 to make the second clock 1 4 is synchronized with the first clock 1 2. One: An example will be used to explain the implementation process of the above process. Please refer to Figure 2. FIG. 3 is a waveform diagram of a conventional delay lock circuit, which synchronizes the second clock with the clock of the first clock, the first clock, the second clock, and the second clock. The horizontal axis in Figure 3 is time, and the vertical axis is the magnitude of the waveform amplitude. Because the conventional technique takes a long time to set a delay, the waveforms of the entire correction process of the first clock 2 and the second clock 4 are divided into three parts, so six waveforms can be seen in Figure 3; Waveform 12a is followed by waveform 12b at mark A1, waveform ua is followed by waveform 14b · at mark A2, and waveform 1213 is followed by waveform i2c at B1, waveform Ub is followed by waveform 14c at mark B2, and so on. The combined waveforms 12a, 12b, and 12c at the marked position M are the waveforms of the first clock 12 between time 0 and time 28T. Similarly, the waveforms 1 4 a, 1 4 b, and 1 4 c are completely shown. The waveform of the first clock 14 between time 0 and time 28T. Please refer to the waveforms 12a and 14a in Figure 3. The waveform 12a is the y waveform of the first clock 12 between time 0 and time 10 τ; where T represents the time of the first clock 12-cycle (as indicated by the waveform time interval 12 p). Please note that the delay lock circuit 1 〇

Page 9 ^ UJ623 V. Description of the invention (6) The second clock 1 of step 1 in K it sub-clock, and the -clock-based delay i sleep gate 疋 from the first, delay lock circuit 1 〇 The rr f of the second clock 14 is adjusted, so the period of the waveform is not fixed. The waveform 14a is a waveform of the second clock 14 between time 0 and time 10 T. f When the delay lock circuit 10 starts to operate, the retarder 16 will generate the second clock 1 4 after a certain period of time, i. Corresponding period in. For example, the rising edge of the waveform ^ \ period ^ 2 will trigger the delayer 16 at a certain delay, gf / ih gate & $ Corresponding period 20b in the waveform Ua; period 201a and period theory, i幵; In 12 rounds, the relationship is represented by the arrow 帛 c in Figure 3. At the same time, the period 002a will trigger the period 2 0 2b; 203b ', etc. of the waveform 14a +. Trigger cycle period 2 in the second clock 14 at cycle 203 = 20: Late: the previous 6 generates a week in the second clock according to the trigger of the cycle 201 a "After the zuib, the comparator 24 will be 〆Γ = ' -Γ. Mutual: Delivery time::, 2. When the second clock is closed between the cities, the first 2 is compared with the period 2 0 2a in the first clock. The reference period == ^ period 201a—a period (1T) and a period of 20U. 201b comparative test; ^ comparative pulse corresponds to cycle synchronization. Take the example in Figure 3 to determine whether the pulse and the second clock are Λ. The period 2 in the first clock is 2 〇1 b. 5. The description of the invention (7): The first pulse:: the period 202a, so the comparator 24 will determine the -clock 1 2-". As mentioned earlier, the" delayer 16 will start at the time of the second clock with a period of 2m according to the trigger of the factor n!: N〇la; make it it phase 2 The initial value of the delay time plus the delay time of the delay state itself, like the example in Figure 3, the time difference of f / Λ 2ΐΛ25 (Η indicated by 15a (as indicated by == ΐ: backward relationship, cannot be quantified) Measure the second delay time between the two (the time difference between the rising edge of the two cycles). Pulse 12ίί 24i, compared with the cycle 2202a and the cycle 20b, determine that the second door is delayed by 18, In order to delay the second clock: (it will touch γ to produce a sudden 3;) Late: the test will be started due to the delay ... Cycle 2_ = ': will be 7 1 2: 2: Of course, the comparator 24 compares again Cycles 203a and 202b f (step 28 again), the first clock will be found; ινΛί? 〇) 24rr, m € iii6 # ^^: ^^ Wu 18 (step 30). Next, the retarder 16 will With the first clock 2 The trigger of 03a generates period 203b, and the time difference between these two weeks will be five. Invention description (8) 7 ί 3 ί delay unit and reduce ldt, relatively make period 204a | less id into 2ϋ reference period) and period The time difference between the rising edges between 203b is reduced by S ΐ] 2. The late-lock circuit 10 continuously compares a correction process, and it is gradually reduced: 7 The time difference during the reference period of 2f will also be adjusted in units of 1dt and time interval Udt). As I know, the delay lock circuit 1 () delays the delay time of each cycle in a clock by a certain l · times. As shown in the picture, the time gap between the rising edge of the mountain between the reference cycle 2 has been reduced to: ? I, the time H between the period 220b and the corresponding reference period 2 仏 is known as 6dt. When the time 26T is reached, the period j which the period 226 conceals is 丄 Ό. At this time, the period of the second clock H will be equal to the period f 7 Y. Ting said that after successive corrections, the retarder i 2]-& has the same number, so that the delay time of triggering the 4-unit entry by the rising edge of the first clock cycle is exactly one cycle. For example, the == Timing: The rising edge of the clock cycle triggers the second clock corresponding cycle: 2: 6 at: the unknown system delay In addition, the retarder 16 itself can be used, "inch," because the delay unit 18 makes the first clock and the second clock pair 2 delay time. The delay 16 can not know the system at the beginning. During this period, the number of late units is also the initial guess. Therefore, at this time, the delay pulses used in the 苐 -Rishi mine cannot be synchronized. In the next process, the ^ pulse and the second time | delay lock circuit will repeat 503623. Description of the invention (9) Steps 2 8 and 30 (or 32) to modify the delay time of the corresponding period of the first clock and the second clock successively; finally, the delayer 16 is enabled by the number of delay units 18 The delay time combined with the unknown system delay is exactly one cycle γ of the first clock. The retarder 16 can then be synchronized with the second clock by triggering the second clock cycle based on the first clock cycle. Next, the delay lock circuit 1 Q will still repeat the "compare one correction" process to correct the impact of system interference at any time, but at this time, the retarder 16 will most likely only increase or decrease one or two enabled delays. Correct the interference introduced by the system by a small amount. The disadvantage of the aforementioned driving technology is that it takes a long time to modify the second clock to synchronize it with the first clock. This is because in practice, only one unit of delay time (ie, ldt) can be corrected at a time. In order to make the clock locked to the accuracy of the first clock, the unit delay time must be small enough to avoid quantization err0r. Following the example of figure y3, if the second clock and the first clock correspond to the delay time in the week period, no matter how to correct the 'second clock and the first clock]] it will be because of this 0. fdt's no difference ~ Without full synchronization. Because each time the digital lock circuit corrects the delay time of the second clock, the delay time (the smallest unit of dm correction; less than ""), the time difference (such as 0.5dt) becomes an error that cannot be completely corrected. In other words, the time of a unit delay time dt, the magnitude of the quantization error. The length can be used to balance 503623. V. Description of the invention (ίο) In order to reduce the quantization error, a digital delay lock such as a delay lock circuit is designed. When the circuit is used, the unit delay time dt will be minimized. For example, if the time of the period τ of the first clock in FIG. 3 is equivalent to 100 dt (that is, ldt = T / 100), then the first clock and If the second clock is not completely synchronized, the error will be less than one hundredth of a cycle. If a unit delay time dtlis is as small as one thousandth to a period τ, then the quantization error will be further reduced to one thousandth Cycle, but the reduction of the unit delay time will increase the process of correcting the second clock delay time. From Figure 3, it can be seen that when the conventional technique is used to modify the second clock delay time, every week The period T can only correct (increase or decrease) the error of a unit time. The smaller the unit time, the smaller the amount of correction delay time in each period of T; relatively, the more time it takes to complete the entire correction process Long (in other words, it takes more cycles T to correct the second clock to synchronize with the first clock). When

However, in the modern lean industry, not only does the quantization error of the delay lock circuit need to be small (to accurately phase lock), but also the delay lock circuit can quickly synchronize the second clock lock to the first clock to improve Information processing efficiency. Summary of the Invention: Therefore, the main purpose of the present invention is to provide a method for delay locking and related circuits, which can speed up the delay lock without increasing the secret error without increasing the secretion error.疋 之 〇 Yun to solve the shortcomings of conventional technology.

Page 14 503623 V. Description of the invention (π) Detailed description of the invention Please block diagram. It buffers several delays dt. The control is similar to delaying the clock 60 plus one clock 64 to send a data reception. Refer to Figure 4. Fig. 4 shows that the delay lock circuit 50 of the present invention has a delay device 60, a comparator 64 and a control delay unit 58, and each delay unit controller 62 has a register 65. The delay lock circuit 50 of the present invention also benefits 56 to generate a second clock 56. The current driving ability is enhanced and the buffer 52 is synchronized with the second clock 54. At two times, it is compared whether the two clocks are synchronized. The corresponding comparison signal is output to the control comparison signal to control the second pulse 5 4 of the retarder, so that it can be locked with the first delay 5 6,-the electric 62 2. The extension of bow I and the extension of knowledge is based on a second clock device 60 which outputs pulses to device 64 and device 4 2. Control 5 6 in order to adjust the function of clock 52 and 50 0 in the same way. Connected to the delay unit 5 6 delay unit 56 has a delay unit time delay lock circuit 1 0 the first clock 5 2, 5 6 will be buffered. In order to make the first feedback to the comparator, according to the comparison result, the controller 62 can follow the steps of the delayer 56.

I wait, ΐ: "Passed delay lock circuit-when it starts to operate, the second pulse generated by the state cannot be synchronized with the first clock. The user knows that the delay lock circuit must be corrected by one unit at a time. T of the delay time: The delay time of the second clock is modified one by one. In order to reduce the time required for the above repair process, the delay lock circuit of the present invention starts an initial phase lock procedure first. The fast program synchronizes the second clock two two tf with the first clock. Please refer to Figure 5. Figure 5 is the flow chart of the initial phase lock procedure of the present invention. The initial phase lock procedure has the following steps

503623 V. Description of the invention (12) Step: Step 66 ·· Start the initial phase lock procedure. When the mad and beautiful office as s ^ work, the delayer 56 according to the 4th = J electric predicate, ... The second clock 54 generated by the bang pulse 52 is not yet synchronized, and the initial phase lock procedure can be started at this time. Step 68: Set a correction time interval d t to a 4 u ^ ^ and perform the correction procedure 71. The value is an initial value. Next, the calibration procedure 7 1 ·· The calibration procedure 7 1 has the following steps: Step 7 0: First use the delay device 5 6 to generate the correspondence according to the predetermined delay time. Compared with the second clock 54 and the second clock 54, the delay time of Guan Cheng is the same as the delay time. If it is the first time, go to Step 7 2 Β Step 7 2 A: Put the first time. In other words In the clock cycle, the lake and the corresponding second ί 5 3 Ϊ f, ί △ delay unit 56 enabled by the delay unit ^ M ⑽ avoidance by a correction time interval Dt in the delay benefit 5 6 according to In the first clock cycle, a few delay units 58 will be enabled, so that the delay time during the first clock cycle ig — I., the time 1 of the Yi Zhou can be increased for each delay unit 58 — the time interval Dt will be reduced by one. When correcting the time interval Dt, the number of delays required to be 58 is (Dt / dt). The delayed single step 72B that is enabled: contrary to the purpose of step m, the delay time of this step is increased by the time of the correction time Dt. Also = B generates the second clock according to the first clock cycle according to the first clock cycle. When the clock cycle is delayed, there will be 503623 more conditions. The decision is whether or not to check the calibration process recursively during the calibration, and it will meet the information that meets the timing interval Dt. If the value is set, the end condition is exemplified. Once the end condition ends the entire initial phase lock, it returns to step 70. 56, increase the time between the first clock cycle and the corresponding second clock by a correction time interval Dt. To increase the _ 1 delay 56 additional delay (Dt / dt) delay and time interval Dt value, so that It becomes half of the original. The information (such as the length of the correction time Dt or the number of crossovers) will also be updated at the same time and stored in the control ^ V. Description of the invention (13) Enable several delay unit cycles. The delay time is the time from the time Dt, unit 58. Step 7 4: Update the register 65 in the time interval Dt in which the correction time Dt is updated. Step 7 6: Implementation with an end condition One example is when the correction time interval Dt will be shortened to a certain degree. The number of relevant calibrations in the register 65 has exceeded one. What is the implementation step 78 above (that is, if the requirements are not met, 7? ^ Satisfying the end of the phase lock program will also end the end of the school Program. The length of time from the end to Dt. Therefore, it is shortened, and the correction time is seven pieces. In addition, you can also check if the correction time Dt is updated and satisfied. No matter the end bar is satisfied, continue to the program). Conversely, Surname process again

After the conditions, the correction procedure 71 stops, and the entire initial Q is referred to FIG. 6: Steps to explain the process of the initial phase-locking procedure in the present invention. Please refer to FIG. 5 and FIG. 1 and L for the initial phase-locking procedure in the present invention. Timing chart of the waveform of the first clock ^ /, one clock 54. The horizontal axis of Figure 6 is time

Page 17 503623 V. Description of the invention (14) »The axis is the magnitude of the waveform amplitude. For the sake of clarity, the waveform of the first clock 5 2 and the clock 54 are each divided into two parts. The skin shape 52a is the waveform of the first pulse, 5 time 0T to 9T; the waveform 52b is the first Waveform of clock 52 between time = 0T and time 15T (please note that for complete technical disclosure, waveform 52a and waveform 52b have partial periodic waveform repetitions). The waveform 52a and the waveform 52b are connected at the mark A1, which is the complete waveform of the first clock 52 from time τ to time / 15T. Similarly, the connection of the waveform 54a and the waveform 54b at the mark A2 is the complete waveform of the second clock 54 between time 0τ to time} 5τ. Similar to the case of the conventional technology, the present invention also uses the trigger of the first clock to generate the second clock; the period of the first clock 52 is fixed to τ, as indicated by the time interval 52ρ; b does not. The delay time of the second clock 54 is changed by the controller 62 to control the delay 56 so that the period of the second clock 54 is changed.

々 When the delay lock circuit 50 of the present invention starts to operate, the retarder 56 will trigger on the rising edge of the period 301a (please refer to waveform 52a) in the first clock, and after a certain time delay, it will generate the signal in the second clock. Corresponding period j01b = The corresponding relationship between the period jOla and the period 301b is represented by the header ^ in FIG. Similar to the situation in the conventional technology, the time difference (ie, the delay time) between the rising edge of the period 3 0a and the period 301b will include unknown, secondary delay, and the delay unit 5 8 which is initially activated. The number I i ί affects two factors. Please note that in order to compare with the positive process of the conventional technique in FIG. 3, the delay time between the periods 30a and 30 lb in FIG. 6: Are the same (that is, the conditions before the correction in Figure 3 and Figure 6 are the same); and

Page 18 503623 V. Outline of Invention (⑸) — The length of the delay unit time of a delay unit 58 in FIG. 6 is also the same as the length of the delay unit time dt in FIG. 3. The first clock is one cycle in FIG. The time T is also the same as the length of the first clock in the third cycle in Figure 3. The length of the cycle is the same. ^ In the figure (dt is a first clock 5 2 lags behind and the sixth step in the second fifth starts the initial lock delay unit. 58 and the second clock collar period 3 0 1 a two clocks 5 4 middle and week 7 0). According to the chart time leading reference, the second clock 15dt leads the first clock 6 2. The reason is that The post-cycle 3 0 1 a is equal to the other cycles I in the first clock 52 of the two-equal cycle 3 0 1 b. Compared with the conventional delay-locked electrical clock, the cycle and the first time do not quantify the delay phase program between each other The back branch timing D t is set to 3 2 dt unit delay time). When the comparator 64 compares the first / lagging relationship, the period 3 0 3 a of the first clock cycle is used as a reference period, and the period 3 0 1 a corresponds to the period 3 〇 丨 b comparison (that is, the It can be seen that the period 301b is the period 303a; so the comparator 64 judges and sends the corresponding comparison signal to the controller for the period f period 303a as a reference period, and the state is stable. Bran, aa 1 β & Tian is also visible In the case, “玖 二 蛑, multi-test period” is used to approximate period 3 01 b to rff. Comparator 64 only compares the length of the leading / lagging period of the test period j: controller 6 2 is connected to comparator 6 After the second clock 56 is generated next week, the 4th device 56 will control the delay and update the value of the correction time interval; especially = the time interval of the day of the day_65 is related to the length of the correction time interval Dt Same: Change register buffer (the above is step 723 and 74 503623 V. Description of the invention (16)). · In this embodiment, the end condition is the ldt of the calibration time interval; therefore, the calibration procedure will return to step 7 〇, " In the next process, the delay of crying period of 3 0 3 a respectfully stands up The late state 5 6 will disappear with the younger one in the clock 5 2 and the loss will disappear as 1 r, ... ~ w I delay the day f 3 2 dt, so the original extension fi P1 ° only-f two clock cycle , It will be behind the reference period by 17dt because of an additional delay time of 32dt. Out, it corresponds to the period of 3 003 a and the period of 3 0 3 b, which is behind the age of the old ^ fine ancient by 17 dt. Comparator 64 compares week by week. " 3 0 53 will judge that the second clock 54 is behind the _ clock 52. After one cycle 3 0 5a 'From the flowchart in Figure 5, we can see that the cycle 30 5a in 52 generates 16 delay units 58 to reduce The time between the correction time Dt, the time Dt is already the previous correction program, the original program was originally 32dt, the correction time is reduced by 16 dt, and the second 17dt delay time will be reduced to the period 305a of the period 305a, and the second time It is 1 dt. 9 Tian delayer 5 6 uses the first clock again. At period 30 5b, the delayer 56 will lessen the delay time of the period corresponding to the ^ clock minus 16 dt. Please note that when correcting at this time ^ Corrected the half of the time interval Dt; in the previous school, the distance has now become 16dt. The original period of the delay pulse and the reference period The idt. Seen from FIG six, corresponding to the delay between the periphery 30 7a with reference to a clock cycle delay when the periodic trigger 56 to generate a second clock once again 3〇7a state

503623

At the corresponding period of 307b, because of the delay time, 307b leads you again by 7dt, and the second time is 8 二, which reduces the cycle time again-the correction time interval (At this time, the test 2 is returned with the correction program 71, when Delayed crying triggers the corresponding period of 309b in the second clock 54; please be in touch, open the second 5410, the period 309b will increase by two (one school / μ interval) due to the delay time, and the reference period The delay time of class 309 will be closer to 12. The delay time of cycle 311a and cycle 311b will increase again.

Time), the period 311b and the corresponding reference period Wa are raised by d: Ϊ "to 1". Finally, the corresponding cycle ΪΓΡί is generated with the cycle 313a, and the time interval will be further reduced to ldt, so that the time difference between the cycle 313b and the corresponding reference cycle 31 5a is reduced to zero, and the first clock and the second clock can be synchronized. Please note that the calibration procedure and the entire initial phase-locking procedure will also end at this time, because the next calibration interval is less than 1 dt and the end condition is met. After the initial phase-locking process is completed, the delay time caused by the delay unit 5 8 enabled by the delay unit 5 6 plus the system delay time, the sum of which is an integer multiple of the period T (as shown in the example in Figure 6 is 2 T ). Next, the delay lock circuit 50 of the present invention will continue to trigger the generation of the corresponding period in the second day pulse with the rising edge of each first clock cycle (please note that in the initial phase lock program, the delay lock circuit 50 Only two periods τ will trigger a period in the second clock), because the delay time of the retarder 56 has been adjusted to an integer of the period τ

Page 21 503623 V. Description of the invention (18) times, the second clock 54 is also synchronized with the first clock 52. Demystifying will still continue to operate, so that the controller 62 can correct the delay time error caused by ^ ^ ^; and this error usually requires only a small amount of ^ Summary Initial phase-locking process Figure 7 shows the initial stage of the invention. In addition to the successive correction of the delay time E3, the cycles from the top to the bottom are the cycles 301b, 303b, and the waveform. Period E 1 shows the time of the edge; period E 2 is the shape of E 3 and the first clock 3 is 30 lb. Period E 1 is the period 3 0 3 a. The analogy is the rising edge of the cycle 3 0 3a. Finally, for the cycle 3 1 3 b, the cycle 3 1 3 a, and the cycle e 2 is a process in which the correction time interval Dt is sequentially corrected with the correction of one clock and the second clock. For further reference, refer to Figure 7. In the initial phase lock procedure, each cycle in the second clock 54 is not intended. The horizontal axis of Figure 7 is time; except for the wave train, each cycle in the second clock 54 (30 7b, 3 0 9b, 3m, and 31; the first clock cycle that triggers each of the above cycles rises to each of the above cycles). Corresponds to the time of the reference period; wave, the waveform of the period. In other words, for the period is the period 301a, and the period E2 is the corresponding reference. For the period 3 0 3b, the rising edge of the period E1 is the rising edge of the period E2. It is the rising edge of cycle 3053. The cycle E1 will correspond to the trigger cycle 3l3b and the reference cycle 315a. As can be clearly seen in Figure 7, the progress of the program is reduced one by one; and finally, the technology can finally be synchronized. The process of correcting the delay time in Figure 3. This process of the same Tuesday and # (the same initial condition and the same unit delay time di. JT) is used to perform the initial phase lock procedure and lock the delay (shown in the side

503623 V. Description of the invention (19) Figure 6) Obviously fast one and the second to the same start will be discussed with the timing of the program at the same time, which is the same (that is, the process of _ quantization error > Not only in Figure 6 will increase the quantization error, it must be bad. For the example that can accelerate the lock, the time phase program that is delayed by one unit can be successively shortened. Initially, the delay will increase the distance by half the difference. It will not be able to achieve the first time, the first time to reduce the timing and effect of phase-locking skills in the school. Larger fine-practice units with delayed skills will have to delay the growth of orders. Time technology has to be stepped. This is due to the fine tuning between corrections. In the operation, the time delay is delayed. The invention is based on the method of 26 cycles (26T) of dt. As long as 14τ is in the invention, Initially adjust the delay time by adjusting the I time interval, so that not only will not increase the quantization error. Each time you modify the delay time by 1 dt), if you want to speed up the lock time; but in this way, the dichotomy is successively performed. During the correction, the quantization error will not be increased in the initial phase-locking program, and the delay time will be modified. A more quantitative threshold will also highlight the strictness of the present invention. ^ Comparing the conventional technology with the technology of the present invention, The abundance of time tf ^ 彳 t Assume that a unit delay time is one cycle =: one-fourth-(that is, 1 ... mm), then the conventional technique is delayed pU: ϊ 1 i cycle time to correct the second clock Delay = It is synchronized with the -clock. In contrast, in the present invention, 'since the i = T g knife method successively changes the magnitude of the adjustment delay time, it only takes about 10 out of 10 logarithmic values.] Jingyou can complete the initial phase-locking procedure 时 r and 苐The process of clock synchronization. If a unit delay time _ is reduced to 2048 minutes of a cycle time n, then

Page 23 503623

V. Description of the invention (20) ldt = T / 2048), the conventional technique will take about 10 24 cycles to synchronize the second clock with the first clock; in the same case, the bisection method is used. The invention only needs 11 cycles (the logarithm of 2048 to 2) to complete the initial phase-locking procedure, and it will not increase the quantization error. In summary: the invention can significantly accelerate the lock delay process without increasing the quantization error; it can not only ensure the accuracy of the phase lock of the digital delay phase lock circuit, but also improve the efficiency and reduce the waste of lock Phase process repeated correction = time. Because the initial phase-locking procedure in the present invention will calculate the value of the new time interval in each correction process, the delay lock circuit 5 in the present invention will store the information about the time interval of the correction and judge it accordingly If the calibration process f is no, the process ends. Since the present invention uses a dichotomy to control the correction time interval = reduction (that is, each time the correction time interval is reduced to one-half of the original), ^ directly uses the binary method to temporarily store the information about the correction time interval. ^ j For example, at the beginning of the correction time interval Dt = 32dt, can be recorded in the "quot :: bits (Μί) as 〇〇〇〇〇〇; the correction time interval Dt is halved and after 8dt The value of the register 65 can be recorded as 1000 00. The correction time interval Dt becomes 4dt ^ t spring: when 11110 π is 1 1100 and the weighted time interval is 2dt, the value of the register 65 becomes halved, and the value of the register time Dt is halved to the value of the register 65. The time calibration procedure will also end. In this way, the initial phase lock in the present invention can be managed by the register 65

503623 V. Description of the invention (21) The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. For example, the order in which several steps (steps 70, 74, 76, etc.) of the calibration program 71 in the present invention can be executed interchangeably after being reasonably modified should all belong to the equal change of the present invention.

Page 25 503623 Brief description of the diagram Brief description of the diagram: Figure 1 is a functional block diagram of a conventional delay lock circuit. FIG. 2 is a flowchart of a method for the delay lock circuit of FIG. 1. FIG. Figure 3 is a timing diagram of the first clock and the second clock waveforms of the delay lock circuit in Figure 1. FIG. 4 is a functional block diagram of the delay lock circuit of the present invention. FIG. 5 is a flowchart of a method for the delay lock circuit in FIG. 4. Figure 6 is a timing diagram of the first clock and second clock waveforms of the delay lock circuit in Figure 4. FIG. 7 is a schematic diagram of a modified delay time of the method of the present invention. Explanation of the symbols in the figure: 50 the delay lock circuit 52 of the present invention 52 the first clock 54 the second clock 56 the delay device 58 the delay unit 60 the buffer 62 the controller 64 the comparator 65 the temporary register 71 the calibration program C arrow A and A2 Mark T period dt Unit delay time 52a, 52b, 54a, 54b, E3 waveform 6 6 ^ 68, 70, 72A, 72B, 74, 76 ~ 78 Step How

Page 26 503623 Schematic description 301a 313a 3 0 9b 303a, 305a, 307a, 309a, 311a 315a, 301b, 303b, 305b, 307b 311b, 313b, E2 cycle

Page 27

Claims (1)

503623 6. Scope of patent application 1. A delay lock method for generating a corresponding second clock based on a first clock and synchronizing the first clock with the second clock; The method includes: performing a correction sequence; which increases or decreases a correction time interval between the first clock and the second clock during a corresponding week (i η ΐ erva 1); wherein the correction The time interval is close to that of the previous correction procedure—jji. 〇2. As for the method in the first scope of the patent application, the correction procedure further includes: comparing the first clock with the second time Whether the period corresponding to the clock is synchronized and a comparison result is obtained; wherein when the delay time of the period corresponding to the first clock and the period corresponding to the second clock is increased or decreased by the correction time interval, it is determined according to the comparison result Whether to increase or decrease the correction interval. n 3. The method according to item 2 of the scope of patent application, wherein when comparing whether the first clock and the corresponding second clock period are synchronized, a period in the second clock is compared with the first clock Time gap during S1 corresponding reference week. 4. For the method of applying for item 1 of the patent scope, it also includes: Page 28 503623 VI. Patent application scope Before the calibration procedure is performed, the calibration time interval is set to a preset initial value. 5. If the method of claim 1 is applied to a delay lock circuit, the delay lock circuit includes: a delayer for delaying the second clock to change the second clock and the first clock The delay time during the period corresponding to one clock; m Where the delay time between the first clock and the second clock corresponding to the second program is increased or decreased by the correction interval The delayer delays the second clock to change the delay time of the second clock corresponding to the first clock. 6. The method according to item 5 of the patent application, wherein the delayer includes a plurality of delay units, and each delay unit is used to increase the delay time of a period corresponding to the first clock and the second clock by a fixed amount. Delay unit time. 7. The method of claim 5 in the patent application, wherein the delay lock circuit further includes a comparator electrically connected to the delay device to compare whether the first clock period is synchronized with the second clock period and A corresponding comparison result is generated; when the delay time of the corresponding period of the first clock and the second clock is increased or decreased in the correction program, the correction time interval is determined based on the comparison result. Or reduce the correction interval. 8. The method of claim 7 in which the comparator is compared Page 29 503623 6. The scope of the patent application. The time difference between a period in the second clock and a corresponding reference period in the first clock to produce the comparison result; and the first clock and the second clock The period corresponding to the period in the clock is a predetermined reference time ahead of the reference period. 9. For the method according to item 5 of the patent application, wherein the delay lock circuit further includes a temporary register for temporarily storing information corresponding to the corrected time interval. 10. If the method of the first item of the scope of patent application, it also includes ... If the correction time interval is less than a preset fixed value, then the correction process is not performed. 1 1. A delay-locked pulse according to the first clock, the same comparator as the second clock, whether the period is synchronized, a delay, changing the second clock and a controller, wherein the control number controls the The delay time is increased by a delay circuit (DLL, Delay Lock Loop), which is used to generate a corresponding number and make the first clock step. The delay lock circuit includes: used to compare the first clock with the first clock. The second clock corresponds to the cycle and generates a corresponding comparison signal; it is electrically connected to the comparator to delay the second clock to delay time corresponding to the period of the first clock; to control the delay lock circuit The device can perform a correction process to reduce the correction time interval (interva 1) during the period corresponding to the first clock and the second clock according to the comparison signal; Page 30 503623 VI. The scope of patent application where the calibration time interval is half of the calibration time interval in the previous calibration procedure. 0 Delay time delay. The first and the last should be delayed. For each item, 1X 1 Yuan and 1st Fan Fan Yanli will have to reapply as follows: • Including the fixation of the delay of 1 package, 1 plus the delay time of the delay time, and the response time of the delay time. The time between the first time and the single pulse is late, and the school should be corrected at that time. The road should be delayed for the lock on the recording. Such as electricity. Dingxun 3 The lock-up should be compared with the reference, the middle one should be locked when the pulse of the road is delayed, and the period should be delayed. The first one is the middle one, and the second one should be compared. • Department 4-The first week of the first week of the first period of the fixed pulse in the I device. • This number should be compared with the weekly births of the period. The time of the second week of the second week of the test should be the same as that of the 5 o'clock time. Positive lock calibration should be delayed. If the control is controlled, the electrical appliance custom lock control should be delayed. The value of the item. 1 Sequencing, first course, enclosing, normal pre-calibration, profit one should be dedicated, please enter small, Shen already road, such as distance from electricity Page 31