503584 A7 __B7 —_____ 五、發明說明（/ ) [技術領域] 本發明係關於一種薄膜電晶體及使用該電晶體之液晶 '顯示裝置及電致發光顯示裝置。 [背景技術] 做爲以往之薄膜電晶體，例如可舉出在液晶顯示裝置 所不斷進行開發之低溫多晶矽薄膜電晶體(以下稱爲「低溫 Poly-SiTFT」）。以下參照圖式來說明該低溫P〇ly-SiTFT。 使用多晶矽薄膜電晶體之大型液晶顯示裝置，由於需 要取得大面積多使用便宜之玻璃基板。惟，將玻璃基板當 作基板來使用的情況下，由於其耐熱性並不充分，故不得 不於較低溫(大約600°C以下)來製作薄膜電晶體。 圖11係顯示習知之低溫Poly-SiTFT之製造方法之製 程別截面圖。 在以往之低溫Poly-SiTFT之製造方法中，首先在玻璃 基板11之表面設置有用以防止玻璃基板11中之雜質擴散 之矽氧化膜所構成之底塗絕緣膜12(40〇nm左右)之基板上 ，以矽烷(SiH4)爲原料氣體而利用等離子體CVD法來形成 厚度50nm之非結晶矽膜13(圖11(a))。其次，照射xeci 準分子雷射15讓非結晶砂膜13結晶化而形成多晶政所構 成之半導體膜14。此時之照射條件雖取決於半導體膜14 之膜厚與膜材質等之條件，惟在能量密度150〜450mJ · cm· 2、照射次數1〜500次之範圍來進行。將該半導體膜14以 眾知之光微影及蝕刻來圖案化成爲島狀(第11圖(b))。其次 ，藉由等離子體CVD法在島狀之半導體膜14上形成厚度 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ·' 圈 ----------------------訂-------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ..______B7________ 五、發明說明（2 ) 90nm之閘極絕緣膜16。接著’採用鉬與鎢之合金MoW來 形成閘極31，將閘極絕緣膜16與閘極31以眾知之光微影 及蝕刻來圖案化成爲島狀。接著，以閘極31爲光罩，產生 氫稀釋膦PH3之等離子體，以加速電壓70kV、劑量1 X 1015cm·2的條件進行離子摻雜，以形成源極區域32與汲極 區域33(第11圖（c))。其次，進行熱處理，讓注入之離子 活性化。接著，藉等離子體CVD法於全面堆積二氧化矽 (Si02)作爲層間絕緣膜34 ’之後，形成接觸孔之後，以塡 埋該接觸孔的方式以濺鍍法來堆積例如鋁(A1)。其次，以 光微影與蝕刻將該鋁(A1)膜圖案化，以形成源極35與汲極 36。藉此，乃完成薄膜電晶體401(第11圖(d))。 惟，以上述方式所製作之以往的低溫Poly-SiTFT，有 接通電流低的課題存在。 [發明之揭示] 本發明係用以解決上述課題所得者，其目的在於提供 一種可提升接通電流之薄膜電晶體。 是以，本發明者首先著手於瞭解電流之所以低的原因 。其結果發現其原因係如以下所闡明般。 亦即，於低溫Poly-SiTFT之製程中，一旦將玻璃基板 上所形成之作爲底膜的非結晶矽膜以雷射加以結晶化，則 於其結晶化之際所產生之溫度梯度會在成爲完成膜之多晶 矽膜中產生lOOOMPa以上的拉伸性應力。該拉伸性應力會 對於多晶矽膜之晶格造成應變，於是在該多晶矽膜中發生 缺陷。於是，該缺陷會捕捉在源極區域與汲極區域之間移 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ___Β7_______ 五、發明說明（）） 動之電子，因此薄膜電晶體之遷移度會降低，其結果，Id 一Vg特性的變動會放緩’從而接通電流會下降。 是以，由上述之闡明結果可知，爲了提昇接通電流， 對拉伸性之多晶矽膜施加壓縮力爲有效的做法。具體而言 ，對包圍多晶矽膜之外圍膜賦予拉伸性之內部應力或晶格 應變，可對多晶矽膜施加壓縮力，其結果，多晶矽膜中之 缺陷會減少，薄膜電晶體之遷移度會提升。也因此，Id — Vg特性的變動會顯著，.從而接通電流會上升。 是以，有關本發明之薄膜電晶體，係具備··基板、底 塗絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣 膜上分別形成之源極區域、通道區域、汲極區域，以矽爲 主成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接） 、以及膜狀之閘極（與該閘極絕緣膜鄰接）；其中，上述閘 極與上述閘極絕緣膜之各內部應力的和爲拉伸性。依據該 構成，由於可藉由與半導體膜鄰接之閘極絕緣膜以及閜極 之拉伸性的內部應力來對半導體膜施加壓縮力，將可提升 接通電流。 此時，上述閘極之晶格應變亦可爲拉伸性。依據該構 成，可進一步提升接通電流。 此時，上述閘極之晶格應變的絕對値亦可在 0·1%〜0.4%。依據該構成，可適切地提升接通電流。 又，有關本發明之薄膜電晶體，係具備：基板、底塗 絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣膜 上分別形成之源極區域、通道區域、汲極區域，以矽爲主 5 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公爱)" ' ~ (諝先閱讀背面之注意事項再填寫本頁) -----—訂 ---------線- 503584 A7 _ B7______ 五、發明說明（0 ) 成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接）、 以及膜狀之閘極（與該閘極絕緣膜鄰接）；其特徵在於，上 述閘極絕緣膜之內部應力爲拉伸性。依據該構成，由於可 藉由與半導體膜鄰接之閘極絕緣辉的內部應力來對半導體 膜施加壓縮力，將可提升接通電流。 此時，上述閘極絕緣膜之內部應力的絕對値亦可在 lOMPa〜400 MPa。依據該構成，可適切地提升接通電流。 又，有關本發明之薄膜電晶體，係具備：基板、底塗 絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣膜 上分別形成之源極區域、通道區域、汲極區域，以矽爲主 成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接）、 以及膜狀之閘極（與該閘極絕緣膜鄰接）；其特徵在於，上 述底塗絕緣膜與上述閘極絕緣膜之各內部應力的和爲拉伸 性。依據該構成，由於可藉由與半導體膜鄰接之閘極絕緣 膜以及底塗絕緣膜的內部應力來對半導體膜施加壓縮力， 將可提升接通電流。 此時，可讓上述底塗絕緣膜與閘極絕緣膜之各內部應 力分別爲拉伸性。依據該構成，可進一步提升接通電流。 此時，上述底塗絕緣膜之內部應力的絕對値亦可在 lOMPa〜400 MPa。依據該構成，可適切地提升接通電流。 又，有關本發明之薄膜電晶體，係具備：基板、底塗 絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣膜 上分別形成之源極區域、通道區域、汲極區域，以矽爲主 成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接）、 6 本紙張尺度適用中國國家標準（CNS)A4規格（謂χ 297公爱） ' --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 __ B7 ___ 五、發明說明（f ) 以及膜狀之閘極（與該閘極絕緣膜鄰接）；其特徵在於，上 述半導體膜之上述源極區域與上述汲極區域之晶格間距離 較上述通道區域之晶格間距離爲長。依據該構成，由於對 半導體膜藉由閘極來施加壓縮力，將可提升接通電流。 此時，上述閘極之晶格應變亦可爲拉伸性。依據該構 成，可進一步提升接通電流。 此時，上述閘極之晶格應變的絕對値可在0.1%〜0.4% 。依據該構成，可適切地提升接通電流。 又，有關本發明之薄膜電晶體，係具備：基板、底塗 絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣膜 上分別形成之源極區域、通道區域、汲極區域，以矽爲主 成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接）、 以及膜狀之閘極（與該閘極絕緣膜鄰接）；其特徵在於，上 述底塗絕緣膜、上述閘極、以及上述閘極絕緣膜之各內部 應力的和爲拉伸性。依據該構成，由於可藉由包圍半導體 膜的底塗絕緣膜、閘極以及閘極絕緣膜的內部應力來對半 導體膜施加壓縮力，將可提升接通電流。 又，有關本發明之薄膜電晶體，係具備：基板、底塗 絕緣膜(形成於該基板上）、半導體膜(具有在該底塗絕緣膜 上分別形成之源極區域、通道區域、汲極區域，以矽爲主 成分）、閘極絕緣膜(與該半導體膜之上述通道區域鄰接）、 膜狀之閘極(與該閘極絕緣膜鄰接）、以及層間絕緣膜(係以 將形成有上述底塗絕緣膜、上述半導體膜、上述閘極絕緣 膜、以及上述閘極之上述基板的表面加以覆蓋的方式所形 7 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐) ~ ------------·--------^---------線.φ. (請先閱讀背面之注意事項再填寫本頁) 503584 A7 __B7___ 五、發明說明（6 ) 成者）；其特徵在於，上述層間絕緣膜之內部應力爲拉伸性 。依據該構成，由於可藉由層間絕緣膜的內部應力來對半 導體膜施加壓縮力，將可提升接通電流。 此時，上述層間絕緣膜之內部應力的絕對値可在 lOMPa〜400 MPa。依據該構成，可適切地提升接通電流。 又，在上述之情況中，上述半導體膜係由雩射光所照 射過之結晶化的多晶矽所構成，連結上述源極區域與汲極 區域之方向係與上述雷射光之掃描方向大致一致也爲可行 的方法。對於多晶矽來說，由於結晶化用雷射光之掃描方 向相較於與該掃描方向呈垂直之方向產生較大之拉伸性內 部應力，所以依據該構成，該內部應力可藉由包圍半導體 膜之膜的內部應力來有效地加以抵銷，而可有效地提升接 通電流。 又，上述薄膜電晶體可爲一於上述底塗絕緣膜上依序 積層上述半導體膜、上述閘極絕緣膜、以及上述閘極所構 成之頂閘型電晶體。 又，上述薄膜電晶體可爲一於上述底塗絕緣膜上依序 積層上述閘極、上述閘極絕緣膜、以及上述半導體膜所構 成之底閘型電晶體。 又，有關本發明之液晶顯示裝置，係一邊對構成顯示 畫面之複數的畫素依序掃描一邊將畫像訊號寫入該掃描過 之畫素中，藉此來變化液晶面板之透過率，從而對應於上 述畫像訊號之畫像在上述顯示畫面進行顯示；其特徵在於 ，用以進行上述畫素之掃描狀態與非掃描狀態之切換的切 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------------—訂---------線"4^ (請先閱讀背面之注意事項再填寫本頁) 503584 A7 五、發明說明（7) 換元件係由申請專利範圍第1、4、6、9、12、13項中任一 項之薄膜電晶體所構成。依據該構成，由於薄膜電晶體之 接通電流得以提升，用以接通切換元件之閘極控制電壓以 低電壓即可，乃可減低切換元件之驅動電路的消耗電力、 甚至可減低液晶顯示裝置之消耗電力。 又’有關本發明之電致發光顯示裝置，係一邊對構成 顯示畫面之複數的畫素依序掃描一邊對該掃描過之畫素供 給對應畫像訊號之電流，藉此來讓電致發光單元發光，從 而讓對應於上述畫像訊號之畫像在上述顯示畫面進行顯示 ;其特徵在於，用以進行上述畫素之掃描狀態與非掃描狀 態之切換的切換元件以及用以供給上述對應畫像訊號之電 流的電晶體之至少一者係由申請專利範圍第1、4、6、9、 12 ' 13項中任一項之薄膜電晶體所構成。依據該構成，由 &_膜電晶體之接通電流得以提升，用以接通切換元件之 聞極控制電壓以低電壓即可，乃可減低切換元件之驅動電 路的消耗電力、甚至可減低液晶顯示裝置之消耗電力。 本發明之上述目的、其他目的、特徵以及優點，可參 照以下所附加之圖式，由以下之適宜的實施態樣之詳細說 明獲得彰顯。 [圖式之簡單說明] 第1圖所示係與本發朋之實施形態1相關之薄膜電晶 體的構成截面圖。 第2圖所示係第i圖之薄膜電晶體之製造方法之製程 別截面®。 __ 9 本氏張政用中國國家標準（CNS)A4規格（210 X 297公楚） ---I---------------—訂---------i^w— (請先閱讀背面之注意事項再填寫本頁) 503584 A7 _B7___ 五、發明說明（公） 第3圖所示係薄膜電晶體之遷移度與閘極之晶格應變 的關係圖。 第4圖所示係薄膜電晶體之遷移度與閘極絕緣膜之內 部應力的關係圖。 第5圖所示係薄膜電晶體之遷移度與底塗絕緣膜之內 部應力的關係圖。 第6圖所示係薄膜電晶體之遷移度與層間絕緣膜之內 部應力的關係圖。 第7圖所示係與本發明之實施形態2相關之液晶顯示 裝置之構成方塊圖。 第8圖所示係第7圖之液晶顯示裝置之構造的部分截 面圖。 第9圖所示係與本發明之實施形態3相關之電致發光 顯示裝置之構成方塊圖。 第10圖所示係第9圖之電致發光顯示裝置之構造的部 分截面圖。 第11圖所示係習知之薄膜電晶體之製造方法的製程別 截面圖。 [用以實施發明之最佳形態] 以下，針對本發明之實施形態，參照圖式來說明。 實施形態1 第1圖所示係與本發明之實施形態1相關之薄膜電晶 體的構成截面圖。 如第1圖所示，薄膜電晶體1具備：基板11、底塗絕 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） K n n n n In m It n n n d · n n 11 ·1 n n —i 一 ot fl (K n n n n n n I (請先閱讀背面之注意事項再填寫本頁) 503584 A7 五、發明說明（？） 緣膜12(形成於該基板11上）、半導體膜14(形成於該底塗 絕緣膜之表面的既定區域）、源極區域32與汲極區域33(在 該半導體膜14中以既定之間隔分別形成）、低雜質區域 37,37(Lightly Doped Drain Region :以下稱爲 LDD 區域)( 在源極區域32與汲極區域33之間分別與之相接而個別形 成）、通道區域61(夾在上述兩個LDD區域37,37之間）、 閘極絕緣膜16(被覆於底塗絕緣膜12之形成有半導體膜14 之表面）、膜狀之閘極31(形成於閘極絕緣膜16表面之位於 上述通道區域61之上方.的部分）、層間絕緣膜34(係被覆形 成有閘極31之閘極絕緣膜16的表面）、以及源極35與汲 極36(係以分別自上述半導體膜14之源極區域32、汲極區 域33貫通閘極絕緣膜16、層間絕緣膜34而延伸到該層間 絕緣膜34之表面的方式所分別形成）。 基板11係由例如道可寧古公司製造之可寧古#1737等 之玻璃基板所構成。底塗絕緣膜12係用以防止雜質之擴散 ，例如由氧化矽所構成。半導體膜14在此係由多晶矽所構 成。源極區域32與汲極區域33皆由多晶矽當中之N型雜 質之高濃度區域所構成，又，LDD區域37也同樣由N型 雜質之低濃度區域所構成。通道區域61係由半導體膜14 之基材的多晶矽所構成。閘極31係由例如鉬與鎢之合金 MoW所構成。層間絕緣膜34係由例如二氧化矽(Si〇2)所構 成。源極35以及汲極36係由例如鋁(A1)所構成。 其次，說明以上所構成之薄膜電晶體1的製造方法。 第2圖係顯示薄膜電晶體1之製造方法之製程別截面圖。 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂———線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ______— 五、發明說明（/。） 在製造薄膜電晶體1之時，於第2圖(a)中，首先，對 於玻璃基板11之表面，利用等離子體CVD法（以 TEOS(Tetraethylorthosilicate : (C2H5〇)4Si)爲原料氣體）形 成厚度400nm左右之底塗絕緣膜12，其次，利用等離子體 CVD法(以例如矽烷(SiH4)爲原料氣體)在底塗絕緣膜12上 形成厚度30nm〜200nm之非結晶砂膜(未予圖示）。其次， 藉由照射例如XeCl準分子雷射，讓非結晶矽結晶化，來 形成多晶矽膜。此時，雷射光之掃描方向係與將待形成源 極區域之區域和待形成汲極區域之區域加以連接之方向一 致。又，此時之照射條件雖取決於非結晶矽膜之膜厚與膜 材質等之條件，惟較佳係在能量密度150〜450mJ · cnf2、 照射次數1〜500次之範圍來進行。其次，將非結晶矽膜以 眾知之光微影及蝕刻來圖案化成爲島狀，形成半導體膜14 〇 其次，於第2圖（b)中，利用等離子體CVD法（以 TEOS爲原料氣體)以將形成有半導體膜14之底塗絕緣膜 12的表面加以覆蓋的方式形成閘極絕緣膜16。其次，在閘 極絕緣膜16上形成例如由鉬與鎢之合金MoW所構成之閘 極導電膜，之後，藉由光微影與蝕刻將閘極導電膜做島狀 之圖案化來形成閘極31。此時，閘極31係位於半導體膜 14之上方來形成。其次，產生氫稀釋膦PH3之等離子體， ..以閘極31爲光罩，在加速電壓701^¥、劑量1\1013(：1^2的 條件對半導體膜14進行離子摻雜，以於該半導體膜14形 成LDD區域37。 12 度適用中國國家標準（CNS)A4規格（210 X 297公釐1 " "" -----—I-----—----訂---------^ (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ____ B7 _ 五、發明說明_(") 其次，於第2圖(c)中，藉由光阻39來被覆閘極31之 表面以形成摻雜光罩。其次，產生氫稀釋膦PH3之等離子 體’以上述摻雜光罩爲光罩，在加速電壓70kV、劑量lx 1015cnT2的條件對半導體膜14進行離子摻雜，以於該半導 體膜14形成源極區域32與汲極區域33。其次，在去除了 摻雜光罩之後，藉由例如RTA(RaPid Thermal Anneal)做局 部的加熱，使得植入之離子活性化。 其次，在第2圖(d)中，對於上述加工過之基板11之 表面全體利用等離子體CVD法(以TEOS爲原料氣體)來堆 積層間絕緣膜34。其次，自半導體膜14之源極區域32與 汲極區域33往上方貫通閘極絕緣膜16與層間絕緣膜34來 形成接觸孔34a，34a，之後，於層間絕緣膜34上藉濺鍍法 來堆積鋁(A1)層。其次，對該鋁(A1)層進行光微影與蝕刻使 其圖案化，來形成源極35與汲極36，藉此，即完成薄膜 電晶體1〇 其次，詳細地說明製造條件。在本發明中係以對構成 薄膜電晶體1之膜的內部應力或晶格應變進行控制爲其特 徵。惟，由於無法直接測定所完成之薄膜電晶體1之各膜 的內部應力或晶格應變，其測定並不容易。是以，在本實 施形態，係讓構成薄膜電晶體1之膜個別或複數種組合形 成於矽基板上，對形成於該基板上之膜的內部應力或晶格 應變進行測定，而將該測定値成爲既定之製造條件來當作 實際之薄膜電晶體1之製造條件加以設定。 具體而言，底塗絕緣膜12與閘極絕緣膜16之成膜條 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------I.-----------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7, ^__B7____ 五、發明說明（IX) 件，其電力密度係設定在300mW · cm·2〜800mW · cm·2的 範圍內，基板溫度係設定在400°C〜300°C之範圍內，TEOS 氣體流量對氧氣體流量之比係設定在0.01〜之範圍內， 壓力係設定在150Pa〜300Pa之範圍內，且在此範圍內之條 件下於矽基板上形成底塗絕緣膜與閘極絕緣膜之時，該底 塗絕緣膜與閘極絕緣膜之內部應力係設定成自l〇MPa成爲 400MPa的拉伸性之條件。 實際上，在該條件下形成底塗絕緣膜12與閘極絕緣膜 16來製作薄膜電晶體1，而對於該薄膜電晶體1測定底塗 絕緣膜與閘極絕緣膜之內部應力。在此測定中，將層間絕 緣膜34等位於閘極絕緣膜16上方之層加以剝除，穿過閘 極絕緣膜16來照射X射線藉由X射線繞射法所評價之半 導體膜14(多晶矽膜)之晶格應變、以及進一步剝除閘極絕 緣膜16後所評價之半導體膜14的晶格應變之間的差係介 於0.01%〜0.11%的範圍內。此相當於從lOMPa到400MPa 之內部應力。又，對於以上述方式所製作之其他的薄膜電 晶體1，若剝除玻璃基板11而自底塗絕緣膜12側對半導 體膜14照射X射線以X射線繞射法來進行評價，則半導 體膜14在有和沒有底塗絕緣膜12之情況的晶格應變之差 .係介於0.01%〜0.11%之範圍。此相當於從lOMPa到 400MPa之內部應力。 又，閘極導電膜(閘極31)之成膜條件，其電力密度係 設定在16W · cm_2〜22W · cm·2的範圍內，壓力係設定在 150Pa〜300Pa之範圍內，且在此範圍內之條件下於矽基板 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-------------------訂·--------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 __B7____ 五、發明說明（f)) 上形成閘極導電膜之時，其內部應力係設定成自500MPa 成爲1200MPa的拉伸性之條件。 實際上，在該條件下形成閘極導電膜來製作薄膜電晶 體1，而對於該薄膜電晶體1測定閘極導電膜之內部應力 。在此測定中，將層間絕緣膜34等位於閘極導電膜31上 方之層加以剝除，藉由X射線繞射法來評價閘極31之晶 格應變則發現係介於0.1%〜0.4%的範圍內。此相當於從 500MPa到2000MPa之內部應力。此處，壓縮性之內部應 力表示膜係彎曲成凸型，又拉伸性之內部應力表示膜係彎 曲成凹型。又，對於以上述條件所製作之其他的薄膜電晶 體1，若剝除玻璃基板11以X射線繞射法來分別進行半導 體膜14之通道區域61、源極區域32、以及汲極區域33之 晶格應變的評價可發現，通道區域61之晶格應變較少。此 意味著閘極31之拉伸性的晶格應變會對於半導體膜14之 通道區域61施加壓縮力。 又，層間絕緣膜34之成膜條件，其電力密度係設定在 300mW · cm~2〜800mW · cm_2的範圍內，基板溫度係設定在 400°C〜300°C之範圍內，TEOS氣體流量對氧氣體流量之比 係設定在〇·〇1〜〇·5之範圍內，壓力係設定在150Pa〜300Pa 之範圍內，且在此範圍內之條件下於矽基板上形成層間絕 緣層之時，該層間絕緣層之內部應力係設定成自lOMPa成 爲400MPa的拉伸性之條件。 實際上，在該條件下形成層間絕緣層34來製作薄膜電 晶體1，而對於該薄膜電晶體1測定層間絕緣層34之內部 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 ¥釐） " ——--------------丨—訂---------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ^_B7___ 五、發明說明（卟） 應力。在此測定中，穿過層間絕緣膜34對閘極31照射X 射線之情況與剝除層間絕緣膜34而對閘極31照射X射線 之情況，由X射線繞射法所評價之閘極31的晶格應變之 差係介於〇·〇1%〜0.08%的範圍。此相當於從lOMPa到 400MPa之內部應力。 其次，說明以上述方式所構成之薄膜電晶體1之作用 效果。本發明者爲了確認本實施形態之薄膜電晶體1的效 果，乃在包含上述範圍之寬廣的範圍內來變化其製造條件 而製作薄膜電晶體，並就該薄膜電晶體之各膜的內部應力 或晶格應變與性能的關係加以測定。此測定係在測定完薄 膜電晶體之遷移度（亦即接通電流）之後，如上述般將該薄 膜電晶體做部分的剝除後藉由X射線繞射法來測定各膜之 內部應力或是晶格應變所進行者。其測定結果係示於第3 圖〜第6圖。 第3圖係顯示薄膜電晶體之性能之遷移度與閘極之晶 格應變之間的關係圖。第3圖之橫軸中，負的區域代表壓 縮性之晶格應變，正的區域代表拉伸性之晶格應變。壓縮 性之晶格應變係意味著閘極彎曲成凸型，拉伸性之晶格應 變係意味著閘極彎曲成凹型。進行過第3圖之測定之薄膜 電晶體中之閘極絕緣膜的內部應力爲約30MPa之拉伸性應 力。由第3圖可知’薄膜電晶體之遷移度在閘極31(亦即 閘極導電膜）之晶格應變爲壓縮性之情形係約SOcmVv/s， 而當閘極導電膜之晶格應變爲拉伸性之情況（正確地說爲 0.1%之情況）’則提升到約120〜140 cm2/V/s。是以，在本 16 本紙張尺度適用中國國家標準（CNS)A4規格（210<^7公餐）一 ---- I-----------#--------π---------線_ (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ___B7____ 五、發明說明（K ) 實施形態中，如上所述，閘極31之晶格應變係設定於 0.1%〜0.4%之範圍。藉此，相較於習知例可得到提升遷移 度之薄膜電晶體。 第4圖係顯示薄膜電晶體之遷移度與閘極之內部應力 之間的關係圖。第4圖之橫軸中’負的區域代表壓縮性之 內部應力，正的區域代表拉伸性之內部應力。壓縮性之內 部應力係意味著閘極絕緣膜彎曲成凸型，拉伸性之內部應 力係意味著閘極絕緣膜彎曲成凹型。進行過第4圖之測定 之薄膜電晶體中之閘極的晶格應變爲0.15%之拉伸性應變 。由第4圖可知，藉由令閘極絕緣膜之內部應力爲拉伸性( 正確地說爲l〇MPa以上），則可提升薄膜電晶體之遷移度 。是以’在本實施形態中，閘極絕緣膜之內部應力係設定 成lOMPa〜400MPa之拉伸性。藉此，相較於習知例可得到 提升遷移度之薄膜電晶體。 第5圖係顯示薄膜電晶體之遷移度與底塗絕緣膜之內 部應力之間的關係圖。第5圖之橫軸中，負的區域代表壓 縮性之內部應力，正的區域代表拉伸性之內部應力。壓縮 性之內部應力係意味著底塗絕緣膜彎曲成凸型，拉伸性之 內部應力係意味著底塗絕緣膜彎曲成凹型。進行過第5圖 之測定之薄膜電晶體中之絕緣膜的內部應力爲l〇〇MPa。 由第5圖可知’藉由令閘極絕緣膜之內部應力爲拉伸性(正 確地說爲lOMPa以上），則可提升薄膜電晶體之遷移度。 是以’在本實施形態中，閘極絕緣膜之內部應力係設定成 lOMPa〜400MPa之拉伸性。藉此，相較於習知例可得到提 17 本紙張尺度適用中國國家標準（CNS)A4規格（210 ----- --------------------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 503584 B7 五、發明說明（Μ ) 升遷移度之薄膜電晶體。 第6圖係顯示薄膜電晶體之遷移度與層間絕緣膜; 部應力之間的關係圖。第6圖之橫軸中，負的區域代表_ 縮性之內部應力，正的區域代表拉伸性之內部應力。內# 應力之壓縮性與拉伸性之意思與上述相同。由第6圖可失口 ，藉由令層間絕緣膜之內部應力爲拉伸性（正確地說胃 lOMPa以上），則可提升薄膜電晶體之遷移度。是以，在本 實施形態中，閘極絕緣膜之內部應力係設定成 lOMPa〜400MPa之拉伸性。藉此，相較於習知例可得到提 升遷移度之薄膜電晶體。 又，在上述之構成例中，係顯示了於玻璃基板11上形 成之用以包圍半導體膜14之各膜的內部應力或晶格應變全 爲拉伸性的情況，爲本發明之本質係對於包圍以多晶矽爲 主成分之半導體膜14的膜賦予拉伸性之內部應力或晶格應 變’以對該半導體膜14施加壓縮力，故包圍該半導體膜 14之各膜的內部應力之和成爲拉伸性即可。 又’在上述之構成例中，作爲基板11係使用了玻璃基 板’惟亦可使用矽基板、陶瓷基板、石英基板等。 又’在上述之構成例中，作爲半導體膜14之底膜之非 結晶砂膜雖利用等離子體CVD法來形成，爲除了等離子體 CVD法以外亦可使用減壓CVD法或濺鍍法等來形成。又 ’半導體膜14之底膜除了非結晶矽以外，亦可由矽•鎵、 微晶砂、多晶砍、或單晶砍來構成。 又’在上述構成例中，作爲底塗絕緣膜雖使用了氧化 18 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） Γ 请先閱讀背面之注意事項再填寫本頁) ·_ 丨—訂---------- 503584 A7 __B7____ 五、發明說明（G ) 矽膜，惟亦可使用氮化矽等之絕緣膜。 又，在上述之構成例中，作爲雷射雖使用了 XeCl準 分子雷射，惟亦可使用ArF、KrF等之準分子雷射或氬雷 射。 又，在上述構成例中，作爲閘極絕緣膜雖以TEOS當 作原料氣體藉由等離子體CVD法來形成氧化矽膜，惟除了 等離子體CVD法以外亦能以減壓CVD法、濺鍍法、高壓 氧化法等來形成，又，作爲閘極絕緣膜亦可形成熱氧化膜 或氮化矽膜等。 又，在上述之構成例中，作爲所植入之離子的活性化 處理雖施以RTA，惟經離子植入之半成品在400°C以上之 環境氣氛中退火亦可，又，若預期與磷一同植入之氫可發 揮自活性則也可不經特別的活性化處理。 又，在上述之構成例中，作爲閘極之材料、源極之材 料以及汲極之材料雖分別使用了鉬與鎢之合金MoW、鋁 (A1)，惟也可使用由鋁(A1)、鉅(Ta)、鉬(Mo)、鉻(Cr)、鈦 (Ti)等之金屬或其合金，又，也可使用含有多量雜質之多 晶矽、多晶矽與鎵之合金、或ITO等之透明導電材料。 又，在上述構成例中，作爲層間絕緣膜，雖以TESO 作爲原料氣體藉由等離子體CVD法來形成二氧化矽膜’惟 該膜亦可用ΑΡ-CVD法或ECR-CVD法來形成。又，作爲 層間絕緣膜，可形成氮化矽、氧化鉬、氧化鋁等之絕緣膜 ，進一步可將該等絕緣膜積層形成之。 又，在上述構成例中，作爲所植入之離子，雖使用磷 19 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------参--------訂---------S (請先閱讀背面之注意事項再填寫本頁) 503584 A7 ____B7 _ 五、發明說明（θ ) (P)作爲施體，惟亦可使用鋁(A1)等作爲施體，又，也可使 用作爲受體之硼(B)等。 實施形態2 第7圖所示係與本發明之實施形態2相關之液晶顯示 裝置之構成方塊圖，第8圖所7K係第7圖之液晶顯不裝置 之構造的部分截面圖。於第8圖中之與第1圖同一符號係 < 表示同一或相當之部分。 在第7圖中，液晶顯示裝置200係具備液晶面板201 與用以驅動該面板之CMOS驅動電路30A，30B。在液晶面 板201中，複數之掃描線41與複數之訊號線42係以相互 直交的方式來配置，該掃描線41與訊號線42所區隔成之 矩陣狀物係形成了畫素202。在各畫素202係配置有由薄 膜電晶體所構成之切換電晶體50。切換電晶體50之閘極 係與掃描線41連接，源極係與訊號線42連接，汲極係與 畫素電極（未予圖示)連接。此汲極係藉由在等效電路上分 別形成於畫素電極與對向電極24之間、以及輔助電容與對 向電極24之間之液晶電容29與積蓄電容28來連接到該對 向電極24。又，掃描線41與訊號線42分別連接到CMOS 驅動電路30A與CMOS驅動電路30B。又，切換電晶體50 係由實施形態1之薄膜電晶體1所構成。 —倂參照第8圖，液晶面板201具有：彼此對向之對 向基板211與陣列基板212、挾持於兩基板211，212之間之 液晶26、以及分別配置於兩基板211，212之外側之偏光板 27。對向基板211係在玻璃基板23之內面依序積層著濾色 20 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂 ---------線 (請先閱讀背面之注意事項再填寫本頁) 503584 A7 五、發明說明（) 片25、對向電極24、以及定向膜22所構成者。陣列基板 212係由構成液晶面板201之區域與構成CMOS驅動電路 30A，30B之區域所構成者。在陣列基板212之構成液晶面 板201的區域，於玻璃基板38之內面分別形成有掃描線 41、訊號線42、切換電晶體50、畫素電極21，並形成有 用以將該等覆蓋之定向膜22。另外，陣列基板212之構成 CMOS驅動電路30A，30B之區域，該CMOS驅動電路 30A，30B係於玻璃基板38之內面與液晶面板201之構成要 素21，41，42,50 —體形成。又，構成切換電晶體50之薄膜 電晶體，其玻璃基板38係以構成第1圖之玻璃基板11的 方式與液晶面板201之其他構成要素21，41，42 —體形成。 以上述方式所構成之液晶顯示裝置，係對應於通過掃 描線41自CMOS驅動電路30A所輸入之掃描訊號讓各畫 素2〇2之切換電晶體50依序接通，此接通時晝像訊號(源 極訊號)會依序通過訊號線42自CMOS驅動電路30B寫入 各畫素202中。藉此，液晶26依據畫像訊號而調變，於顯 示畫面顯示出對應於該畫像訊號之畫像。此時，由於切換 電晶體50之遷移度受到提升，掃描訊號之用以接通該切換 電晶體50的閘極控制電壓些許即可。是以，可減低CMOS 驅動電路30A之消耗電力、乃至於減低液晶顯示裝置2〇0 之消耗電力。 又，在上述構成例中，雖以實施形態〗之薄膜電晶體 1來構成切換電晶體50，惟構成CMOS驅動電路30A，30B 之薄膜電晶體亦可由實施形態1之薄膜電晶體1來構成， 21 ---------------------訂—-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS〉A4規格(210x 297公爱了 503584 A7 ___B7_____ 五、發明說明（产） 藉此，可進一步減低液晶顯示裝置200之消耗電力。 實施形態3 第9圖所示係與本發明之實施形態3相關之電致發光 顯示裝置之構成方塊圖’第10圖所示係第9圖之電致發光 顯示裝置之構造的部分截面圖。於第10圖中’與第1圖爲 相同之符號係表示同一或相當之部分。 於第9圖中，電致發光顯示裝置300係具備：電致發 光顯示部(以下稱爲EL顯示部)301與用以驅動該顯示部之 CMOS驅動電路70Α，70Β。於EL顯示部301中，複數之 掃描線41與電流供給線47對、以及複數之掃描線41與複 數之訊號線42係以相互直交的方式來配置，該掃描線41 與訊號線42、以及該掃描線41與電流供給線47所區隔成 之矩陣狀物係形成了畫素302。在各畫素302係配置有由 實施形態1之薄膜電晶體1所構成之切換電晶體50以及驅 動用電晶體46。切換電晶體50之閘極係與掃描線41連接 ，一側之主端子係與訊號線42連接，另一側之主端子係透 過電容器與電流供給線47連接。驅動用電晶體46之閘極 係與切換電晶體50之上述另一側之主端子連接著，一側之 主端子係與電流供給線47連接，另一側之主端子係與電致 發光元件48連接著。 一併參照第10圖，電致發光顯示裝置300具有薄膜 電晶體陣列基板311，該薄膜電晶體陣列基板311係在玻 璃基板310上一體形成EL顯示部301與CMOS驅動電路 70A，70B所構成者。在EL顯示部301中，於玻璃基板310 22 本紙張尺度顧中關家鮮（CNS)A4規格（210 X 297公爱)" " H ϋ n n n n It ϋ n f flu n » n m ϋ n n ϋ n w(OJa n n el n _1 n n I (請先閱讀背面之注意事項再填寫本頁) 503584 A7 _ B7 五、發明說明（w) 上係依序積層底塗絕緣膜12、閘極絕緣膜16、以及層間絕 緣膜34，利用該等在每個畫素302形成各薄膜電晶體(係 構成驅動用電晶體46以及切換電晶體50，圖10中僅顯示 了驅動用電晶體46)。又，在層間絕緣膜34上之既定區域 係依序形成：由ITO膜所構成之透明電極49、由例如聚乙 烯二羥基噻吩(PEDT)所構成之導電性高分子膜43、實際上 發光之例如聚二烷基芴衍生物膜44、以及鈣(Ca)膜所構成 之陰極45。而該等係構成了電致發光單元48。藉此，驅動 用電晶體46與切換電晶體50乃和電致發光單元48 —體形 成。 以上述方式所構成之電致發光顯示裝置300，一旦 CMOS驅動電路70A對掃描線41輸出脈衝訊號，則切換 電晶體50會接通。另一方面，CMOS驅動電路70B會配 合該脈衝訊號輸出之時機對訊號線42輸出顯示訊號。如此 / 一來，不僅驅動用電晶體46呈接通狀態，對應於該顯示訊 號的電流會自電流供給線47流動而讓電致發光單元48發 光。此時，由於切換電晶體50與驅動用電晶體46之遷移 度受到提升，掃描訊號之用以接通該切換電晶體50的閘極 控制電壓些許即可。是以，可減低CMOS驅動電路70A之 消耗電力、乃至於減低電致發光顯示裝置300之消耗電力 〇 又，在上述構成例中，雖以實施形態1之薄膜電晶體 1來構成切換電晶體50，惟構成CMOS驅動電路70A，70B 之薄膜電晶體亦可由實施形態1之薄膜電晶體1來構成， 23 βϋ n n n ϋ n i n n n · an n n IB1 n n fi J ，I Mmm— n flu ϋ I flu ·ϋ I 言 纟 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503584 A7 —---— B7____ 五、發明說明（^) 〜 藉此，可進一步減低電致發光顯示裝置300之消耗電力。 又，在上述構成例中，作爲電致發光材料（發光材料) 雖使用了聚二甲基芴衍生物，惟亦可使用其他的有機材料( 例如其他的聚芴系材料或聚苯乙烯撐系材料），又也可使用 無機材料。 又，在上述實施形態1〜3中，雖以頂閘(top-gate)型之 物來構成薄膜電晶體，惟亦可由基板上依序積層形成閘極 、聞極絕緣膜、半導體膜來構成底閘(bottom_gate)型者。 由以上說明可知，對於同業者而言，本發明中顯然有 許多的改良與其他之實施形態。是以，上述說明僅是作爲 範例來解釋，其目的僅是教導業者實行本發明之最佳態樣 而提供者。在不跳脫本發明之精神的前提下，可將其構造 以及/或是機能的詳細部分做實質的變更。 [產業上可利用性] 有關本發明之薄膜電晶體，其作爲液晶顯示裝置、電 致發光顯示裝置等所使用之薄膜電晶體是有用的。 有關本發明之液晶顯不裝置，其作爲液晶電視、液晶 監視器、液晶資訊端子等之顯示部是有用的。 有關本發明之電致發光顯示裝置，其作爲電視、監視 器、資訊端子等之顯示部是有用的。 [符號說明] Γ%先閱讀背面之注意事項再填寫本頁> --------訂---------線 1,401 薄膜電晶體 11 基板 12 底塗絕緣膜 24 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503584 A7 B7 25 26 27 28 29 30A，30B，70A，70B 31 五、發明說明（W ) 13 14 16 21 22 24 32 33 34 34a，34b 35 36 37 39 41 42 43 44 45 46 47 非結晶矽膜 半導體膜 閘極絕緣膜 畫素電極 定向膜 對向電極 濾色片 液晶 偏光板 積蓄電容 液晶電容 CMOS驅動電路 閘極 源極區域 汲極區域 層間絕緣膜 接觸孔 源極 汲極 LDD區域 光阻 掃描線 訊號線 導電性高分子膜 聚二烷基芴衍生物膜 貫通孔 驅動用電晶體 電流供給線 -------------Φ -------—訂---------Μ—01 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503584 A7 B7 五、發明說明_( W) 48 49 50 61 200 201 202,302 211 212 300 301 310 311 電致發光單元 透明電極 切換電晶體 通道區域 液晶顯示裝置 液晶面板 畫素 對向基板 陣列基板 電致發光顯示裝置 EL顯示部 玻璃基板 薄膜電晶體陣列基板 ---------------------訂—-----線"^1^" (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）503584 A7 __B7 —_____ 5. Description of the Invention (/) [Technical Field] The present invention relates to a thin film transistor and a liquid crystal 'display device and an electroluminescence display device using the transistor. [Background Art] As a conventional thin-film transistor, for example, a low-temperature polycrystalline silicon thin-film transistor (hereinafter referred to as "low-temperature Poly-SiTFT") which has been continuously developed in liquid crystal display devices. The low temperature Poly-SiTFT will be described below with reference to the drawings. Large-scale liquid crystal display devices using polycrystalline silicon thin film transistors require a large area and use cheap glass substrates. However, when a glass substrate is used as a substrate, since its heat resistance is not sufficient, it is necessary to produce a thin film transistor at a relatively low temperature (about 600 ° C or lower). Fig. 11 is a cross-sectional view showing a conventional manufacturing method of a low-temperature Poly-SiTFT. In the conventional manufacturing method of low-temperature Poly-SiTFT, firstly, a substrate with an undercoat insulating film 12 (approximately 40 nm) made of a silicon oxide film to prevent diffusion of impurities in the glass substrate 11 is first provided on the surface of the glass substrate In the above, an amorphous silicon film 13 having a thickness of 50 nm is formed by a plasma CVD method using silane (SiH4) as a source gas (FIG. 11 (a)). Next, the xeci excimer laser 15 is irradiated to crystallize the amorphous sand film 13 to form a semiconductor film 14 made of polycrystalline silicon. Although the irradiation conditions at this time depend on conditions such as the film thickness and film material of the semiconductor film 14, the energy density is 150 to 450 mJ · cm · 2, and the number of irradiation times is 1 to 500 times. This semiconductor film 14 is patterned into an island shape by known light lithography and etching (Fig. 11 (b)). Secondly, a thickness of 3 is formed on the island-shaped semiconductor film 14 by the plasma CVD method. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) · 'Circle --------- ------------- Order ------- line (please read the notes on the back before filling this page) 503584 A7 ..______ B7________ V. Description of the invention (2) 90nm gate极 硅 膜 16。 Insulation film 16. Next, the gate electrode 31 is formed by using an alloy MoW of molybdenum and tungsten, and the gate insulating film 16 and the gate electrode 31 are patterned into island shapes by known light lithography and etching. Next, using the gate 31 as a mask, a plasma of hydrogen-diluted phosphine PH3 was generated, and ion doping was performed under the conditions of an acceleration voltage of 70 kV and a dose of 1 X 1015 cm · 2 to form a source region 32 and a drain region 33 (the first Figure 11 (c)). Next, heat treatment is performed to activate the implanted ions. Next, a silicon dioxide (SiO2) is deposited on the entire surface by the plasma CVD method as an interlayer insulating film 34 ', a contact hole is formed, and then, for example, aluminum (A1) is deposited by sputtering to bury the contact hole. Next, the aluminum (A1) film is patterned by photolithography and etching to form a source electrode 35 and a drain electrode 36. This completes the thin film transistor 401 (FIG. 11 (d)). However, the conventional low-temperature Poly-SiTFT manufactured in the above-mentioned manner has a problem that the on-current is low. [Disclosure of the Invention] The present invention is made to solve the above-mentioned problems, and an object thereof is to provide a thin film transistor which can increase the on-current. Therefore, the inventors first set out to understand why the current is low. As a result, it was found that the reason is as described below. That is, in the process of low-temperature Poly-SiTFT, once the amorphous silicon film formed on the glass substrate as a base film is crystallized by laser, the temperature gradient generated during its crystallization will become Tensile stress above 1000 MPa is generated in the polycrystalline silicon film of the completed film. The tensile stress causes strain on the crystal lattice of the polycrystalline silicon film, so that defects occur in the polycrystalline silicon film. Therefore, the defect will capture the shift between the source region and the drain region. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- -------- Order --------- Line (Please read the precautions on the back before filling this page) 503584 A7 ___ Β7 _______ V. Description of the invention ()) The moving electrons, so the thin film transistor The mobility will decrease, and as a result, the change in Id-Vg characteristics will slow down, and the on-current will decrease. Therefore, from the results of the above explanation, it is known that it is effective to apply a compressive force to a stretchable polycrystalline silicon film in order to increase the on-current. Specifically, compressive force can be applied to the polycrystalline silicon film by giving tensile internal stress or lattice strain to the peripheral film surrounding the polycrystalline silicon film. As a result, defects in the polycrystalline silicon film will be reduced, and the mobility of the thin film transistor will be improved. . As a result, the Id-Vg characteristic changes significantly, and the on-current increases. Therefore, the thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), a semiconductor film (having a source region, a channel region, and a substrate region formed on the primer insulating film, respectively). The drain region is mainly composed of silicon), a gate insulating film (adjacent to the above-mentioned channel region of the semiconductor film), and a film-shaped gate (adjacent to the gate insulating film); The sum of the internal stresses of the gate insulating film is stretchability. According to this configuration, since the compressive force can be applied to the semiconductor film by the tensile internal stress of the gate insulating film and the cathode adjacent to the semiconductor film, the on-current can be increased. In this case, the lattice strain of the gate may be stretchable. With this configuration, the on-current can be further increased. At this time, the absolute strain of the lattice strain of the above-mentioned gate electrode may also be in the range of 0.1% to 0.4%. According to this configuration, the on-current can be appropriately increased. The thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), and a semiconductor film (having a source region, a channel region, and a drain electrode formed on the primer insulating film, respectively). Area, mainly silicon. This paper size applies Chinese National Standard (CNS) A4 specification (21G X 297 public love) " '~ (~ Please read the precautions on the back before filling this page) -----— Order --------- Line-503584 A7 _ B7______ 5. Description of the Invention (0) composition), gate insulation film (adjacent to the above-mentioned channel region of the semiconductor film), and film-shaped gate electrode (connected with the The gate insulating film is adjacent); characterized in that the internal stress of the gate insulating film is stretchable. According to this configuration, since the compressive force can be applied to the semiconductor film by the internal stress of the gate insulation adjacent to the semiconductor film, the on-current can be increased. At this time, the absolute stress of the internal stress of the gate insulating film may also be 10 MPa to 400 MPa. According to this configuration, the on-current can be appropriately increased. The thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), and a semiconductor film (having a source region, a channel region, and a drain electrode formed on the primer insulating film, respectively). Area, which is mainly composed of silicon), a gate insulating film (adjacent to the above-mentioned channel region of the semiconductor film), and a film-shaped gate (adjacent to the gate insulating film); The sum of the respective internal stresses of the gate insulating film is stretchability. According to this configuration, since the compressive force can be applied to the semiconductor film by the internal stress of the gate insulating film and the primer insulating film adjacent to the semiconductor film, the on-current can be increased. In this case, each of the internal stresses of the primer insulating film and the gate insulating film can be made stretchable. According to this configuration, the on-current can be further increased. At this time, the absolute stress of the internal stress of the above-mentioned primer insulating film may also be 10 MPa to 400 MPa. According to this configuration, the on-current can be appropriately increased. The thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), and a semiconductor film (having a source region, a channel region, and a drain electrode formed on the primer insulating film, respectively). Area, with silicon as the main component), gate insulation film (adjacent to the above-mentioned channel area of the semiconductor film), 6 paper standards are applicable to the Chinese National Standard (CNS) A4 specification (referred to as χ 297 public love) '---- ---------------- Order --------- line (please read the notes on the back before filling this page) 503584 A7 __ B7 ___ V. Description of the invention ( f) and a film-shaped gate (adjacent to the gate insulating film); characterized in that the distance between the lattices of the source region and the drain region of the semiconductor film is greater than the distance between the lattices of the channel region long. According to this configuration, since a compressive force is applied to the semiconductor film by the gate, the on-current can be increased. In this case, the lattice strain of the gate may be stretchable. With this configuration, the on-current can be further increased. At this time, the absolute strain of the lattice strain of the gate can be 0.1% to 0.4%. According to this configuration, the on-current can be appropriately increased. The thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), and a semiconductor film (having a source region, a channel region, and a drain electrode formed on the primer insulating film, respectively). Area, which is mainly composed of silicon), a gate insulating film (adjacent to the above-mentioned channel region of the semiconductor film), and a film-shaped gate (adjacent to the gate insulating film); The sum of the internal stresses of the gate electrode and the gate insulating film is stretchability. According to this configuration, the compressive force can be applied to the semiconductor film by the internal stress of the undercoat insulating film, the gate, and the gate insulating film surrounding the semiconductor film, which can increase the on-current. The thin film transistor of the present invention includes a substrate, a primer insulating film (formed on the substrate), and a semiconductor film (having a source region, a channel region, and a drain electrode formed on the primer insulating film, respectively). Area, mainly composed of silicon), a gate insulating film (adjacent to the above-mentioned channel region of the semiconductor film), a film-shaped gate (adjacent to the gate insulating film), and an interlayer insulating film (to be formed with The undercoat insulating film, the semiconductor film, the gate insulating film, and the surface of the substrate of the gate are covered. 7 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) ~ -------------------- ^ --------- line.φ. (Please read the precautions on the back before filling this page) 503584 A7 __B7___ V. Description of the invention (6) The author); It is characterized in that the internal stress of the interlayer insulating film is stretchability. According to this configuration, since the compressive force can be applied to the semiconductor film by the internal stress of the interlayer insulating film, the on-current can be increased. At this time, the absolute stress of the internal stress of the interlayer insulating film may be 10 MPa to 400 MPa. According to this configuration, the on-current can be appropriately increased. In the above case, the semiconductor film is made of crystallized polycrystalline silicon irradiated with radon light, and it is also feasible that the direction connecting the source region and the drain region is substantially the same as the scanning direction of the laser light. Methods. For polycrystalline silicon, since the scanning direction of the laser light for crystallization generates larger tensile internal stress than the direction perpendicular to the scanning direction, according to this configuration, the internal stress can be obtained by surrounding the semiconductor film. The internal stress of the film is effectively offset, and the on-current can be effectively increased. The thin-film transistor may be a top-gate transistor in which the semiconductor film, the gate insulating film, and the gate are sequentially laminated on the undercoat insulating film. The thin-film transistor may be a bottom-gate transistor formed by sequentially stacking the gate, the gate insulating film, and the semiconductor film on the primer insulating film. In addition, the liquid crystal display device of the present invention writes an image signal into the scanned pixels while sequentially scanning a plurality of pixels constituting the display screen, thereby changing the transmittance of the liquid crystal panel and correspondingly The image of the above-mentioned image signal is displayed on the above-mentioned display screen; it is characterized in that it is used to switch between the scanning state and the non-scanning state of the above pixels. 297 mm) ------------------- order --------- line " 4 ^ (Please read the precautions on the back before filling this page ) 503584 A7 V. Description of the invention (7) The switching element is composed of a thin film transistor in any one of the scope of patent applications 1, 4, 6, 9, 12, and 13. According to this configuration, since the turn-on current of the thin-film transistor is increased, the gate control voltage for turning on the switching element can be lowered, which can reduce the power consumption of the driving circuit of the switching element and even reduce the liquid crystal display device. Of power consumption. Furthermore, according to the electroluminescence display device of the present invention, while sequentially scanning a plurality of pixels constituting a display screen, a current corresponding to an image signal is supplied to the scanned pixels, thereby causing the electroluminescence unit to emit light. So that the image corresponding to the image signal is displayed on the display screen; it is characterized by a switching element for switching between the scanning state and the non-scanning state of the pixel and a current source for supplying the current corresponding to the image signal At least one of the transistors is composed of a thin film transistor according to any one of the scope of patent applications 1, 4, 6, 9, 12'13. According to this structure, the on-current of the & film transistor can be improved, and the control voltage for turning on the switching element can be reduced to a low voltage, which can reduce the power consumption of the driving circuit of the switching element and even reduce the power consumption. Power consumption of liquid crystal display devices. The above-mentioned object, other objects, features, and advantages of the present invention can be expressed by the following detailed description of suitable implementation modes with reference to the attached drawings. [Brief description of the drawings] Fig. 1 is a cross-sectional view showing the structure of a thin-film transistor related to the first embodiment of the present invention. Figure 2 shows the manufacturing process of the thin-film transistor shown in Figure i. __ 9 Zhang's Zhang Zheng uses the Chinese National Standard (CNS) A4 specification (210 X 297 Gongchu) --- I ----------------- Order ------- --i ^ w— (Please read the precautions on the back before filling this page) 503584 A7 _B7___ V. Description of the invention (public) The relationship between the mobility of the thin film transistor shown in Figure 3 and the lattice strain of the gate Illustration. Figure 4 shows the relationship between the mobility of the thin film transistor and the internal stress of the gate insulating film. Figure 5 shows the relationship between the mobility of the thin film transistor and the internal stress of the underlying insulating film. Figure 6 shows the relationship between the mobility of the thin film transistor and the internal stress of the interlayer insulating film. Fig. 7 is a block diagram showing the configuration of a liquid crystal display device according to the second embodiment of the present invention. Fig. 8 is a partial cross-sectional view showing the structure of the liquid crystal display device of Fig. 7. Fig. 9 is a block diagram showing the structure of an electroluminescent display device according to the third embodiment of the present invention. Fig. 10 is a partial sectional view showing the structure of the electroluminescent display device of Fig. 9. Fig. 11 is a cross-sectional view showing a conventional manufacturing method of a thin film transistor. [Best Mode for Carrying Out the Invention] An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) Fig. 1 is a cross-sectional view showing the structure of a thin-film electric crystal according to Embodiment 1 of the present invention. As shown in Fig. 1, the thin film transistor 1 includes: a substrate 11, a primer 10, and a paper size that conforms to the Chinese National Standard (CNS) A4 (210 X 297 mm) K nnnn In m It nnnd · nn 11 · 1 nn —i ot fl (K nnnnnn I (Please read the precautions on the back before filling out this page) 503584 A7 V. Description of the invention (?) Edge film 12 (formed on the substrate 11), semiconductor film 14 (formed on A predetermined region on the surface of the undercoat insulating film), a source region 32 and a drain region 33 (formed at predetermined intervals in the semiconductor film 14), and a low impurity region 37, 37 (Lightly Doped Drain Region: hereinafter LDD region) (individually formed between the source region 32 and the drain region 33, respectively), the channel region 61 (sandwiched between the two LDD regions 37, 37), and the gate insulating film 16 (Coated on the surface of the undercoat insulating film 12 on which the semiconductor film 14 is formed), film-shaped gate 31 (formed on the surface of the gate insulating film 16 above the above-mentioned channel region 61), interlayer insulating film 34 (The surface of the gate insulating film 16 on which the gate 31 is formed), And source 35 and drain 36 (through the gate insulating film 16 and the interlayer insulating film 34 from the source region 32 and the drain region 33 of the semiconductor film 14 respectively, and extending to the surface of the interlayer insulating film 34 The substrate 11 is composed of a glass substrate such as Koenco # 1737 manufactured by Dookunco. The undercoat insulating film 12 is used to prevent the diffusion of impurities, such as silicon oxide. Semiconductor The film 14 is composed of polycrystalline silicon. The source region 32 and the drain region 33 are both composed of a high concentration region of N-type impurities in the polycrystalline silicon, and the LDD region 37 is also composed of a low concentration region of N-type impurities. Structure. The channel region 61 is made of polycrystalline silicon, which is the base material of the semiconductor film 14. The gate 31 is made of, for example, an alloy of molybdenum and tungsten, MoW. The interlayer insulating film 34 is made of, for example, silicon dioxide (Si02) The source 35 and the drain 36 are made of, for example, aluminum (A1). Next, a method for manufacturing the thin film transistor 1 configured as described above will be described. FIG. 2 is a cross-sectional view showing a manufacturing process of the thin film transistor 1 .11 This paper is suitable for China National Standard (CNS) A4 Specification (210 X 297 mm) -------------------- Order --- line (Please read the precautions on the back before filling (This page) 503584 A7 ______— V. Description of the invention (/.) When manufacturing the thin film transistor 1, in FIG. 2 (a), first, the surface of the glass substrate 11 was subjected to a plasma CVD method (using TEOS (Tetraethylorthosilicate: (C2H5〇) 4Si) is used as a raw material gas) to form an undercoat insulating film 12 having a thickness of about 400 nm. Next, a plasma CVD method (for example, using silane (SiH4) as a raw material gas) is formed on the undercoat insulating film 12. An amorphous sand film (not shown) with a thickness of 30nm to 200nm. Secondly, the amorphous silicon is crystallized by irradiating, for example, XeCl excimer laser, to form a polycrystalline silicon film. At this time, the scanning direction of the laser light is the same as the direction connecting the region where the source region is to be formed and the region where the drain region is to be formed. In addition, although the irradiation conditions at this time depend on the film thickness and material quality of the amorphous silicon film, it is preferably performed in the range of an energy density of 150 to 450 mJ · cnf2, and the number of irradiation times of 1 to 500 times. Next, the amorphous silicon film is patterned into an island shape by well-known light lithography and etching to form a semiconductor film. 14 Next, in FIG. 2 (b), a plasma CVD method is used (using TEOS as a source gas). The gate insulating film 16 is formed so as to cover the surface of the undercoat insulating film 12 on which the semiconductor film 14 is formed. Next, a gate conductive film made of, for example, an alloy of molybdenum and tungsten MoW is formed on the gate insulating film 16, and then the gate conductive film is patterned in an island shape by photolithography and etching to form a gate. 31. At this time, the gate electrode 31 is formed above the semiconductor film 14. Next, a plasma of hydrogen-diluted phosphine PH3 is generated. The gate electrode 31 is used as a mask, and the semiconductor film 14 is ion-doped under the conditions of an acceleration voltage of 701 ^ ¥ and a dose of 1 \ 1013 (: 1 ^ 2). The semiconductor film 14 forms an LDD region 37. 12 degrees applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm 1 " " " ------ I ---------- Order --------- ^ (Please read the notes on the back before filling out this page) 503584 A7 ____ B7 _ V. Description of the invention _ &&; Second, in Figure 2 (c), borrow The surface of the gate electrode 31 is covered by a photoresist 39 to form a doped photomask. Secondly, a plasma of hydrogen-diluted phosphine PH3 is generated. The above-mentioned doped photomask is used as a photomask. The semiconductor film 14 is ion-doped so that the semiconductor film 14 forms a source region 32 and a drain region 33. Second, after removing the doping mask, for example, local heating is performed by using RTA (RaPid Thermal Anneal), The implanted ions are activated. Next, in FIG. 2 (d), the entire surface of the processed substrate 11 is plasma CVD (using TEOS). Source gas) to deposit the interlayer insulating film 34. Next, the gate insulating film 16 and the interlayer insulating film 34 are penetrated upward from the source region 32 and the drain region 33 of the semiconductor film 14 to form contact holes 34a, 34a. An aluminum (A1) layer is deposited on the interlayer insulating film 34 by a sputtering method. Next, the aluminum (A1) layer is patterned by photolithography and etching to form a source 35 and a drain 36, thereby, That is, the thin film transistor 10 is completed. Next, the manufacturing conditions are described in detail. In the present invention, it is characterized by controlling the internal stress or lattice strain of the film constituting the thin film transistor 1. However, it is impossible to directly measure the completed film. It is not easy to measure the internal stress or lattice strain of each film of the thin film transistor 1. Therefore, in this embodiment, the films constituting the thin film transistor 1 are formed individually or in combination on a silicon substrate. The internal stress or lattice strain of the film formed on the substrate is measured, and the measurement is set to a predetermined manufacturing condition and set as the actual manufacturing condition of the thin film transistor 1. Specifically, the undercoat insulation Membrane 1 2 Film-forming strip with gate insulating film 16 13 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -------- I .--------- --Order --------- Wire (please read the precautions on the back before filling this page) 503584 A7, ^ __ B7____ 5. Description of the Invention (IX), the power density is set at 300mW · cm · In the range of 2 ~ 800mW · cm · 2, the substrate temperature is set in the range of 400 ° C ~ 300 ° C, the ratio of TEOS gas flow to oxygen gas flow is set in the range of 0.01 ~, and the pressure is set in 150Pa When the undercoat insulating film and the gate insulating film are formed on a silicon substrate in a range of ~ 300Pa and under the conditions within this range, the internal stress of the undercoat insulating film and the gate insulating film is set to l0. MPa is a condition for stretchability of 400 MPa. Actually, a thin-film transistor 1 is formed by forming the undercoat insulating film 12 and the gate insulating film 16 under these conditions, and the internal stress of the undercoat insulating film and the gate insulating film is measured for the thin-film transistor 1. In this measurement, a layer above the gate insulating film 16 such as the interlayer insulating film 34 is peeled off, and the X-ray is irradiated through the gate insulating film 16 to the semiconductor film 14 (polycrystalline silicon) evaluated by the X-ray diffraction method. The difference between the lattice strain of the film) and the lattice strain of the semiconductor film 14 evaluated after further stripping the gate insulating film 16 is in the range of 0.01% to 0.11%. This corresponds to an internal stress from 10 MPa to 400 MPa. In addition, for other thin film transistors 1 manufactured as described above, if the glass substrate 11 is peeled off and the semiconductor film 14 is irradiated with X-rays from the undercoat insulating film 12 side for evaluation by the X-ray diffraction method, the semiconductor film is evaluated. 14 The difference in lattice strain between the cases with and without the primer insulating film 12 is in the range of 0.01% to 0.11%. This corresponds to an internal stress from 10 MPa to 400 MPa. In addition, for the film formation conditions of the gate conductive film (gate 31), the power density is set in the range of 16W · cm_2 ~ 22W · cm · 2, and the pressure is set in the range of 150Pa ~ 300Pa, and within this range Under the conditions within the silicon substrate 14 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) I ------------------- Order ·- ------- Line (Please read the precautions on the back before filling this page) 503584 A7 __B7____ V. Description of the Invention (f)) When the gate conductive film is formed on it, its internal stress is set from 500MPa to Conditions for stretchability of 1200 MPa. Actually, a thin film transistor 1 is formed by forming a gate conductive film under these conditions, and the internal stress of the gate conductive film is measured for this thin film transistor 1. In this measurement, the layers above the gate conductive film 31 such as the interlayer insulating film 34 were stripped off, and the lattice strain of the gate 31 was evaluated by the X-ray diffraction method. It was found to be between 0.1% and 0.4%. In the range. This corresponds to an internal stress from 500 MPa to 2000 MPa. Here, the compressive internal stress indicates that the film system is bent into a convex shape, and the stretchable internal stress indicates that the film system is bent into a concave shape. Further, for other thin film transistors 1 manufactured under the above conditions, if the glass substrate 11 is removed, the channel region 61, the source region 32, and the drain region 33 of the semiconductor film 14 are separately performed by the X-ray diffraction method. Evaluation of the lattice strain revealed that the lattice strain of the channel region 61 was small. This means that the tensile lattice strain of the gate electrode 31 exerts a compressive force on the channel region 61 of the semiconductor film 14. In addition, the film formation conditions of the interlayer insulating film 34 are set in a power density range of 300mW · cm ~ 2 ~ 800mW · cm_2, and the substrate temperature is set in a range of 400 ° C ~ 300 ° C. When the ratio of the oxygen gas flow rate is set in the range of 0.001 to 0.5, the pressure is set in the range of 150Pa to 300Pa, and when an interlayer insulating layer is formed on the silicon substrate under the conditions in this range, The internal stress of the interlayer insulating layer is set to a condition of stretchability from 10 MPa to 400 MPa. In fact, under this condition, an interlayer insulating layer 34 is formed to make a thin film transistor 1, and the inside of the interlayer insulating layer 34 is measured for the thin film transistor 1. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). ¥ li) ——-------------- 丨 —Order --------- Line (Please read the precautions on the back before filling in this page) 503584 A7 ^ _B7___ 5. Description of the Invention (Porphyry) Stress. In this measurement, the case where the gate 31 is irradiated with X-rays through the interlayer insulating film 34 and the case where the interlayer insulating film 34 is stripped and the gate 31 is irradiated with X-rays are evaluated by the X-ray diffraction method. The difference in the lattice strain is between 0.001% and 0.08%. This corresponds to an internal stress from 10 MPa to 400 MPa. Next, functions and effects of the thin film transistor 1 constructed as described above will be described. In order to confirm the effect of the thin film transistor 1 according to this embodiment, the inventors have manufactured a thin film transistor by changing its manufacturing conditions within a wide range including the above range, and have regard to the internal stress of each film of the thin film transistor or The relationship between lattice strain and performance was measured. This measurement is to measure the internal stress of each film or the internal stress of each film by X-ray diffraction method after measuring the mobility of the thin film transistor (that is, to turn on the current), and then to strip the thin film transistor as described above. Is carried out by lattice strain. The measurement results are shown in FIGS. 3 to 6. Fig. 3 is a graph showing the relationship between the mobility of the performance of the thin film transistor and the lattice strain of the gate. In the horizontal axis of Fig. 3, a negative region represents a compressive lattice strain, and a positive region represents a tensile lattice strain. A compressive lattice strain system means that the gate is bent into a convex shape, and a stretchable lattice strain system means that the gate is bent into a concave shape. The internal stress of the gate insulating film in the thin film transistor subjected to the measurement shown in FIG. 3 was a tensile stress of about 30 MPa. It can be seen from FIG. 3 that the mobility of the thin film transistor is about SOcmVv / s when the lattice strain of the gate electrode 31 (ie, the gate conductive film) is compressive. In the case of stretchability (in the case of 0.1%), it is increased to about 120 to 140 cm2 / V / s. Therefore, the Chinese paper (CNS) A4 (210 < ^ 7 公 餐） 一 ---- I ----------- # -------- π --------- line_ (Please read the back first Please note this page and fill in this page again) 503584 A7 ___B7____ 5. Description of the Invention (K) In the embodiment, as described above, the lattice strain of the gate 31 is set in the range of 0.1% to 0.4%. As a result, a thin film transistor having improved mobility can be obtained compared with the conventional example. Figure 4 is a graph showing the relationship between the mobility of the thin film transistor and the internal stress of the gate. The negative region of the horizontal axis in Fig. 4 represents the compressive internal stress, and the positive region represents the tensile internal stress. The compressive internal stress means that the gate insulating film is bent into a convex shape, and the tensile internal stress means that the gate insulating film is bent into a concave shape. The lattice strain of the gate electrode in the thin film transistor having been measured in FIG. 4 is a tensile strain of 0.15%. It can be seen from FIG. 4 that by making the internal stress of the gate insulating film to be stretchable (to be more than 10 MPa), the mobility of the thin film transistor can be improved. Therefore, in this embodiment, the internal stress of the gate insulating film is set to a stretchability of 10 MPa to 400 MPa. Thus, compared with the conventional example, a thin film transistor having improved mobility can be obtained. Fig. 5 is a graph showing the relationship between the mobility of the thin film transistor and the internal stress of the underlying insulating film. In the horizontal axis of Fig. 5, the negative region represents the compressive internal stress, and the positive region represents the tensile internal stress. The compressive internal stress means that the primer insulating film is bent into a convex shape, and the tensile internal stress means that the primer insulating film is bent into a concave shape. The internal stress of the insulating film in the thin-film transistor subjected to the measurement shown in FIG. 5 was 100 MPa. It can be seen from Fig. 5 that by making the internal stress of the gate insulating film to be stretchable (exactly 10 MPa or more), the mobility of the thin film transistor can be improved. Therefore, in this embodiment, the internal stress of the gate insulating film is set to a stretchability of 10 MPa to 400 MPa. In this way, compared with the conventional examples, we can get 17 paper sizes that are applicable to China National Standard (CNS) A4 specifications (210 ----- ------------------ --Order --------- line < Please read the notes on the back before filling this page) 503584 B7 V. Description of the invention (M) Thin film transistor with increased mobility. Figure 6 is a graph showing the relationship between the mobility of a thin film transistor and the interlayer insulation film stress. In the horizontal axis of Fig. 6, the negative region represents the internal stress of shrinkability, and the positive region represents the internal stress of stretchability. The meaning of compressibility and elongation of internal stress is the same as above. From Fig. 6, it can be lost. By making the internal stress of the interlayer insulating film to be stretchable (to be more than 10MPa in the stomach), the mobility of the thin film transistor can be improved. Therefore, in this embodiment, the internal stress of the gate insulating film is set to a stretchability of 10 MPa to 400 MPa. As a result, a thin film transistor with improved mobility can be obtained compared with the conventional example. Moreover, in the above-mentioned configuration example, the case where the internal stress or the lattice strain of each of the films formed on the glass substrate 11 to surround the semiconductor film 14 are all shown to be stretchable is the essence of the present invention. The film surrounding the semiconductor film 14 containing polycrystalline silicon as the main component imparts tensile internal stress or lattice strain to apply a compressive force to the semiconductor film 14, so the sum of the internal stresses of the films surrounding the semiconductor film 14 becomes tensile. Extensibility is sufficient. In addition, in the above configuration example, a glass substrate is used as the substrate 11; however, a silicon substrate, a ceramic substrate, a quartz substrate, or the like may be used. Further, in the above-mentioned configuration example, although the amorphous sand film as the base film of the semiconductor film 14 is formed by a plasma CVD method, a pressure-reduced CVD method or a sputtering method may be used in addition to the plasma CVD method. form. In addition to the non-crystalline silicon, the base film of the semiconductor film 14 may be composed of silicon gallium, microcrystalline sand, polycrystalline chopper, or single crystal chopper. Also, in the above configuration example, although the oxidation of 18 papers was used as the primer insulation film, the Chinese paper standard (CNS) A4 (21 × 297 mm) is applicable. Γ Please read the precautions on the back before filling in this page ) · _ 丨 —Order ---------- 503584 A7 __B7____ V. Description of the invention (G) Silicon film, but insulating films such as silicon nitride can also be used. In the above-mentioned configuration examples, although XeCl excimer laser is used as the laser, excimer laser such as ArF, KrF, or argon laser may be used. In the above configuration example, although the gate insulating film uses TEOS as a source gas to form a silicon oxide film by a plasma CVD method, in addition to the plasma CVD method, a reduced-pressure CVD method and a sputtering method can be used. And a high-pressure oxidation method, and a gate oxide film may be formed as a thermal oxide film or a silicon nitride film. In the above-mentioned constitution example, although RTA is applied as the activation treatment of implanted ions, the semi-finished product after ion implantation may be annealed in an ambient atmosphere of 400 ° C or more. The co-implanted hydrogen can exhibit self-activity or without special activation treatment. In the above configuration example, although MoW and aluminum (A1), which are alloys of molybdenum and tungsten, are used as the material of the gate, source and drain, respectively, aluminum (A1), aluminum (A1), Metals such as giant (Ta), molybdenum (Mo), chromium (Cr), titanium (Ti), or alloys thereof. Polycrystalline silicon, polycrystalline silicon and gallium alloys containing a large amount of impurities, or transparent conductive materials such as ITO can also be used. . In the above-mentioned configuration example, although the interlayer insulating film is formed of a silicon dioxide film by a plasma CVD method using TESO as a source gas, the film may be formed by an AP-CVD method or an ECR-CVD method. In addition, as the interlayer insulating film, an insulating film such as silicon nitride, molybdenum oxide, and aluminum oxide can be formed, and the insulating film can be further laminated. In the above configuration example, although the implanted ions are phosphorus 19, the paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ------------ See -------- Order --------- S (Please read the notes on the back before filling this page) 503584 A7 ____B7 _ V. Description of the invention (θ) (P) as donor However, aluminum (A1) and the like can also be used as donors, and boron (B) and the like as acceptors can also be used. Embodiment 2 FIG. 7 is a block diagram showing the structure of a liquid crystal display device related to Embodiment 2 of the present invention. FIG. 7K is a partial cross-sectional view showing the structure of the liquid crystal display device of FIG. The same symbols in Figure 8 as in Figure 1 < means the same or equivalent. In FIG. 7, the liquid crystal display device 200 includes a liquid crystal panel 201 and CMOS driving circuits 30A and 30B for driving the panel. In the liquid crystal panel 201, a plurality of scanning lines 41 and a plurality of signal lines 42 are arranged at right angles to each other. A matrix 202 separated by the scanning lines 41 and the signal lines 42 forms pixels 202. Each pixel 202 is provided with a switching transistor 50 composed of a thin film transistor. The gate of the switching transistor 50 is connected to the scanning line 41, the source is connected to the signal line 42, and the drain is connected to a pixel electrode (not shown). This drain is connected to the counter electrode by a liquid crystal capacitor 29 and a storage capacitor 28 formed between the pixel electrode and the counter electrode 24 and the auxiliary capacitor and the counter electrode 24 on an equivalent circuit, respectively. twenty four. The scanning lines 41 and the signal lines 42 are connected to the CMOS driving circuit 30A and the CMOS driving circuit 30B, respectively. The switching transistor 50 is composed of the thin film transistor 1 of the first embodiment. — Referring to FIG. 8, the liquid crystal panel 201 has: an opposite substrate 211 and an array substrate 212 facing each other, a liquid crystal 26 held between the two substrates 211 and 212, and liquid crystals 26 disposed outside the two substrates 211 and 212, respectively Polarizing plate 27. The opposite substrate 211 is sequentially laminated with the color filter 20 on the inner surface of the glass substrate 23. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ --------- Order --------- line (please read the notes on the back before filling this page) 503584 A7 V. Description of the invention () Sheet 25, counter electrode 24, and The alignment film 22 is constituted. The array substrate 212 is composed of a region constituting the liquid crystal panel 201 and a region constituting the CMOS driving circuits 30A and 30B. In the area of the array substrate 212 that constitutes the liquid crystal panel 201, scanning lines 41, signal lines 42, switching transistors 50, and pixel electrodes 21 are formed on the inner surface of the glass substrate 38, respectively, and orientations are formed to cover these areas. Film 22. In addition, the array substrate 212 is formed by the areas of the CMOS drive circuits 30A and 30B. The CMOS drive circuits 30A and 30B are integrally formed on the inner surface of the glass substrate 38 and the constituent elements 21, 41, 42, 50 of the liquid crystal panel 201. In the thin-film transistor constituting the switching transistor 50, a glass substrate 38 is formed integrally with the other components 21, 41, and 42 of the liquid crystal panel 201 so as to constitute the glass substrate 11 of Fig. 1. The liquid crystal display device constructed in the above manner corresponds to the scanning signal input from the CMOS driving circuit 30A through the scanning line 41 to sequentially turn on the switching transistors 50 of each pixel 202. When this is turned on, the daylight image The signals (source signals) are sequentially written into the pixels 202 from the CMOS driving circuit 30B through the signal line 42. Thereby, the liquid crystal 26 is adjusted according to the image signal, and an image corresponding to the image signal is displayed on the display screen. At this time, since the mobility of the switching transistor 50 is improved, the gate control voltage of the scanning signal for turning on the switching transistor 50 may be slightly. Therefore, the power consumption of the CMOS driving circuit 30A can be reduced, and even the power consumption of the liquid crystal display device 2000 can be reduced. In the above configuration example, although the switching transistor 50 is constituted by the thin film transistor 1 according to the embodiment, the thin film transistor constituting the CMOS driving circuits 30A and 30B may also be constituted by the thin film transistor 1 according to the first embodiment. 21 --------------------- Order ---------- (Please read the notes on the back before filling this page) This paper size is applicable to China National standard (CNS> A4 specification (210x 297 publicly loved 503584 A7 ___B7_____) 5. Description of the invention (production) By this, the power consumption of the liquid crystal display device 200 can be further reduced. Embodiment 3 The figure 9 is the same as the invention The block diagram of the structure of the electroluminescence display device according to the third embodiment is shown in FIG. 10, which is a partial cross-sectional view showing the structure of the electroluminescence display device in FIG. 9. In FIG. 10, it is the same as FIG. The symbols indicate the same or equivalent parts. In FIG. 9, the electroluminescence display device 300 includes an electroluminescence display section (hereinafter referred to as an EL display section) 301 and a CMOS drive circuit 70A for driving the display section. 70B. In the EL display section 301, a plurality of scanning lines 41 and a current supply line 47 are paired. The plurality of scanning lines 41 and the plurality of signal lines 42 are arranged in a manner orthogonal to each other. The scanning lines 41 and the signal lines 42 and the matrix formed by the scanning lines 41 and the current supply lines 47 are formed. A pixel 302 is provided. Each pixel 302 is provided with a switching transistor 50 and a driving transistor 46 composed of the thin film transistor 1 of Embodiment 1. The gate of the switching transistor 50 is connected to the scanning line 41. The main terminal on one side is connected to the signal line 42 and the main terminal on the other side is connected to the current supply line 47 through a capacitor. The gate of the driving transistor 46 is connected to the above-mentioned main terminal on the other side of the switching transistor 50 Connected, the main terminal on one side is connected to the current supply line 47, and the main terminal on the other side is connected to the electroluminescent element 48. Referring to FIG. 10 together, the electroluminescent display device 300 has a thin film transistor array Substrate 311, which is a thin film transistor array substrate 311 formed on the glass substrate 310 integrally formed with an EL display portion 301 and CMOS drive circuits 70A and 70B. In the EL display portion 301, the glass substrate 310 22 is taken into consideration Guan Family Fresh (CNS) A4 specifications (210 X 297 public love) " " H ϋ nnnn It ϋ nf flu n »nm ϋ nn ϋ nw (OJa nn el n _1 nn I (Please read the precautions on the back before filling in this (Page) 503584 A7 _ B7 V. Description of the invention (w) The top coating insulating film 12, the gate insulating film 16, and the interlayer insulating film 34 are sequentially laminated on top, and each thin film transistor is formed at each pixel 302 using these (The driving transistor 46 and the switching transistor 50 are configured. Only the driving transistor 46 is shown in FIG. 10). In addition, predetermined regions on the interlayer insulating film 34 are sequentially formed: a transparent electrode 49 made of an ITO film, a conductive polymer film 43 made of, for example, polyethylene dihydroxythiophene (PEDT), and a light emitting film which actually emits light. For example, a polydialkylfluorene derivative film 44 and a cathode 45 formed of a calcium (Ca) film. These systems constitute the electroluminescent unit 48. Thereby, the driving transistor 46 and the switching transistor 50 are formed integrally with the electroluminescent unit 48. In the electroluminescent display device 300 configured as described above, once the CMOS driving circuit 70A outputs a pulse signal to the scanning line 41, the switching transistor 50 is turned on. On the other hand, the CMOS driving circuit 70B outputs a display signal to the signal line 42 in accordance with the timing of the pulse signal output. As a result, not only the driving transistor 46 is turned on, but a current corresponding to the display signal will flow from the current supply line 47 to cause the electroluminescent unit 48 to emit light. At this time, since the mobility of the switching transistor 50 and the driving transistor 46 is improved, the gate control voltage of the scanning signal for turning on the switching transistor 50 may be slightly. Therefore, it is possible to reduce the power consumption of the CMOS driving circuit 70A and even the power consumption of the electroluminescent display device 300. In the above configuration example, the thin-film transistor 1 of the first embodiment is used to constitute the switching transistor 50. However, the thin film transistors constituting the CMOS driving circuits 70A and 70B can also be formed by the thin film transistor 1 of Embodiment 1. 23 βϋ nnn ϋ ninnn · an nn IB1 nn fi J, I Mmm— n flu ϋ I flu · ϋ I Words (please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 503584 A7 —---- B7____ V. Description of the invention (^) ~ Thereby, the power consumption of the electroluminescent display device 300 can be further reduced. In the above configuration examples, although a polydimethylfluorene derivative is used as the electroluminescent material (light-emitting material), other organic materials (for example, other polyfluorene-based materials or polystyrene supports) may be used. Materials), and inorganic materials can also be used. In the first to third embodiments, although the thin-film transistor is made of a top-gate type, it may be formed by sequentially stacking a gate electrode, an insulating film, and a semiconductor film on the substrate. Bottom gate (bottom_gate) type. As can be seen from the above description, it will be apparent to those skilled in the art that there are many improvements and other embodiments of the present invention. Therefore, the above description is only explained as an example, and its purpose is only to teach the provider to implement the best mode of the present invention. Without departing from the spirit of the present invention, substantial changes may be made to the details of its structure and / or function. [Industrial Applicability] The thin film transistor of the present invention is useful as a thin film transistor used in a liquid crystal display device, an electroluminescent display device, and the like. The liquid crystal display device of the present invention is useful as a display portion of a liquid crystal television, a liquid crystal monitor, a liquid crystal information terminal, and the like. The electroluminescence display device of the present invention is useful as a display portion of a television, a monitor, an information terminal, and the like. [Symbol] Γ% Please read the notes on the back before filling in this page> -------- Order --------- Line 1,401 Thin film transistor 11 Substrate 12 Undercoat insulating film 24 Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 503584 A7 B7 25 26 27 28 29 30A, 30B, 70A, 70B 31 V. Description of invention (W) 13 14 16 21 22 24 32 33 34 34a, 34b 35 36 37 39 41 42 43 44 45 46 47 amorphous silicon film semiconductor film gate insulating film pixel electrode orientation film counter electrode color filter liquid crystal polarizing plate storage capacitor liquid crystal capacitor CMOS drive circuit gate source region Drain region interlayer insulation film contact hole source drain LDD region photoresist scan line signal line conductive polymer film polydialkylfluorene derivative film through-hole drive transistor current supply line -------- ----- Φ -------— Order --------- M-01 (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 503584 A7 B7 V. Description of the invention_ (W) 48 49 50 61 200 201 202,302 211 212 300 301 310 311 Cell transparent electrode switching transistor channel area liquid crystal display device liquid crystal panel pixel counter substrate array substrate electroluminescence display device EL display portion glass substrate thin film transistor array substrate --------------- ------ Order —----- line " ^ 1 ^ " (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 Mm)