TW503578B - A novel capacitively coupled DTMOS on SOI - Google Patents

A novel capacitively coupled DTMOS on SOI Download PDF

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Publication number
TW503578B
TW503578B TW090115697A TW90115697A TW503578B TW 503578 B TW503578 B TW 503578B TW 090115697 A TW090115697 A TW 090115697A TW 90115697 A TW90115697 A TW 90115697A TW 503578 B TW503578 B TW 503578B
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Taiwan
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region
source
drain
lightly doped
regions
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TW090115697A
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Chinese (zh)
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Srinath Krjshnan
John C Holst
Bin Yu
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A transistor structure (50) is provided comprising a source region (82, 86) having a N+ source region (82) and a N- lightly doped source region (86). The structure also comprises a drain region (80, 84) having a N+ drain region (80) and a N- lightly doped drain region (84). A P++ heavily doped region (110) is provided. The P++ region (110) resides alongside at least a portion of at least one office N+ lightly doped source region (86) and N- lightly doped drain region (84). A P+ body region (120, 158) resides below a gate (90, 156) of the device (50) and between the source (82, 86) and drain (80, 84) regions. The P++ heavily doped region (110) provides a capacitive coupling between a body region (120, 158) and the gate (90, 156) of the device (50) and form a capacitive voltage divider with the junction capacitance of die device (50).

Description

503578 五、發明說明（1 ) [技術領域] 本發明大體上係關於一種場效應電晶體（FETS)之設 計，尤指一種金屬氧化矽（MOS)電晶體結構配置以運用為 一種動態門限電壓金屬氧化石夕（DTMOS)結構，此結構利於 與習知DTMOS電晶體結構有關之可用電壓限制之緩和。 [背景技術] 如此技藝上眾所皆知，電晶體如金屬氧化砍（Mqs)電 晶體，已形成於半導體本體之隔絕區域如外延層，此外延 層本身係形成於半導體、典型大塊矽、基板上。藉n_通道 MOS場效應電晶體（FET)，本體係呈p-型導電性以及源極 與汲極區域係形成於p_型導電性本體作為N+型導電性區 域。藉p-通道MOSFET，本體或外延層係呈n_型導電性以 及源極與汲極區域係形成於n-型導電性本體作為p+型導電 性區域。已假定半導體本體或層係形成於絕緣基板上或於 形成於半導體基板之絕緣層上。此技術有時稱之為絕緣體 上砍B曰片（SOI)技術。絕緣體上碎晶片技術較大塊秒 MOS電晶體具有多數優點。此等優點包含：減低之源極/ 沒極電容及因而於較高操作頻率下改善之速度性能；減低 之N+至P+間隔及由於隔絕容易因之較高堆積·密度，·以及較 高’’軟誤差”翻轉免疫性（即對阿爾法粒子碰撞效應之免疫 性）。 絕緣體上矽晶片技術特徵在於形成一薄矽層用以於依 序形成於基板上之絕緣層如氧化物上形成作用裝置。於沒 極上之電晶體源極係以例如植入矽層中而形成，而電晶體 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 91847 (請先閱讀背面之注音？事項再填寫本頁} I -------訂--- 經濟部智慧財產局員工消費合作社印製 線—#·^------丨—κ丨丨卜 503578 A7 Γ~------—SI__— 丨丨丨丨丨 … 五、發明說明（2 ) 閘極係以形成圖案氧化物與導電體（例如金屬）層結構而形 成。藉由具有較低寄生電容（由於絕緣體層）及由於浮置體 帶電效應而增加之汲極電流（因通道區域無連接以及浮置 體之帶電提供通路通向大部分載體，該等載體動態地降低 門限電壓，導致增加之汲極電流），使此等結構於性能上提 供顯著增加。然而，浮置體於操作此電晶體時會引入動態 不穩定性。 soi場效應電晶體結合兩個分離之免疫性組，一般以 植入形成，藉由以薄閘絕緣體與導電閘覆蓋之電晶體源極 與汲極管間之一般區域（裝置本體）而組成電晶體之源極與 汲極。通道區域典型為無電性連接以及因此本體係電性浮 動。因源極與汲極區域通常完全延伸過薄矽層，本體之電 位能係以Kirchoff氏電流定律操控，其中流入本體之電流 總合相等於流出本體之電流總合。因通遒位能係取決於本 體電壓，裝置之門限電壓隨本體電壓而變化。 於通道區域及源極與汲極間之邊界分別形成通常逆偏 壓之接面。於通道區域中之傳導通常立即發生於閘絕緣體 之下得以閘極電壓控制損耗之區域内。然而，該等於源極 與没極邊界之接面亦形成寄生侧兩極電晶體，其實際上存 在於場效應電晶體之下及可補充需求之通道電流。另一方 面，寄生侧兩極裝置無法得以控制，並於某些偏壓情形下， 寄生侧兩極裝置之操作可瞬時支配於場效應電晶體之操 作’及有時於通道電流非為所欲時，其可有效佔據大體上 整個砍層。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱p1—-—- 2 91847 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 _ 一 · I n Is «1 n n n^eJ· I n 1 n n n n I 線丨·--------------- A7 五、發明說明（3 , 士胁:裝置轉換時，本體係麵接至裝置之各不同端，因於 、二極間、本體與源極間以及本體極間 各不同端之電壓改變時，本體電壓隨時間而改 變’其依次影響裝晋 裝置之門限電壓。於某些情況下，此關係 。、：置（例如’反相器）。舉例而言，當反相器之閉極 ’、通時’及極放電（其典型為反相器之輸出），因此當閘 極啟通時，；及極電壓則下降。因汲極及本體係彼此電容性 麵接，故當汲極電壓下降時，本體電壓亦同。於本體電壓 與Π限電壓間存有_逆關係。對—NM〇s裝置而言，當本 體電壓下降時，裝置之門限電壓則增加。當本體電壓增加 時門限電壓則減低。因此，當裝置轉換時，汲極及本體 間之電容性耦接導致裝置失去驅動電流。 於SOI電晶體申，缺乏大塊矽或本體對M〇s電晶體 之接觸。於某些裝置中，連接於卜通道M〇SFet中之p-型導電性本體或於p-通道M〇SFET中之.型導電性本體至 固疋電位係為有利。此防止多種與具有相對於接地之本體 電位’’浮置’’有關之滯後效應。藉由大塊矽，MOSFET係相 對地容易因大塊矽之底面得輕易電性連接至固定電位。 SOI裝置亦展現紐結效應，此紐結效應源自碰撞離子 化作用。當SOIMOSFET係操作於相對地大汲極至源極電 壓時’具充足能量之通道電子導致接近於通遒之汲極端之 碰撞離子化作用。產生之電洞建立於裝置本體中，因此提 昇本體電位。增加之本體電位減低MOSFET之門限電壓。 此增加MOSFET之電流並於SOI MOSFET電流對電壓（I-t i a (CNS)A4 ^ (210 x 297¾ )~^~~ (請先閱讀背面之注音？事項再填寫本頁) — -----訂--- 經濟部智慧財產局員工消費合作社印製 i_i I 1 I 1_ n _1 n mmm— §mw n ϋ 1 1 -503578 V. Description of the Invention (1) [Technical Field] The present invention relates generally to the design of a field-effect transistor (FETS), especially a metal silicon oxide (MOS) transistor structure configured for use as a dynamic threshold voltage metal Oxidized oxidized oxide (DTMOS) structure, this structure facilitates the relaxation of the available voltage limitation related to the conventional DTMOS transistor structure. [Background Art] As is well known in the art, transistors such as metal oxide transistors (Mqs) transistors have been formed in isolated areas of the semiconductor body such as epitaxial layers. In addition, the epitaxial layers themselves are formed in semiconductors, typical bulk silicon, On the substrate. By n_channel MOS field effect transistor (FET), the system has p-type conductivity and the source and drain regions are formed in the p_ type conductive body as the N + type conductive region. With a p-channel MOSFET, the body or epitaxial layer is n-type conductive, and the source and drain regions are formed on the n-type conductive body as a p + type conductive region. It has been assumed that a semiconductor body or layer is formed on an insulating substrate or on an insulating layer formed on a semiconductor substrate. This technology is sometimes referred to as the insulator-on-chip (SOI) technology. Larger-second MOS transistors with chip-on-insulator technology have many advantages. These advantages include: reduced source / inverted capacitance and thus improved speed performance at higher operating frequencies; reduced N + to P + spacing and higher packing density due to easy isolation, and higher '' "Soft error" flips immunity (i.e., immunity to the alpha particle collision effect). The silicon wafer on insulator technology is characterized by the formation of a thin silicon layer to form an effective device on an insulating layer such as an oxide formed sequentially on a substrate. The transistor source on Yuji is formed by, for example, being implanted in a silicon layer, and the transistor ^ paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 91847 (Please read the note on the back first? Please fill in this page again for matters} I ------- Order --- Printing Line of Employee Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs— # · ^ ------ 丨 —κ 丨 丨 卜 503578 A7 Γ ~- -----— SI __— 丨 丨 丨 丨 丨 ... 5. Description of the invention (2) The gate is formed by forming a pattern oxide and a conductor (such as a metal) layer structure. By having a lower parasitic capacitance (due to Insulator layer) and increase due to floating body charging effect The pole current (because there is no connection in the channel area and the floating body's charged supply path leads to most carriers, which dynamically reduce the threshold voltage, resulting in increased drain current), which makes these structures provide a significant increase in performance. However, the floating body will introduce dynamic instability when operating this transistor. The soi field effect transistor combines two separate immune groups, which are generally formed by implantation, and are covered by a thin gate insulator and a conductive gate. The general area (device body) between the source and the drain of the crystal constitutes the source and drain of the transistor. The channel area is typically non-electrically connected and therefore the system is electrically floating. Because the source and drain regions are usually completely Extending over the thin silicon layer, the potential of the body can be controlled by Kirchoff's current law, in which the sum of the current flowing into the body is equal to the sum of the current flowing out of the body. Because the potential energy depends on the body voltage, the threshold voltage of the device varies with The body voltage varies. Normally reverse-biased junctions are formed at the channel region and the boundary between the source and drain, respectively. Conduction in the channel region is usually That is, in the area under the gate insulator where the gate voltage can control the loss. However, the interface between the source and the non-polar boundary also forms a parasitic side bipolar transistor, which actually exists under the field effect transistor and Can supplement the required channel current. On the other hand, the parasitic-side bipolar device cannot be controlled, and under certain bias conditions, the operation of the parasitic-side bipolar device can instantly dominate the operation of the field effect transistor 'and sometimes in the channel When the current is not what you want, it can effectively occupy almost the entire cutting layer. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love p1 --- --- 2 91847 (Please read the note on the back first? Please fill in this page for further information) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _ I · Is «1 nnn ^ eJ · I n 1 nnnn I Line 丨 · -------------- -A7 V. Description of the invention (3, Shiwaki: When the device is switched, this system is connected to the different ends of the device. When the voltage between the two poles, between the body and the source, and between the different ends of the body changes. , The body voltage changes with time ' Threshold voltage of the device. In some cases, this relationship. : Set (for example, 'inverter'). For example, when the closed pole of the inverter is turned on, when it is turned on, and the pole is discharged (which is typically the output of the inverter), so when the gate is turned on, the voltage of the pole drops. Since the drain and the system are capacitively connected to each other, when the drain voltage drops, the body voltage is also the same. There is an inverse relationship between the body voltage and the Π limit voltage. For the -NM0s device, when the body voltage decreases, the threshold voltage of the device increases. As the body voltage increases, the threshold voltage decreases. Therefore, when the device is switched, the capacitive coupling between the drain and the body causes the device to lose drive current. For SOI transistors, there is a lack of bulk silicon or bulk contact with Mos transistors. In some devices, it may be advantageous to connect the p-type conductive body in the P-channel MOSFet or the p-type conductive body in the p-channel MOSFET to the solid-state potential. This prevents a variety of hysteresis effects related to having a body potential '' floating 'relative to ground. With a large piece of silicon, the MOSFET is relatively easy to be electrically connected to a fixed potential because of the bottom surface of the large piece of silicon. The SOI device also exhibits a kink effect, which is derived from collision ionization. When the SOIMOSFET is operated at a relatively large drain-to-source voltage, the channel electrons with sufficient energy cause collision ionization near the drain end of the transistor. The generated holes are built in the device body, thus increasing the body potential. The increased body potential reduces the threshold voltage of the MOSFET. This increases the MOSFET current and the SOI MOSFET current-to-voltage (It ia (CNS) A4 ^ (210 x 297¾)) ~ ^ ~~ (Please read the note on the back? Matters before filling out this page) — ----- Order --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs i_i I 1 I 1_ n _1 n mmm— §mw n ϋ 1 1-

關於側兩極作用，若碰撞離子化作用4致多數電洞， 本體偏移可充分提昇致使源極區域至本體p_n接面係順向 偏壓。所得次要載體之放射至本體導致於源極、本體與沒 門之寄生npn雙極電晶體以引致閘極控制對mosfet電 流之損失。 一種對控制浮置體效應及門限電壓之解決方法係為已 知之動愍門限金屬氧化物場效應電晶體（DTM〇s)。當 MOSFET之閘極及本體係電性耦接時，得以達到對正規 MOSFET之大幅改善。除減低之門限電壓及較快轉換次數 外，此等裝置提供於能量消耗上之改善。此優點係為加強 於SOI裝置，其中基座電流及電容係由於非常小接面面積 而明顯減低。然雨，此等裝置係限制於約二極體下降6_ 8 伏特之操作。若電壓上升高於二極體下降，本體至源極及 本體至汲極寄生二極體將開啟以及閘極控制將會失去。此 得以導致自源極至汲極之非常高電流，其可甚至導致裝置 之破壞。 由上述觀點，明顯得知技藝上對裝置之不符需要，其 減輕某些上述關於DTMOS SOI裝置缺點之負效應。 [發明揭示] 本發明提供一種新穎DTMOS裝置及其製法。本發明 之裝置減輕某些上述與DTMOS裝置有關之問題。本發明 之裝置包含汲極與源極區域及輕摻雜之汲極與源極區域 (LDD區域）。該裝置亦包含在汲極與源極區域及LDD區域 itt先閱讀背面之注杳？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 i - * n n n n n ϋ n mi n I n n *1 ^ · ^ — •1--------卜丨 — l· — 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 91847 503578 A7 —___^____ B7 五、發明說明（5 ) 旁之重摻雜區域，彼等皆置於閘極下。重摻雜區域提供 DTMOS裝置之閘極與本體之電容性麵接。電容性耦接與 裝置之接面電容結合以於汲極管與本體間形成電容性電壓 分流器。此提供得以操作DTMOS裝置於.6-.8伏特之能 力，造成增加之轉換速度。此外，於以降低裝置之門限電 壓而轉換裝置中，裝置結構減輕本體電位之下降。如上所 述’本體電位及門限電位係彼此相關，以及藉控制本體電 位，本體電位之下降於轉換中得以減輕。此依序緩和門限 電壓上之變化。 本發明之一方面係關於MOSFET裝置。該裝置包括輕 摻雜源極延伸區域及輕摻雜汲極延伸區域。該裝置進一步 包含重摻雜區域，其位於輕摻雜源極延伸區域及輕摻雜汲 極延伸區域其中之一之至少一部份旁。 本發明之另一方面係關於電晶體裝置，此電晶體裝置 包括具有N+源極區域及ν·輕摻雜源極區域之源極區域。該 結構亦包括具有N+汲極區域及輕摻雜汲極區域之汲極 區域。δ又有P重摻雜區域。該p++區域位於至少輕摻雜 源極區域與Ν-輕摻雜汲極區域其中之一之一部份旁。ρ+本 體區域位於裝置閘極下及於源極與汲極區域間。p#重摻雜 區域提供本體區域與裝置閘極間之電容性耦接，並以裝置 之接面電容形成電容性分壓器。 本發明之又另一方面係關於NMOS裝置，此NMOS裝 置包括形成於頂矽層之Ν+源極及Ν+汲極區域。ρ++重掺雜區 域亦形成於頂矽層。該Ρ++區域具有高於Ν+源極及N+汲極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 經 濟 部 智 財 產 局 員 工 消 費 合 作 社 印 製 I*--·· -_ ·---------.訂----I »----線丨 ^--------------- 91847 ^03578 A7 五、發明說明（6 ) 區域之高摻雜濃度。該P*區域位於至少N+源極及N+汲極 區域其中之_之一部份旁。該p++區域提供本體區域與裝置 之閉極間之電容性耦接，並以裝置之接面電容形成電容性 分壓器。 本發明之另一方面係關於DTMOS裝置。該DTMOS 裝置包括源極區域、汲極區域、閘極區域、本體區域及電 容性系統操作性耦接於閘極區域與汲極區域間。 本發明之又另一方面係關於一種形成M〇SFEt裝置之 方法。於此方法♦，形成輕摻雜源極與汲極區域。形成重 摻雜區域，並位於至少輕摻雜源極及汲極區域其中之一之 至少一部份旁。源極與汲極區域然後係分別形成於鄰近輕 摻雜區域之下。該重摻雜區域具有大於源極與汲極區域及 輕摻雜區域之摻雜濃度，以及重摻雜區域係植入於低於源 極與汲極區域及輕摻雜區域之能量級層。 本發明之另一方面係關於一種形成s〇I NM〇s電晶體 之方法，包括步驟使用SIMOX程序以形成矽基，此矽基 為於基座與頂矽層間之氧化物層。N•輕摻雜源極與汲極延 伸區域係形成於頂矽層。P++重摻雜區域亦形成於頂矽層。 N+源極及N+汲極區域係形成於頂矽層。該區域具有高於 N+區域之摻雜濃度。該！區域位於至少其中一個n+區域之 至少一部份旁。該域提供本體區域與裝置閘極間之電 容性耦接，以裝置之接面電容形成電容性分壓器。 為完成上述及相關目的，本發明遂包括於下文中完全 說明並於申請專利範圍中特定指出之特徵。下述說明及附 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱)----------- 6 91847 (請先閱讀背面之注咅？事項再填寫本頁) wfj i I »§1 An 經濟部智慧財產局員工消費合作社印製 * ί*** •線丨ti-----.ir, 503578 A7Regarding the side bipolar effect, if most of the holes are caused by the collision ionization, the body offset can be sufficiently increased to cause the source region to the body p_n junction to be forward biased. The resulting radiation of the secondary carrier to the body causes parasitic npn bipolar transistors at the source, body, and gate to cause loss of mosfet current by the gate control. One solution for controlling floating body effects and threshold voltages is known as dynamic threshold metal oxide field effect transistors (DTM0s). When the gate of the MOSFET and this system are electrically coupled, a significant improvement on the regular MOSFET can be achieved. In addition to the reduced threshold voltage and faster switching times, these devices provide improvements in energy consumption. This advantage is enhanced by the SOI device, in which the base current and capacitance are significantly reduced due to the very small interface area. However, these devices are limited to approximately 6-8 volt drop operation of the diode. If the voltage rises above the diode drop, the body-to-source and body-to-drain parasitic diodes will turn on and the gate control will be lost. This can lead to very high currents from the source to the drain, which can even cause damage to the device. From the above point of view, it is clear that the technically inconsistent requirements for the device alleviate some of the above-mentioned negative effects of the disadvantages of the DTMOS SOI device. [Disclosure of the Invention] The present invention provides a novel DTMOS device and a manufacturing method thereof. The device of the present invention alleviates some of the above-mentioned problems associated with DTMOS devices. The device of the present invention includes a drain and source region and a lightly doped drain and source region (LDD region). The device is also included in the drain and source regions and the LDD region. Itt read the note on the back first? Please fill in this page for further information) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs i-* nnnnn ϋ n mi n I nn * 1 ^ · ^ — • 1 -------- 卜 丨 — l · — This paper The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 91847 503578 A7 —___ ^ ____ B7 V. Description of the invention (5) The heavily doped regions beside (5) are placed under the gate. The heavily doped region provides a gate connection of the DTMOS device to the capacitive surface of the body. The capacitive coupling is combined with the interface capacitance of the device to form a capacitive voltage shunt between the drain and the body. This provides the ability to operate DTMOS devices at .6-.8 volts, resulting in increased conversion speed. In addition, in switching the device by reducing the threshold voltage of the device, the device structure reduces the drop in the potential of the body. As mentioned above, 'the body potential and the threshold potential are related to each other, and by controlling the body potential, the decrease of the body potential is reduced during conversion. This in turn eases changes in the threshold voltage. One aspect of the invention relates to a MOSFET device. The device includes a lightly doped source extension region and a lightly doped drain extension region. The device further includes a heavily doped region located next to at least a portion of one of the lightly doped source extension region and the lightly doped drain extension region. Another aspect of the present invention relates to a transistor device including a source region having an N + source region and a ν · lightly doped source region. The structure also includes a drain region having an N + drain region and a lightly doped drain region. δ has P heavily doped regions. The p ++ region is located next to at least one of a lightly doped source region and an N-lightly doped drain region. The ρ + body region is located under the device gate and between the source and drain regions. The p # heavily doped region provides a capacitive coupling between the body region and the device gate, and forms a capacitive voltage divider with the device's junction capacitance. Another aspect of the present invention relates to an NMOS device. The NMOS device includes an N + source and an N + drain region formed on a top silicon layer. A p ++ heavily doped region is also formed on the top silicon layer. The P ++ area has higher than N + source and N + drain. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau I *-·· -_----------. Order ---- I »---- line 丨 ^ -------- ------- 91847 ^ 03578 A7 V. Description of the invention (6) High doping concentration in the region. The P * region is located next to at least one of the N + source and N + drain regions. The p ++ region provides a capacitive coupling between the body region and the closed pole of the device, and forms a capacitive voltage divider with the device's junction capacitance. Another aspect of the invention relates to a DTMOS device. The DTMOS device includes a source region, a drain region, a gate region, a body region, and a capacitive system operatively coupled between the gate region and the drain region. Yet another aspect of the present invention relates to a method for forming a MOSFEt device. In this method, lightly doped source and drain regions are formed. A heavily doped region is formed next to at least a portion of at least one of the lightly doped source and drain regions. The source and drain regions are then formed under adjacent lightly doped regions, respectively. The heavily doped region has a higher doping concentration than the source and drain regions and the lightly doped region, and the heavily doped region is implanted in an energy level layer lower than the source and drain regions and the lightly doped region. Another aspect of the present invention relates to a method for forming a SOI NMOS transistor, including the step of using a SIMOX process to form a silicon base, the silicon base being an oxide layer between a base and a top silicon layer. N • lightly doped source and drain extension regions are formed on the top silicon layer. P ++ heavily doped regions are also formed on the top silicon layer. The N + source and N + drain regions are formed on the top silicon layer. This region has a higher doping concentration than the N + region. Yes! The region is located next to at least a portion of at least one of the n + regions. This domain provides a capacitive coupling between the body area and the gate of the device, forming a capacitive voltage divider with the junction capacitance of the device. In order to achieve the above and related objectives, the present invention then includes features that are fully explained below and specifically pointed out in the scope of the patent application. The following descriptions and attached paper sizes are applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 public love) ----------- 6 91847 (Please read the note on the back? Matters before filling in this Page) wfj i I »§1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * ί *** • line 丨 ti-----.ir, 503578 A7

五、發明說明（7 ) 圖仔細闡述某些本發明之說明實施例。此等實施例係為指 示性，然而，亦可採用某些未悖離本發明範疇之變化方式。 本發明其他目的、優點及新穎特點將自下述本發明之仔細 說明配合附圖而闡明。 [圖式簡單說明] 第1圖為本發明之DTMOS SOI結構之側面剖視示意 rm · 圖， 第2圖為本發明第1圖中沿a-A線之DTMOS SOI結 構之側面剖視示意圖； 第3圖為本發明第1圖中沿b_b線之DTMOS SOI結 構之侧面剖視示意圖； 第4圖為本發明第1&至ic圖之DTMOS SOI結構之 等效電路之示意圖； 第5圖為示本發明第u至ic圖之DTMOS SOI結構 之閘電壓對時間之圖示； 第6圖為示本發明第ia至if圖之DTMOS SOI結構對 應於示於第3圖之閘極電壓之本體電壓對時間之圖； 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注音？事項再填寫本頁) 第7圖為本發明之SOI基板之剖面示意圖； 第8圖為本發明第7圖具有墊片氧化物層及氮化物層 形成於其上之SOI基板之剖面示意圖； 第9圖為本發明第8圖具有隔絕區域形成於其中之結 構之剖面示意圖； 第1 〇圖為本發明第9圖具有淺隔絕溝形成於隔絕區域 之結構之剖面示意圖； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 91847 503578 A7 "" -—--^^ 五、發明說明（8 ) f 11 Π)圖具有氧化物層形成於其上以 填充隔絕溝之結構之剖面示意圖； 第12圖為本發明第„圖於氧化物層已研磨降至氮化 物層表面後之結構之剖面示意圖； _第13圖為本發明第12圖於氮化物層、塾片氧化物層 及氧化物層部分已蝕刻去除後之結構之剖面示音圖； 第14圖為本發明第13圖歷經離子碰撞步驟以形成卜 型本體區域之結構之剖面示意圖； 第15圖為本發明第14圖歷經離子碰撞步驟以形成重 摻雜區域之結構之剖面示意圖； 第16圖為本發明第15圖於歷經離子植入步驟以形成 重摻雜區域後之結構之剖面示意圖； 第17圖為本發明第i 6圖具有形成於隔絕溝間基板表 面上之薄低介電常數閘極氧化物質之結構之剖面示意圖； 第18圖為本發明第17圖於形成閘極後之結構之剖面 不意圖， 第19圖為本發明第1 8圖歷經離子植入步驟以形成 源極/沒極（S/D)輕摻雜區域之結構之剖面示意圖； 第20圖為本發明第19圖於歷經離子植入步驟以形成 N-源極/汲極（S/D)輕摻雜區域後之結構之剖面示意属； 第21圖為本發明第2〇圖於形成間隔器後之結構之剖 面示意圖； 第22圖為本發明第21圖歷經離子植入步驟以形成源 極及汲極區域之結構之剖面示意圖； (請先閱讀背面之注意事項再填寫本頁) # 經濟部智慧財產局員工消費合作社印製 ^-------------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 8 91847 基座 五、發明說明（9 ) 第2 3圖為本發明繁9 抓 弟2圖於歷經離子植入步驟以形成 源極及汲極區域後之結構之剖面示意圖； 第24圖為本發明第23圖於結構上形成氧化物層後之 結構之剖面示意圖；以及 第25圖為本發明第24圖於氧化物層已研磨降至閘極 表面水平後之結構之剖面示意圖。 [元件符號說明] 5〇 電晶體結構 6〇 介電層（矽氧化物層） (請先閲讀背面之注意事項再填寫本頁) # 64 70 頂矽層 80 - 84汲極區域 82 ^ 86源極區域 84 N_輕摻雜汲極區 86 >1_輕摻雜源極區域 90 - 156閘極 92 間隔器 94 n-型通道 100 閘極氧化物層 110 P++重摻雜區域 120 '158 P+本體區域 140 MOSFET 144 源極 146 電容 150 接觸點 152 汲極 160 墊片氧化物層 162 氮化物層 168 隔絕區域 170 槽（隔絕區域） 174 、230氧化物質 180 摻雜劑 190 、200、210 步驟 [發明實施型態] 一·-- - 訂-------- •線— ----------- 本發明係關於一種MOSFET裝置結構，此MOSFET 裝置結構利於緩和接面電容及/或浮置體效應，以及其製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 9 91847 503578 A7 B7 五、發明說明（10 ) 法。本發明之MOSFET裝置，相較於許多習知MOSFET 裝置，展現較快性能、較低能量消耗及較少裝置滯後現象。 本發明藉提供MOSFET裝置之閘極區域與本體區域電容性 耦接以配置如動態門限金屬氧化物場效應電晶體（dtm〇s) 之裝置而完成。電容性耦接係以裝置之接面電容而形成電 容性分壓器以使裝置得以操作於6_·8伏特之上。本發明現 將以參考附圖而說明，其中全文以相似數字標記用以標示 相似元件、雖本發明係主要以SOI MOSFET裝置結構而加 以說明，但本發明亦可採用大塊M〇SFET裝置結構。需了 解’本發明之說明於此僅為說明之用，並非為限制之意。 第1圖為本發明之SOI MOSFET裝置結構50越過中 心區域之側面剖視圖。該裝置結構50包含基座6〇，例如 包括碎。該基座60對裝置結構5〇提供機械支撐，並呈適 當厚度以提供此支撐。介電層64(例如Si〇2、Si3N4)係形成 於基座60上。介電層64之厚度係較佳為於1000埃（a) 至5000埃範圍内。一頂矽層7〇示形成於介電層64上，且 頂石夕層較隹具有厚度於500埃至200〇埃範圍内。頂石夕層 70成為用以製造裝置之作用區域。裝置結構50包含閘極 90及η-型通道94(第2圖），以及形成於閘極90與通道94 間之閘極氧化物層100。氧化物層230作用以保護裝置50 免於污染物等。 第2圖為本發明第1圖中沿a-A線之SOI MOSFET裝 置結構50之剖視圖。該裝置結構5〇係為nmos型裝置， 且進一步包含N+汲極區域80、N+源極區域82、N-輕掺雜 (請先閱讀背面之注意事項再填寫本頁) # 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格⑽x 297公餐） 10 91847 A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（U ) 汲極延伸區域84及N_ 广丄 ^輕摻雜源極延伸區域86 〇於及描 區域80與輕換辘n 及極 ，極延伸區域84、及N+源極區域82 以及1ST輕掺雜源極延伸 Λ 、伸£域86旁有一重摻雜區域 1〇(見第1及3圖）。第3岡-丄 圖不第1圖中沿Β_Β線之裝置結 構50之剖視圖。重摻输F w t Λ 里镠雜&域110形成於閘極9〇與本 間< 電容’其麵接閉極90至本體12〇，並以裝置之電容接 面形成電容性分壓器。重摻雜區域】1〇亦利於裝置別之浮 置體效應之電壓控制（例如紐結效應及滯後效應）。如見於 第1圖，重摻雜严區域110運作於閘極90下於電晶體Ν+ 及極區域80及Ν輕摻雜没極延伸區域84旁。重接雜ρ* 區域110亦運作於閘極9〇下於電晶體N+源極區域82及乂 輕摻雜源極延伸區域8 6旁。 降低源極/汲極區域之摻雜濃度減少於汲極/本體與源 極/本體介面間之接面電容。接面電容係關於形成接面之區 域之捧_，如得見於下式：Cj = A[(qe /2(v〇-v)) (NaNd>^^^))] 1/2其中A示汲極/本體與源極/本體介面之 剖面分別示源極及汲極區域中之施體數，及^示 本體中之受體數。 重掺雜區域係以P+型摻雜劑（例如硼）摻雜，並於摻雜 濃度高於源極/汲極區域80、82及P+本體區域12〇之N+摻 雜濃度情形下。結果，重掺雜區域110形成於閘極9〇與本 體120間之電容，其耦接閘90至本體120,並用以作為分 壓器。此使NMOS裝置得於電壓高於依二極體下降者之情 形下使用為DTMOS裝置。 適用中國國家標準（CNS)A4規格（210 X 297公釐 91847 n » I 蜃 如0. n I I / I n n I I I 1 n n I n n n n n n n n n (請先閱讀背面之注意事項再填寫本頁) A7 A7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 12 五、發明說明（12 ) 於本發明之一特定實施例中，重摻雜區域11〇較佳包 含具有劑量於1x10"至lxl〇2〇原子/平方公分範圍内之硼植 入於約IKeV至約100KeV之能量範圍。輕摻雜源極/汲極 延伸區域包含具有劑量於1x1014至1x1016原子/平方公分範 圍内之砷植入並植入於約50KeV至約2〇〇KeV之能量範 圍。源極及汲極區域80、82包含具有劑量於1><1017至lxlol7 原子/平方公分範圍内之砷或構植入於約5〇Kev至约 200KeV之能量範圍。任何適當劑量及能量範圍及植入可 採用以實施本發明。P-型本體12〇包含一具有劑量於1χ1〇10 至ΙχΙΟ14原子/平方公分範圍内之ρ+植入（例如硼）。 第4圖示SOI MOSFET結構50之等效電路圖。該均 等電路包含具有閘極區域156、本體區域158、源極144 及波極B2之MOSFET140。標示為Cdt電容146係藉接 觸點150自本體區域158連接至閘極區域156。電容146 與MOSFET 140之接面電容q結合以形成分壓器於施用於 MOSFET 140閘極區域之電壓與MOSFET結構50本體區 域1 5 8之電壓位準間。於本體區域！ 5 8之電壓位準係與施 用於閘極區域156之電壓成正比，並以下式控制： Δ vb = (Cdt/Cd/Cj)* AVg 其中Cj係MOSFET 140之接面電容。第5、6圖示％與 VB對時間之關係，而vB(max)係與VG成正比但小於vDD， 如以示於上式之電容性比例測定之。 現轉視第7至25圖，探討與形成第1圖結構50有關 之製造步驟。第7至16圖示如示於第2圖之後視剖面及第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91847 ----------------^^1------- ^---------^ — ----------- (請先M讀背面之注音？事項再填寫本頁)V. Description of the invention (7) The figure illustrates some illustrative embodiments of the invention in detail. These examples are illustrative, however, some variations that do not depart from the scope of the present invention may be used. Other objects, advantages and novel features of the present invention will be explained from the following detailed description of the present invention in conjunction with the accompanying drawings. [Brief description of the drawings] FIG. 1 is a schematic side sectional view of the DTMOS SOI structure of the present invention, FIG. 2, and FIG. 2 is a schematic side sectional view of the DTMOS SOI structure of FIG. 1 along the line AA; The figure is a schematic side sectional view of the DTMOS SOI structure along the b_b line in the first figure of the present invention; the fourth figure is a schematic diagram of the equivalent circuit of the DTMOS SOI structure of the first & Inventive diagram of gate voltage vs. time of the DTMOS SOI structure of the u-ic diagram of the invention; Fig. 6 is a diagram showing the DTMOS SOI structure of the ia to if diagram of the invention corresponding to the body voltage pair of the gate voltage shown in the diagram of Fig. 3 Time chart; printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the note on the back? Matters before filling out this page) Figure 7 is a schematic cross-sectional view of the SOI substrate of the present invention; Figure 8 is the 7th figure of the present invention A schematic cross-sectional view of a SOI substrate having a pad oxide layer and a nitride layer formed thereon; FIG. 9 is a schematic cross-sectional view of a structure having an isolation region formed therein in FIG. 8 of the present invention; Figure 9 has a shallow isolation trench formed in the isolated area Schematic cross-sectional view of the paper; This paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) 7 91847 503578 A7 " " --------- ^ V. Description of the invention (8) f 11 Π) Fig. 12 is a schematic cross-sectional view of a structure having an oxide layer formed thereon to fill an isolation trench; Fig. 12 is a cross-sectional view of the structure of the present invention after the oxide layer has been ground down to the surface of the nitride layer; Fig. 13 Figure 12 is a cross-sectional view of the structure of the nitride layer, the etched oxide layer, and the oxide layer portion of the present invention after being etched away; Figure 14 is the ion collision step of Figure 13 of the present invention to form a blob A schematic cross-sectional view of the structure of the body region; FIG. 15 is a schematic cross-sectional view of the structure of FIG. 14 through the ion collision step to form a heavily doped region; FIG. 16 is a cross-sectional view of the invention in FIG. A cross-sectional view of a structure after a heavily doped region; FIG. 17 is a cross-sectional view of a structure having a thin low-dielectric-constant gate oxide material formed on the surface of an isolation trench substrate in FIG. this It is clear that the cross-section of the structure after the gate electrode is formed in FIG. 17 is not intended, and FIG. 19 is a structure of the light-doped region of source / non-polar (S / D) after undergoing the ion implantation step in FIG. 18 of the present invention. Figure 20 is a schematic sectional view of the structure of Figure 19 after the ion implantation step to form a lightly doped N-source / drain (S / D) region in Figure 19; Figure 21 is the invention Figure 20 is a schematic sectional view of the structure after the spacer is formed; Figure 22 is a schematic sectional view of the structure of the source and drain regions after the ion implantation step of Figure 21 of the present invention; (Please read the note on the back first Please fill in this page for further information) # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ -------------- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) ) 8 91847 Base 5. Description of the invention (9) Figure 2 3 is a schematic cross-sectional view of the structure of Figure 9 of the invention after capturing the second figure through the ion implantation step to form the source and drain regions; Figure 24 is FIG. 23 is a schematic cross-sectional view of a structure after an oxide layer is formed on the structure; and FIG. 25 The present invention is an oxide layer 24 in FIG reduced schematic cross-sectional structure of the polished rear surface level of the gate electrode. [Explanation of component symbols] 50 transistor structure 60 dielectric layer (silicon oxide layer) (Please read the precautions on the back before filling this page) # 64 70 Top silicon layer 80-84 Drain region 82 ^ 86 source Electrode region 84 N_lightly doped drain region 86 > 1_lightly doped source region 90-156 gate 92 spacer 94 n-type channel 100 gate oxide layer 110 P ++ heavily doped region 120 '158 P + body area 140 MOSFET 144 source 146 capacitor 150 contact point 152 drain 160 pad oxide layer 162 nitride layer 168 isolation region 170 slot (isolation region) 174, 230 oxide substance 180 dopant 190, 200, 210 steps [Invention implementation type] One ----order -------- • line --------------- The present invention relates to a MOSFET device structure, and the MOSFET device structure is beneficial to ease the connection Area capacitance and / or floating body effect, and the paper size of the paper are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm 9 91847 503578 A7 B7) 5. Description of the invention (10) method. The MOSFET device of the present invention, Compared with many conventional MOSFET devices, it exhibits faster performance, lower energy consumption and The device lag phenomenon is reduced. The present invention is completed by providing a capacitive coupling between a gate region and a body region of a MOSFET device to configure a device such as a dynamic threshold metal oxide field effect transistor (dtm0s). The capacitive coupling is based on The capacitive connection of the device forms a capacitive voltage divider to enable the device to operate above 6-8 Volts. The present invention will now be described with reference to the drawings, in which the full text is marked with similar numbers to indicate similar components, although The invention is mainly explained by the SOI MOSFET device structure, but the present invention can also adopt a large MOSFET device structure. It should be understood that the description of the present invention is for illustration purposes only, and is not intended to be limiting. Figure 1 This is a side cross-sectional view of the SOI MOSFET device structure 50 across the center of the present invention. The device structure 50 includes a base 60, such as a chip. The base 60 provides mechanical support to the device structure 50 and is provided with an appropriate thickness to provide this. Support. A dielectric layer 64 (such as Si02, Si3N4) is formed on the base 60. The thickness of the dielectric layer 64 is preferably in the range of 1000 angstroms (a) to 5000 angstroms. A top silicon layer 70 Show On the dielectric layer 64, the top stone layer has a thickness in the range of 500 angstroms to 200 angstroms. The top stone layer 70 becomes an active area for manufacturing a device. The device structure 50 includes a gate electrode 90 and η- And a gate oxide layer 100 formed between the gate electrode 90 and the channel 94. The oxide layer 230 functions to protect the device 50 from contaminants and the like. Fig. 2 is a sectional view of the SOI MOSFET device structure 50 taken along line a-A in Fig. 1 of the present invention. The device structure 50 is a nmos device, and further includes an N + drain region 80, an N + source region 82, and N-light doping (please read the precautions on the back before filling out this page) # Ministry of Economic Affairs Intellectual Property Bureau Printed by employee consumer cooperatives. The paper size is in accordance with Chinese National Standard (CNS) A4 size ⑽x 297 meals. 10 91847 A7 A7 Printed by the employee consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The lightly doped source extension region 86 and the light trace region 80 are interchanged with the lightly doped n and pole regions, the pole extension region 84, and the N + source region 82, and the 1ST lightly doped source extension region Λ and 86. There is a heavily doped region 10 next to it (see Figures 1 and 3). Fig. 3 is a cross-sectional view of the device structure 50 along the line B_B in Fig. 1. The doped & domain 110 of the re-doped F w t Λ is formed between the gate electrode 90 and the local < capacitor ', whose surface is connected to the closed electrode 90 to the body 120, and a capacitive voltage divider is formed by the capacitive interface of the device. The heavily doped region] 10 is also beneficial for voltage control of other floating body effects in the device (such as kink effect and hysteresis effect). As shown in FIG. 1, the heavily doped severe region 110 operates under the gate electrode 90 next to the transistor N + and the electrode region 80 and the N lightly doped non-electrode extension region 84. The re-doped ρ * region 110 also operates below the gate 90 near the transistor N + source region 82 and the 乂 lightly doped source extension region 86. Reducing the doping concentration in the source / drain region reduces the interface capacitance between the drain / body and the source / body interface. Junction capacitance is about the area where the junction is formed, as seen in the following formula: Cj = A [(qe / 2 (v〇-v)) (NaNd > ^^^)) 1/2 where A is shown The cross sections of the drain / body and source / body interfaces respectively show the number of donors in the source and drain regions, and ^ show the number of acceptors in the body. The heavily doped regions are doped with a P + type dopant (such as boron), and the N + doping concentration is higher than the source / drain regions 80, 82 and the P + bulk region 120. As a result, the heavily doped region 110 is formed between the gate electrode 90 and the body 120, and is coupled to the gate 90 to the body 120 and used as a voltage divider. This allows the NMOS device to be used as a DTMOS device in situations where the voltage is higher than that of a diode drop. Applicable to China National Standard (CNS) A4 (210 X 297 mm 91847 n »I like 0. n II / I nn III 1 nn I nnnnnnnnn (Please read the notes on the back before filling this page) A7 A7 Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Co-operative Society 12 V. Description of the Invention (12) In a specific embodiment of the present invention, the heavily doped region 11 10 preferably contains a dose in the range of 1 × 10 to 1 × 10 2 atoms / cm 2. Boron is implanted in an energy range of about IKeV to about 100KeV. The lightly doped source / drain extension region contains arsenic with a dose in the range of 1x1014 to 1x1016 atoms / cm2 and is implanted at about 50KeV to about Energy range of 200 KeV. The source and drain regions 80, 82 contain arsenic having a dose in the range of 1 < 1017 to 1xlol7 atoms / cm 2 or a structure implanted in the energy of about 50 Kev to about 200 KeV Range. Any suitable dose and energy range and implant can be employed to implement the invention. The P-type body 120 includes a p + implant (eg, boron) having a dose in the range of 1x1010 to 1x1014 atoms / cm2. First 4 shows the equivalent circuit diagram of the SOI MOSFET structure 50. The equal circuit includes a MOSFET 140 having a gate region 156, a body region 158, a source 144, and a wave B2. The Cdt capacitor 146 is marked from the body region 158 by the contact point 150 Connected to the gate region 156. The capacitor 146 is combined with the junction capacitance q of the MOSFET 140 to form a voltage divider between the voltage applied to the gate region of the MOSFET 140 and the voltage level of the MOSFET structure 50 body region 158. Between the body Area! The voltage level of 5 8 is proportional to the voltage applied to the gate area 156 and is controlled by the following formula: Δ vb = (Cdt / Cd / Cj) * AVg where Cj is the junction capacitance of the MOSFET 140. Section 5 , 6 illustrates the relationship between% and VB versus time, and vB (max) is proportional to VG but less than vDD, as measured by the capacitive ratio shown in the above formula. Now turn to Figures 7 to 25, and discuss with The manufacturing steps related to forming the structure 50 in Fig. 1. The diagrams 7 to 16 are shown in the cross section and the paper size as shown in Fig. 2. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. 91847- -------------- ^^ 1 ------- ^ --------- ^------------ (please first M read the Zhuyin on the back ? Matters then fill out this page)

-n n 1· IV I 1 ϋ · A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ :7至25圖示如示於第1圖之前視剖面。第7圖示於其早 /製造時期之基本SGI結構。該結構包切基座60、石夕氧 s 64及頂梦g 7〇。此基本結構係較佳藉(以氧 之植入而分離)程序而形成。SIM〇x程序之基本步驟關於 植入氧於#晶圓表面下。接著進行鍛燒步驟以接合植入之 氧原子至SK)2均勻層。有時，外延之梦可生長—頂石夕以符 口特定裝置需求’但具有或不具有外延層，頂表面膜7〇 成為用於裝置製造之作用區域。埋蔽之氡化物層Μ矽典型 為么0·1至〇·5 並展％幾乎完全植入氧之合併。典型植 入^量範圍自150至200keV，而氧劑量可變化自1至託18 。頂矽膜70厚度與其變化對於氧化物層64厚度係隨 於植入程序中之植入能量與表面矽喷鍍速率而變化。 IMOX程序之第一關鍵步驟為高溫鍛燒。此锻燒係典 型進行於高於1250°C之溫度歷時數小時以接合植入之氧 及自下表面達到頂（表面）矽層7〇之固態再結晶。 第8至13圖示本發明關於M〇SFET結構5〇隔絕區域 之製造程序步驟。此程序係關於淺槽隔絕（STI)，其涉及蝕 刻槽於頂矽層70及以隔絕物質填充該槽。矽之局部氧化 (LOCOS)隔絕程序一般佔用大晶圓表面積，並因此STJ提 供為另一隔絕方法。 第8圖示形成於頂矽層70表面上之墊片氧化物層16〇 及氮化物層162。墊片氧化物層160具有約20〇埃之厚度 並可熱生長於約900。(：之溫度下歷時40分鐘。氮化物層162 係藉化學蒸氣沉積（CVD)程序而沉積於墊片氧化物層16〇 Μ氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I I n. 4 I ! ----- ^--------I 線* ----------^ . (請先閱讀背面之注音？事項再填寫本頁) A7 A7 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 五、發明說明（Μ ) 表面上至约2 0 0 0埃之厘疮。缺从5131 、<厚度然後習知光阻劑程序係利用以 晶格化並敍刻氮化物層162及塾片氧化物層160使得造成 示於第9圖之結構。此光阻劑程序包含使用工光罩，其 界定隔絕區域168。該隔絕區域168係位於基板6〇上夾置 於隨後形成於頂矽層70上之作用區域間之位置。 接著，如示於第10圖，矽蝕刻係進行使淺槽170形成 於頂碎層70之隔絕區域168處。特定言之，槽光阻物質（未 圖示）係施用以覆蓋結構並然後製圖案以暴露出隔絕區域 168。該淺槽17〇然後使用適當方法钱刻於頂梦層7〇。該 槽光阻物質隨後除去使得造成示於第1〇.圖之結構。 藉矽蝕刻形成槽170後，接著使用高密度電漿化學蒸 氣沉積（HDPCVD)形成氧化物質層174於結構上使得以氧 化物質174完全填充隔絕區域17〇如示於第η圖。已知 HDPCVD係自我平面化程序，此程序利於減低用於後續步 驟之化學機械研磨（CMP)次數。（見，例如，pye, j τ等， 用於0.25微米金屬間介電加工之高密度電漿及 CMP，固態技術’ 1995年12月，65_71頁）。氧化物質174 沉積後，接著氧化物質174係藉CMP研磨降至氮化物層 162之表面水平如示於第12圖。因此，槽17〇中之絕緣氧 化物質174餘留。氧化物質174之上表面係實質上平坦於 氮化物層162之上表面。 如示於第13圖，氮化物層162及墊片氧化物層16〇 係使用適當去除程序而去除。該去除程序亦造成氧化物質 174之頂面蝕刻至實質上平於頂矽層7〇之表面。因此，邊 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） <請先閱讀背面之注音？事項再填寫本頁) 1» n n l a— n n^eJ馨MM aaiM I I MMHI 蠢 ϋ n >1 ϋ >1 n n It I n n I n 503578 A7 B7 經 濟 部 智 慧 財 局 員 X 消 費 合 作 社 印 製 五、發明說明（Η 隔絕槽170之形成係實質上於相關技藝上完成。 現轉觀第14至25圖，係說明本發明關於MOSFET裝 置50之το成之程序步驟。雖本發明於文中說明製造nm〇s 裂裝置，本發明亦得施用於多種電晶體裝置包含PMOS型 裝置。本說明將使彼等熟習此技藝者得以實行本發明闕於 多數不同型電晶體裝置，其皆落於本發明以附加之申請專 刺犯圍所界定之範嘴内。 頂矽層70係呈p-型及槽17〇作為隔絕屏障以界定作 用區域。第14圖示p-型本體〗2〇係藉光阻層（未圖示）罩覆 頂石夕層70之一部份及植入井摻雜劑Γ8〇形成而提供p-塑本體120。現轉觀第15圖，第二植入步驟19〇係進行以 植入pw植入於高於步驟19〇之型本體植入之劑量以達成 高摻雜區域110。一特定罩係採用以確保ρ_型植入僅植入 結構於裝置50之特定區域。步驟ι9〇之植入係較佳為 硼於約1x1018至1χ10ΐ9原子/立方公分範圍内之摻雜濃度。 P植入提供MOSFET裝置之閘極區域與本體區域間電容 性耦接以配置裝置為動態門限電壓金屬氧化物場效應電晶 體（DTMOS)。第16圖顯示完成於相關技藝中之裝置5〇之 電容部分。 第17至25圖示形成裝置結構5〇之電晶體部分之前視 剖面如示於第2圖。第17圖示薄閘極氧化物質ι〇〇設置於 頂矽層70之淺槽170間。該薄閘極氧化物質1〇〇係形成以 具有於約<40埃範圍内之厚度。較佳者，薄閘氧化物質1〇〇 包含Si〇2 ’其具有實質上低介電常數。然而，需知可採用 本中目_準（CNS)A4規格（21G x 297公楚）_ (請先閱讀背面之注意事項再填寫本頁) i 訂-------- -線 * *"4^—--------- 15 91847 503578 經濟部智慧財產局員工消費合作社印製 五、發明說明（16 ) 任何適當物質（例如Si#4)以實施本發明，並傾向落於本發 明之範鳴内。換言之，薄閘氧化物質100得早於形成重掺 雜區域110而形成。 之後如第18圖所示，閘極90係形成於薄閘極氧化物 質100上之淺槽17〇間。閘極90係以聚碎製成。閑極9〇 具有於約1000至2000埃範圍内之厚度，以及閘極9〇之厚 度係選取以慮及任何可能進行之後續研磨。需知薄間極氧 化物質100之厚度及閘極90可如需要剪裁，及本發明傾向 包含任何厚度之適當範圍以實施本發明。過多之閘極氧化 物質100如習知者而移除。 第19圖示n_區域第一離子植入步驟2〇〇。採用電容罩 以於η-型植入中保護高摻雜P++區域。使用汴植入2〇〇以 形成η-通道電晶體輕摻雜區域84及86(第2〇圖），其與閘 極90自行定位。於實施例中，此植入步驟可為例如坤植 入，其具有⑽“至原子/平方公分範圍之劑量及約 5〇KeV至約200KeV之能量範圍。需知任何適當劑量與能 量範圍及植入皆可採用以實施本發明。 接著，於植入砰之步驟後，選擇性氮植入可進行作為 部分植入步驟200。可藉植入加入氮至輕摻雜區域料及 86。氮植入可施用於1><1〇14至5xl〇ls原子/立方公分之劑量 與約5〇KeVL約200KeV之能量範圍。需知雖實施例中氣 植入步驟係進行於硼植入後’但氮植入可早於硼植入進 行。 如所示之氮之植入造成減低之争聯電阻及熱載體效應 本紙張尺度適用中國國家標準（CNS)A4規格（21D X 297公髮）'—"---. ................- 16 91847 (請先閱讀背面之注意事項再填寫本頁) -I Ί n n n —9 n n /g· IV n A7 五、發明說明（17 ) 而不會顯著增加S/D延伸重疊。相對於習知刪之製造 2法其中增加摻雜濃度造成較低片電阻，氣植人不會造成 如增加摻雜結果之較深接面。g (請先閱讀背面之注意事項再填寫本頁} 疋敉冰接面另一方面，若砷摻雜劑量係 增加以降低片電阻，則幸交深接 , 則权冰接面產生。較深接面可造成不 良壓延，使]V[〇S裝詈f雞以松也丨, 難U控制’並可能造成穿孔效應。 ‘、、、而’非如習知方法’氮植入造成減低之串聯電阻。因此， 此步驟不會對減低之串聯電阻提供與習知方法相關之負結 果（例如熱電子載體及穿孔效應）。 再者氮植入不會造成任何S/D延伸擴散量之增加至 閘内。當植入提供於S/D延伸區域内，植入不僅垂直散佈， 亦有植人之水平散佈，其即為所謂之S/D延伸重疊至閑 内。相較於習知摻雜，使用氮植入不會造成任何s/d延伸 重疊之增加。 經濟部智慧財產局員工消費合作社印製 植入步驟200後，間隔器92係沿著閘極9〇之侧壁形 成。為完成此步驟，一 Pa1隔器層（未圖示）可形成於頂碎層 7〇上。間隔器層可藉沉積四乙氧基硅烷（TE〇s)氧化物、矽 二氧化物等形成於了_ 70表面上。例如，間隔器然後各 向異性地蝕刻以形成間隔器92於閘極9〇之侧壁上。一蝕 刻劑，選擇性地蝕刻間隔器物質層（例如，以快於頂矽層7 〇 之速率蝕刻間隔器物質），可用以蚀刻間隔器物質層直S至僅 間隔器92餘留於閘90之侧壁如示於第21圖。 形成間隔器92後，另一離子植入步驟21〇係如示於第 22圖進行。採用電容罩以於n_型植入中保護高摻雜區 域。一 N+植入210係進行以分別形成N+源極區域8〇及ν· 表紙張尺度適用中國國家標準（CNS)A4規格(21〇 X 297公爱〉 91847 州）/8 A7 , 五、發明說明（18 ) 汲極區域82(第23圖）於輕推雜 作Λ置以袒罐鈾工处 η切$ °間隔器92 :广保㈣子植八於間隔器92下之輕摻 伤中。此等輕摻雜區域之保護部份 4 ^ ^ Π nn\r- xj^ 〇 〃、裝置50之個別輕摻雜 及極（LDD)區域84及輕摻雜源極（LDs)區域％。 現轉㈣24圖，氧化物層230係沉積於Μ〇_裝 置5〇上。氧化物層230然後以化學機械研磨（CMP)研磨降 至閉極90之表面水平如示於第25圖。氧化物層23〇之上 表面係因此實質上平於閘極9Q之上表面。因此，除暴露之 閘極9。0外’氧化物層230用以完全罩覆M〇SFET裝置。 間隔器92不予以贅述因其為相同於氧化物層23〇之物質。 因此，MOSFET裝置5〇得於相關技藝中完成。 相較於所探討之S0I型裝置，實質上可採用相同製造 方法以製造該η-通道裝置為大塊裝置。熟習此技藝者得基 於此處之探討而輕易修飾上述步驟以形成卜通道裝置，以 及因此進一步相關探討得以簡略。 惟以上所述者，僅係用以說明本發明之具體實施例而 已，需了解舉凡熟習該項技藝者在未脫離本發明所指示之 精神與原理下所完成之一切等效改變或修飾，仍應皆由後 述之專利範圍所涵蓋。 (請先閱讀背面之注音？事項再填寫本頁) I -------訂·丨丨 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 18 91847-nn 1 · IV I 1 ϋ · A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (: 7 to 25 diagrams are shown in the cross section before the first diagram. The seventh diagram is early / The basic SGI structure in the manufacturing period. The structure includes a cut base 60, Shi Xi oxygen s 64, and Dinggeng g 70. This basic structure is preferably formed by (separation by implantation of oxygen) procedures. SIM〇x The basic steps of the procedure are about implanting oxygen under the wafer surface. Then a calcination step is performed to join the implanted oxygen atoms to the SK) 2 uniform layer. Sometimes, epitaxial dreams can grow—Ding Shixi meets the requirements of specific devices' but with or without an epitaxial layer, and the top surface film 70 becomes the area of action for device manufacturing. The buried hafnium layer M silicon is typically from 0.1 to 0.5% and the combination is almost completely implanted with oxygen. Typical implantation amounts range from 150 to 200 keV, while the oxygen dose can vary from 1 to 18 °. The thickness of the top silicon film 70 and its change The thickness of the oxide layer 64 varies with the implantation energy and the surface silicon spray rate during the implantation process. The first key step in the IMOX process is high temperature calcination. This calcination is typically performed at a temperature above 1250 ° C for several hours to join the implanted oxygen and solid state recrystallization from the bottom surface to the top (surface) silicon layer 70. The eighth to thirteenth diagrams illustrate the manufacturing process steps of the present invention with respect to the MOS structure 50 isolation region. This procedure is about shallow trench isolation (STI), which involves etching the trench into the top silicon layer 70 and filling the trench with an insulating substance. The local oxidation of silicon (LOCOS) isolation process typically occupies a large wafer surface area, and therefore STJ offers another method of isolation. FIG. 8 shows a pad oxide layer 16 and a nitride layer 162 formed on the surface of the top silicon layer 70. The pad oxide layer 160 has a thickness of about 200 angstroms and can be thermally grown at about 900 angstroms. (: The temperature lasted for 40 minutes. The nitride layer 162 was deposited on the pad oxide layer by a chemical vapor deposition (CVD) process at a 160-millimeter-scale scale. It is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). %) III n. 4 I! ----- ^ -------- I line * ---------- ^. (Please read the note on the back? Matters before filling out this page ) A7 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (M) on the surface is up to about 2000 angstroms. The thickness is from 5131, < then the conventional photoresist program is used to crystallize The nitride layer 162 and the cymbal oxide layer 160 are etched so that the structure shown in FIG. 9 is created. This photoresist procedure includes the use of a photomask, which defines an isolated area 168. The isolated area 168 is located on the substrate 60. The upper clamp is placed between the action regions that are subsequently formed on the top silicon layer 70. Next, as shown in FIG. 10, the silicon etching is performed so that the shallow groove 170 is formed at the isolation region 168 of the top chip layer 70. Specifically, In other words, a groove photoresist (not shown) is applied to cover the structure and then patterned to expose the isolated area 168. The shallow 17〇 Then the appropriate method is used to engrav the top dream layer 70. The photoresist material of the groove is subsequently removed so as to cause the structure shown in Fig. 10. After the groove 170 is formed by silicon etching, then high density plasma chemical vapor is used. Deposition (HDPCVD) forms an oxide material layer 174 on the structure so that the isolated area 17 is completely filled with the oxide material 174 as shown in Figure n. HDPCVD is known as a self-planarization process, which is beneficial to reduce the chemical machinery used in subsequent steps. Milling (CMP) times (see, for example, pye, j τ, etc., high-density plasma and CMP for 0.25 micron intermetal dielectric processing, solid state technology 'December 1995, pages 65_71). Oxide species 174 deposition After that, the oxidizing substance 174 is reduced to the surface level of the nitride layer 162 by CMP polishing as shown in Fig. 12. Therefore, the insulating oxidizing substance 174 in the groove 170 remains. The surface above the oxidizing substance 174 is substantially flat. On the upper surface of the nitride layer 162. As shown in FIG. 13, the nitride layer 162 and the pad oxide layer 160 are removed using an appropriate removal process. This removal process also causes the top surface of the oxide substance 174 to be etched to Substantially flat on the surface of the top silicon layer 70. Therefore, the paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 meals) < Please read the note on the back first? Matters before filling out this page) 1 »Nnla— nn ^ eJxin MM aaiM II MMHI stupid n > 1 ϋ > 1 nn It I nn I n 503578 A7 B7 Member of the Ministry of Economic Affairs, Smart Finance Bureau X Printed by Consumer Cooperatives 5. Description of the invention (Η Insulation slot 170 of 170 Formation is essentially accomplished in related techniques. Turning now to Figs. 14 to 25, the steps of the invention regarding the το formation of the MOSFET device 50 will be described. Although the present invention is described herein to make a nmos crack device, the present invention may also be applied to a variety of transistor devices including PMOS type devices. This description will enable those skilled in the art to implement the present invention in many different transistor devices, all falling within the scope of the present invention as defined by the appended patent application. The top silicon layer 70 is p-type and the groove 17 is used as an isolation barrier to define an active area. The 14th illustrated p-type body 20 is formed by covering a part of the capstone layer 70 with a photoresist layer (not shown) and the implantation well dopant Γ80 to provide the p-plastic body 120. Turning now to FIG. 15, the second implantation step 19 is performed by implanting pw at a higher dose than the body implant of step 19o to achieve the highly doped region 110. A specific cover is employed to ensure that the p-type implant is implanted only in a specific area of the device 50. The implantation of step ι90 is preferably a doping concentration of boron in the range of about 1x1018 to 1x10ΐ9 atoms / cm3. P implantation provides capacitive coupling between the gate region and the body region of the MOSFET device to configure the device as a dynamic threshold voltage metal oxide field effect transistor (DTMOS). Figure 16 shows the capacitor portion of the device 50 completed in the related art. Figures 17 to 25 show the front cross-sections of the transistor portion forming the device structure 50 as shown in Figure 2. FIG. 17 shows that thin gate oxides ιο are disposed between the shallow grooves 170 of the top silicon layer 70. The thin gate oxide material 100 is formed to have a thickness in a range of about < 40 Angstroms. Preferably, the thin-gate oxidizing material 100 includes SiO2 'which has a substantially low dielectric constant. However, you need to know that you can use this standard _Standard (CNS) A4 specification (21G x 297 Gongchu) _ (Please read the precautions on the back before filling this page) i Order -------- -line * * " 4 ^ —--------- 15 91847 503578 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (16) Any suitable substance (such as Si # 4) to implement the invention, and The tendency falls within the scope of the present invention. In other words, the thin gate oxide material 100 is formed earlier than the heavily doped region 110 is formed. Thereafter, as shown in FIG. 18, the gate electrode 90 is formed in 170 shallow grooves in the thin gate oxide material 100. The gate electrode 90 is made of polymer particles. The idler 90 has a thickness in the range of about 1000 to 2000 Angstroms, and the thickness of the gate 90 is selected to take into account any possible subsequent grinding. It should be noted that the thickness of the thin interpolar oxidizing material 100 and the gate electrode 90 can be tailored if necessary, and the present invention tends to include any suitable thickness range to implement the present invention. Excessive gate oxide material 100 is removed as known. Figure 19 illustrates the first ion implantation step 200 in the n_ region. Capacitor shields are used to protect highly doped P ++ regions in n-type implants. The ytterbium implanted with 200 was used to form n-channel transistor lightly doped regions 84 and 86 (Fig. 20), which were self-localized with the gate 90. In an embodiment, this implantation step may be, for example, a Kun implantation, which has a dose ranging from 至 "to the atom / cm2 range and an energy range of about 50 KeV to about 200 KeV. It is necessary to know any appropriate dose and energy range and planting All can be used to implement the invention. Then, after the implantation step, selective nitrogen implantation can be performed as part of the implantation step 200. Nitrogen can be added to the lightly doped area material and 86. Nitrogen implantation It can be applied at a dose of 1 > < 1014 to 5x10 ls atoms / cubic centimeter and an energy range of about 50 KeV to about 200 KeV. It should be noted that although the gas implantation step is performed after the boron implantation in the examples, but Nitrogen implantation can be performed earlier than boron implantation. As shown in the figure, the nitrogen implantation results in reduced contention resistance and heat carrier effect. This paper is applicable to China National Standard (CNS) A4 (21D X 297). " ---.......- 16 91847 (Please read the notes on the back before filling this page) -I Ί nnn —9 nn / g · IV n A7 V. Description of the invention (17) without significantly increasing S / D extension overlap. Compared to the conventional manufacturing method 2 which increases the doping concentration, The lower the sheet resistance, the air planting will not cause a deeper junction such as increasing the doping result. G (Please read the precautions on the back before filling this page} 疋 敉 Ice junction On the other hand, if arsenic is doped The dose is increased to reduce the sheet resistance. Fortunately, the deep junction, the right ice junction will be generated. The deeper junction can cause poor rolling, so that [V] is not easy to control and difficult to control. Causes the perforation effect. ',, and' not as conventional 'Nitrogen implantation results in reduced series resistance. Therefore, this step does not provide negative results related to conventional methods for the reduced series resistance (eg, thermoelectric carriers) And perforation effect). Furthermore, nitrogen implantation will not cause any increase in the amount of S / D extension diffusion into the gate. When the implantation is provided in the S / D extension area, the implantation not only spreads vertically but also implants horizontally. Dispersion, which is the so-called S / D extension overlap. Compared with the conventional doping, the use of nitrogen implantation will not cause any increase in s / d extension overlap. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs After the implantation step 200, the spacer 92 is along the side wall of the gate 90. To complete this step, a Pa1 spacer layer (not shown) can be formed on the top crush layer 70. The spacer layer can be deposited by depositing tetraethoxysilane (TE0s) oxide, silicon dioxide Is formed on the surface of _70. For example, the spacer is then anisotropically etched to form spacer 92 on the sidewall of gate 90. An etchant selectively etches the spacer material layer (for example, to The spacer material is etched at a faster rate than the top silicon layer 70), and the spacer material layer can be etched until only the spacer 92 remains on the side wall of the gate 90 as shown in Figure 21. After the spacer 92 is formed, Another ion implantation step 21 is performed as shown in FIG. 22. Capacitor shields are used to protect highly doped regions in n-type implants. An N + implantation 210 was performed to form N + source regions 80 and ν. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love> 91847 state) / 8 A7. V. Description of the invention (18) The drain region 82 (Fig. 23) is placed in a light-duty miscellaneous structure, and the uranium can be cut at the uranium cutting site. The spacer 92: Guangbao Xunzi planted in the lightly mixed wound under the spacer 92. The protective portions of these lightly doped regions 4 ^ ^ nn \ r- xj ^ 〇 〃, the individual lightly doped regions (LDD) regions 84 and lightly doped source (LDs) regions of the device 50%. Turning to Figure 24, the oxide layer 230 is deposited on the MO device 50. The oxide layer 230 is then polished by chemical mechanical polishing (CMP) to a surface level of the closed electrode 90 as shown in FIG. 25. The surface above the oxide layer 23 is therefore substantially flat to the surface above the gate 9Q. Therefore, the oxide layer 230 is used to completely cover the MOS device except the exposed gate 9.0. The spacer 92 is not described in detail because it is the same substance as the oxide layer 23. Therefore, the MOSFET device 50 has to be completed in the related art. Compared to the SOI device under discussion, the same manufacturing method can be used to make the n-channel device as a bulk device. Those skilled in the art can easily modify the above steps based on the discussion here to form a channel device, and therefore further related discussions can be simplified. However, the above are only used to explain the specific embodiments of the present invention. It is necessary to understand that all equivalent changes or modifications made by those skilled in the art without departing from the spirit and principles indicated by the present invention, are still They should all be covered by the patent scope mentioned later. (Please read the phonetic on the back? Matters before filling out this page) I ------- Order · 丨 丨 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 Specification (210 X 297 mm) 18 91 847

Claims (1)

503578503578 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1. -種金氧半場效電晶體（M0SFET)裝置州，包括： 輕摻雜源極延伸區域（86)及輕摻雜沒極延伸區域 (84);以及 重掺雜區域（11G)位於輕摻雜源極延伸區域(86)及 輕摻雜汲極延伸區域（84)其中之一之至少一部份旁。 2·如申請專利範圍第Μ之裝置，該重捧雜區域⑴〇)位 於源極區域（82)之至少一部份旁。 3.如申請專利範圍第2項之裝置，該重摻雜區域⑴〇)位 於一汲極區域（80)之至少一部份旁。 4· 一種電晶體裝置（50)，包括： 源極區域，包括Ν+源極區域（82)及Ν-輕掺雜源極 區域（86); 及極區域’包括]没極區域（80)及輕摻雜没極 區域（84); PR重摻雜區域（110)，該P*重摻雜區域（11〇)位於N-輕摻雜源極區域（86)及]ST輕摻雜没極區域（84)其中之一 之至少一部份旁；以及 P+本體區域（120、158)位於裝置之閘極（90、156) 下及於源極（82)與汲極（80)區域間； 其中該P++重摻雜區域（110)提供電容性耦接，以裝 置（50)之接面電容形成電容性分壓器於裝置（5〇)之本體 區域（120、158)與閘極（90、156)間。 5.如申請專利範圍第4項之電晶體裝置，該重摻雜區 域（110)以本體電位耦接閘極電位。 (請先閲讀背面之注意事項再填寫本頁) - 訂--------線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 19 91847 503578 A8 B8 C8 D8 六、申請專利範圍 6· —種N通道金屬氧化半導體（NM0S)裝置（50)，包括： N+源極（82)及N+汲極（80)區域形成於頂矽層（70); 以及 P*重摻雜區域（110)形成於頂矽層，該區域 (110)具有高於N+源極（82)及N+汲極（80)區域之摻雜濃 度’該P*區域（110)位於至少N+源極（82)及N+沒極（80) 區域之至少一部份旁； 其中該P*區域（110)提供電容性耦接於裝置（50)之 本體區域（120、1S8)與閘極（90、156)間，並以裝置（50) 之接面電容形成電容性分壓器。 7· 一種動態門限電壓金氧半場效電晶體（DTMOS)裝置 (5〇)，包括： 源極區域（82、86); 汲極區域（80、84); 閘極區域（90、156); 本體區域（120、158);以及 電容性系統操作性耦接於閘極區域（90、156)與汲 極區域（80、84)之間。 8·如申請專利範圍第7項之裝置，該源極及汲極區域以摻 雜物質而形成，該電容性系統自重摻雜區域而形成，該 重摻雜區域位於至少源極區域及汲極區域之至少一部 份旁。 9· 一種形成金氧半場效電晶體（MOSFET)裝置（50)之方 法，包括下列步驟： (請先閱讀背面之注意事項再填寫本頁) 1敏 --線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 20 91847 503578 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 形成輕掺雜源極（86)及汲極（84)區域； 形成重摻雜區域（110)，至少部份位於至少輕摻雜 源極（86)及汲極（84)區域旁；以及 形成源極（82)及汲極（80)區域分別鄰近輕摻雜區域 (84、86)，該重摻雜區域（110)具有高於源極（82)及汲極 (80)區域與輕摻雜源極（86)及汲極（84)區域之摻雜濃 度，並植入於高於源極（82)及汲極（80)區域與輕摻雜源 極（86)及汲極（84)區域之能量位準。 10.—種形成絕緣矽上金氧半場效電晶體（SOI NMOS)裝置 (50)之方法，包括下列步驟： 使用SIM0X程序以形成矽基座（60)、氧化物層（64) 於該基座（60)與頂矽層（70)間； 形成N·輕摻雜源極（86)及1ST輕摻雜汲極（84)延伸 區域於頂矽層； 形成PH重摻雜區域（110)於頂矽層（70);以及 形成N+摻雜源極（82)及汲極（80)區域，該P#區域 (110)高於N+區域（80、82)之摻雜濃度，該P#區域（110) 位於至少N_輕摻雜源極（86)及1ST輕摻雜汲極（84)延伸區 域之至少一部份旁； 其中該P#區域（110)提供於裝置（50)之本體區域 (120、158)與閘極（90、156)間之電容性耦接，並以裝置 (50)之接面電容形成電容性分壓器。 (請先閱讀背面之注意事項再填寫本頁) -獻 · 線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 21 918476. Scope of Patent Application Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1.-A kind of metal oxide half field effect transistor (MOSFET) device states, including: Lightly doped source extension region (86) and lightly doped anode extension A region (84); and a heavily doped region (11G) are located beside at least a part of one of the lightly doped source extension region (86) and the lightly doped drain extension region (84). 2. If the device in the scope of the patent application is applied for, the re-entrant region (0) is located beside at least a part of the source region (82). 3. If the device according to item 2 of the patent application, the heavily doped region ⑴) is located at least a part of a drain region (80). 4. A transistor device (50), comprising: a source region including an N + source region (82) and an N-lightly doped source region (86); and the electrode region 'including] the non-electrode region (80) And lightly doped region (84); PR heavily doped region (110), the P * heavily doped region (110) is located in the N-lightly doped source region (86) and the ST lightly doped region The P + body region (120, 158) is located under the gate (90, 156) of the device and between the source (82) and the drain (80) regions Wherein, the P ++ heavily doped region (110) provides capacitive coupling, and a capacitive voltage divider is formed by the junction capacitance of the device (50) in the body region (120, 158) of the device (50) and the gate ( 90, 156). 5. The transistor device according to item 4 of the patent application, wherein the heavily doped region (110) is coupled to a gate potential by a bulk potential. (Please read the precautions on the back before filling in this page)-Order -------- Line · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 19 91847 503578 A8 B8 C8 D8 6. Scope of Patent Application 6-A type of N-channel metal oxide semiconductor (NM0S) device (50), including: N + source (82) and N + drain (80) regions formed on the top silicon layer (70); and P * Heavy doped region (110) is formed on the top silicon layer, and the region (110) has a higher doping concentration than the N + source (82) and N + drain (80) regions. The P * region (110) is located at least N + source (82) and N + non-electrode (80) are adjacent to at least a part of the region; wherein the P * region (110) provides capacitive coupling to the body region (120, 1S8) and the gate of the device (50) (90, 156), and use the junction capacitance of device (50) to form a capacitive voltage divider. 7. A dynamic threshold voltage metal-oxide-semiconductor field-effect transistor (DTMOS) device (50), comprising: a source region (82, 86); a drain region (80, 84); a gate region (90, 156); The body region (120, 158); and the capacitive system is operatively coupled between the gate region (90, 156) and the drain region (80, 84). 8. If the device in the scope of patent application No. 7, the source and drain regions are formed by doping substances, the capacitive system is formed by self-doping regions, the heavily doped regions are located at least the source region and the drain region Next to at least part of the area. 9. · A method for forming a metal-oxide-semiconductor field-effect transistor (MOSFET) device (50), including the following steps: (Please read the precautions on the back before filling out this page) Copies printed by the cooperative are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 20 91847 503578 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Apply for patents to form lightly doped sources (86) and a drain (84) region; forming a heavily doped region (110), at least partially located beside at least a lightly doped source (86) and drain (84) region; and forming a source (82) and The drain (80) region is adjacent to the lightly doped region (84, 86), respectively. The heavily doped region (110) has a higher area than the source (82) and the drain (80) region and the lightly doped source (86). And the doping concentration of the drain (84) region, and implanted at higher energy levels than the source (82) and drain (80) regions and the lightly doped source (86) and drain (84) regions . 10. A method of forming a metal-oxide-semiconductor field-effect transistor (SOI NMOS) device (50) on insulating silicon, including the following steps: Use a SIM0X program to form a silicon base (60) and an oxide layer (64) on the base Between the base (60) and the top silicon layer (70); forming N · lightly doped source (86) and 1ST lightly doped drain (84) extended regions on the top silicon layer; forming PH heavily doped region (110) On the top silicon layer (70); and forming N + doped source (82) and drain (80) regions, the P # region (110) having a higher doping concentration than the N + regions (80, 82), the P # The region (110) is located at least a part of at least the N_lightly doped source (86) and the 1ST lightly doped drain (84) extending region; wherein the P # region (110) is provided in the device (50). The body region (120, 158) is capacitively coupled with the gate electrode (90, 156), and a capacitive voltage divider is formed by the junction capacitance of the device (50). (Please read the precautions on the back before filling out this page) -Dedicated · Thread · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 21 91847
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