TW502324B - Structure of a test key for monitoring salicide residue - Google Patents

Abstract

A structure of a test key for monitoring self-aligned silicide (salicide) residues has of a silicon substrate, multiple parallel diffusion regions formed on the silicon substrate, multiple polysilicon lines formed on the silicon substrate, a dielectric layer covering the multiple polysilicon lines and the multiple diffusion regions, and multiple metallic test fingers formed on the dielectric layer. The multiple polysilicon lines are set across the multiple diffusion regions to form multiple contact regions, each contact region having an ion well, in the multiple diffusion regions, and each of the multiple metallic test fingers is orthogonal to the multiple polysilicon lines and electrically connected with each ion well via a contact plug.

Description

502324 V. Description of the invention (1) Field of the invention The present invention provides a test key structure for monitoring self-aligned silicide residues, especially a high-sensitivity test window structure, which can be used to test the acceptability of a wafer. (Wafer acceptance tesi :, WAT) The 'induced' leakage current on the side wall of the unilateral polycrystalline silicon line was measured. Background: In the traditional semiconductor front-end-of-line (FE0L) process, the self-aligning metal silifide (seif — aHgne (j silicide, salicide) process is a process often used to reduce word lines. (Word 1 ine) / gate resistance and source / sour / drain sheet resistance. The conventional self-aligning metal silicide process generally includes the following steps: ( 1) Globally deposit a metal layer such as cobalt or titanium; (2) Perform a thermal process (usually a rapid thermal process) to make the previously deposited metal layer selective The ground reacts with the contacted Shi Xi substrate or the polycrystalline silicon gate to form a metal silicide; and (3) performing a post-cleaning process to wash away the unreacted metal layer. This self-aligning metal silicide process and post-cleaning process method You can refer to US Patent Nos. 6,221,76 6 and 5, 3 1 6, 977, which will not be repeated here. However, the surface of the semiconductor wafer after the cleaning process is still unavailable.

Page 5 502324

Guaranteed to be completely clean without metal residue issues. * If it is thorough enough, the sidewalls I on both sides of the word line will not be sunk by the cleaning process, and it may affect the entire integrated circuit to form induced leakage current. Derived leakage to sub-wavelength (subwavelengttO generation (< 〇), process, reduction of minimum line spacing, metal residue-derived lightning leakage, ^ m), and line spacing efficiency assessment (assess) metal with f efficiency The quality and quality of the silicide process will not be CP0st-c1ean. The effect will be performed after cleaning-the so-called wafer acceptance test (WAT) ° wafer acceptance test ( WAT) basically uses a plurality of test keys formed in a peripheral region of a die to perform electrical tests. The test window is usually formed on a scribe line, and each test window is used to monitor the characteristics of the wafer. The purpose is different, such as threshold voltage, saturated current, and gate. Oxide thickness and leakage current. The test window structure used to monitor the leakage current after the metal silicide process is shown in Figure 1 (a) and Figure 1 (b). Figure 1 (a) and Figure 1 (b) are the layout of the test window for testing the metal residue on the diffusion area and the layout of the test window for testing the metal residue on the polysilicon line sidewall. There are at least two test windows that are conventionally used to monitor the residual residual leakage current of metals after the metal silicide process: the first one, as shown in Figure 1 (a)

Page 6 502324 5. The test window for metal residues on the diffusion region shown in the description of the invention (3) includes a plurality of staggered long diffusion regions 1 2 (also called diffusion test finger ^ iffusi () n test finger)) is formed on the silicon substrate, and the strips are diffused. Between the domains is a shallow trench insulation (shaU〇w trench isolati〇n, T 〇 area 1 4. Part of the long diffused area 2 and a The terminal circuit is electrically connected, and the remaining long diffusion region 12 is electrically connected to the terminal B voltage. For example, a readout circuit is externally connected and is biased by ^ volts, and The B terminal is grounded. When the metal residue ι diffuses on both sides of the diffusion region 12 and accumulates to -degree, when the two adjacent months expand -v, the readout circuit can read a leakage current value. 属 # t ^ b) No, the second is to test the gold line area 22 on the polysilicon line side wall (also can shake several long polycrystalline slabs arranged in the wrong place) on the silicon substrate 10, the long diffusion area Between 22, there is a domain 2 2 and A, and the terminal Lei region 24. Similarly, part of the long polycrystalline silicon line area is the toilet B, and the terminal Lei Lu Road Are connected, and the remaining long polysilicon line region 22 is connected in parallel by T. For example, the terminal A is usually externally connected to a readout circuit (^ ounded). The adjacent long-distance diffusion region 2 2 The two sides accumulate to a certain degree, so that the current value. When the Shi Xi line area 22 is turned on, the readout circuit can read a leak and the shortcomings of the test window layout structure are not sensitive enough. As before

502324 5. According to the description of the invention (4), in FIG. 1 (b), only when the metal residues 2 6 accumulate to a certain extent on both sides of each long diffusion region 2 2, two adjacent polycrystalline silicon line regions 2 2 When it is turned on, the readout circuit connected to the A 'terminal can read a leakage current value. In this case, the conventional test window structure cannot detect the case where there is only a metal object on one side. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a high-sensitivity test window layout structure for sensitively monitoring the residual induced leakage current after cleaning of a metal silicide process. Another object of the present invention is to provide a test window layout to effectively detect the presence of metal objects on one side. According to a preferred embodiment of the present invention, a test key structure for monitoring the residue of self-aligned silicide (salicide) in the present invention includes: a Shixi substrate with at least one first A diffusion region and a second diffusion region are laterally disposed on one side of the first diffusion region; a first polycrystalline silicon line and a second polycrystalline silicon line span the first diffusion region and the second diffusion region And the first polycrystalline silicon line and the second polycrystalline silicon line separate a first contact hole region from the first diffusion region and a second contact hole region from the second diffusion region, respectively. , Wherein the first contact hole region includes a first ion well, and the first

Page 8 502324 V. Description of the invention (5) The second contact hole region includes a second ion well; at least one dielectric layer covers the first polycrystalline silicon line, the second polycrystalline silicon line, the first diffusion region, and On the second contact hole region; and a first metal test finger and a second metal test finger, which are close to orthogonal to the first polycrystalline silicon evening line and the second polycrystalline silicon line, are disposed on On the dielectric layer, and the first metal test finger is electrically connected to the first ion well via a first contact plug; the second metal test finger is electrically connected to the second ion well via a second contact plug; connection. The first polycrystalline silicon line and the second polycrystalline silicon line each have two close-to-vertical sidewalls and a spacer formed on each of the sidewalls. For a detailed description of the invention, please refer to FIG. 2. FIG. 2 is a schematic diagram of a part of the layout of the test window of the present invention. As shown in FIG. 2 'The testkey structure of the present invention 3 0 0 includes a silicon substrate 1 0 0, on which At least a plurality of diffusion regions 100 are horizontally formed on the silicon substrate 100. Between the diffusion regions 102 is an STI region 108. The plurality of first polycrystalline silicon lines 104a and the plurality of second polycrystalline silicon lines 104b span the diffusion region 102 and the ST I region 108. The first polycrystalline silicon line 1 0 4 a and the second polycrystalline silicon line 丨 〇4 b are both concave and convex layout patterns, so as to 'make the first polycrystalline silicon line 1 04a and the second polycrystalline silicon line 1 〇4b can separate a plurality of contact hole areas 1 〇2 from the expansion area 1 〇2, wherein the silicon substrate 100 surface of each contact hole area 〇3 contains an ion well (not shown

^ 2324

Close). Each of the first polycrystalline silicon line 104a and the second polycrystalline silicon line 104b has two sides, and vertical sidewalls and a spacer (not shown) are formed on each side. The implantation of the ion well is performed after the formation of the side wall. The side wall is similar to the general M0S transistor process, and its material is generally made of nitride. In addition, in FIG. 2, the silicon substrate 10 in the contact hole region 103 is equal to the first polycrystalline silicon line 104a and the second polycrystalline silicon line 1041), each of which is a petrochemical layer ( Not shown). In the preferred embodiment of the present invention, the distance between the diffusion regions 102 is about ^ 0.2 microns, and the line width of the first polycrystalline silicon line 104a and the plurality of second polysilicon lines 104b is about 0.12 microns. about. The shortest distance w in the uneven pattern formed by the first polycrystalline silicon line 〇4a and the second polycrystalline silicon line 104b is about 0.2 micron.

The test key structure 300 of the present invention further includes a dielectric layer (not shown) covering the first polycrystalline silicon line 104a, the second polycrystalline silicon line 104b, the diffusion region 102, and the STI. Area 108. The dielectric layer is formed by a conventional chemical vapor deposition (CVD) method after cleaning after the metal silicide process is completed. For example, the dielectric layer may be a silicon dioxide layer, a BPSG layer, a PSG layer, or a low dielectric constant material (FSG, etc.). After the deposition of the dielectric layer is completed, the metal objects 210 a and 210b 'remaining in the post-cleaning process in the test window 300 are coated in the dielectric layer. A first member belongs to the test finger 106a and a second metal test finger i〇6b, which are close to the first polycrystalline silicon line 104a and the second polycrystalline silicon line i04b, which are set in the media

Page 10 502324 V. Description of the invention (7) Electrical layer. The first metal test finger 1 0a and the second metal test finger 1 6 "are electrically connected to the ion well in the contact hole area 1 0 3 by the contact plug 108. The formation of the contact plug 108 and Metal test fingers 丨 〇a and 〇6b are well known to those skilled in the art, so they will not be described again. From the above structural description, it can be seen that the test window 300 of the present invention has a three-layer structure. (Diffusion region 102, polycrystalline silicon lines 〇04a and 〇4b, metal test, 106a and 106b). Therefore, it is necessary to wait until the definition of the first layer of metal wire is completed before performing the metal silicide residual derived leakage current test. When the leakage current monitoring step is performed, the first polycrystalline silicon line 04a and the second polycrystalline silicon line 104b are respectively applied with different voltages: point A and point B. For example, '' 第一 多The crystalline silicon wire 1 〇 4 a is externally connected to an a-point readout circuit and provides a 1.5 volt bias voltage, and the second polycrystalline silicon wire i 〇 4 _ ground. The first metal test refers to 106 and the second metal. The test finger 1061) is applied with different voltages: C and d bias. For example, The first metal test finger 〇〇6 & externally connected to a 2-point readout circuit and provide a 1.5 volt bias, and the second metal test finger 1 06b point D is grounded. Therefore, point AB It can measure the leakage current of unilateral metal residue 2 1 0a, and the CD point can measure the leakage current of unilateral metal residue 2 1 0b. Compared with the conventional test window structure, the present invention has a three-layer structure design Therefore, it is possible to sensitively detect the residual leakage current of a unilateral metal object, especially for the cleaning effect of the metal silicide post-cleaning process.

Page 11 502324 V. Description of the invention (8) The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. lii Page 12 502324 Schematic description of the diagrams Brief description of the diagrams Figure 1 (a) is a partial layout of a test window for testing metal residues on diffusion regions; Figure 1 (b) is a test window for testing metal residues on the side walls of polycrystalline silicon wires Partial layout; Figure 2 is a schematic diagram of a partial layout of the test window of the present invention. Explanation of Symbols _ «

Page 13 10 Cut the substrate 12 Long diffusion region 14 STI region 16 Metal residue 22 Polycrystalline silicon region 24 STI region 26 Metal residue 100 Silicon substrate 102 Diffusion region 103 Contact hole region 104a, b Polycrystalline silicon wire 10 6a, b Metal test finger 108 Contact plug 210a, b Residual metal object 300 Test window

Claims (1)

502324 VI. Scope of patent application1. A testkey structure for monitoring the self-aligned residues of se 1 f-a 1 ignedsi 1 pesticide (sa 1 pesticide). The test window structure includes: a silicon substrate Having at least a first diffusion region and a second diffusion region laterally disposed on one side of the first diffusion region; a first polycrystalline silicon line and a second polycrystalline silicon line spanning the first On the diffusion region and the second diffusion region, and the first polycrystalline silicon line and the second polycrystalline silicon line separate a first contact hole region from the first diffusion region and a second contact region from the first diffusion region; A second contact hole region is isolated, wherein the first contact hole region includes a first ion well, and the second contact hole region includes a second ion well; at least one dielectric layer covers the first polycrystalline silicon line, On the second polycrystalline silicon line, the first diffusion region, and the second diffusion region; and a first metal test finger (testfinger) and a second metal test finger, which are close to orthogonal to the A polycrystalline silicon line and the second polycrystalline silicon line are disposed on the dielectric layer, and the first metal test finger is electrically connected to the first ion well through a first contact plug, and the second metal test finger It is electrically connected to the second ion well through a second contact plug. 2. For example, the test window structure of the first patent application scope, wherein the first polysilicon line and the second polysilicon line each have two close vertical sidewalls and a sidewall sub (s p a c e r) formed on each of the sidewalls. 3. The test window structure as described in the scope of patent application item 2, wherein the side wall Page 14 502324 VI. The scope of patent application is composed of nitride nitride. The test items of the structure window in this section include the base silicon on the bottom surface of each side. Γ e domain ya area 1 hole ed touch 01 first connection 1C IX1411J II. 1 S Fan Dili This layer of speciality please apply for the domain silicon as the area belongs to the gold 4. Touch one by one 5. If the scope of patent application The test window structure of item 1, wherein the test window structure is formed on a scribe line of a wafer. 6. The test window structure according to item 1 of the patent application scope, wherein the first diffusion region and the second diffusion region are separated by a shallow low trench isolation (STI) region. 7. For example, the test window structure of the first patent application scope, wherein the first metal test finger and the second metal test finger are externally connected to a test circuit for measuring a metal silicide residue-derived leakage current. 8. A test window array, the test window array comprising: a broken substrate; a plurality of columns of diffusion regions are disposed parallel to each other on the surface of the silicon substrate; a plurality of rows of polycrystalline silicon lines span the plurality of columns of diffusion regions, and The plurality of rows of polycrystalline silicon lines separate the plurality of columns of diffusion regions from a plurality of contact hole regions, wherein each of the contact hole regions includes an ion well; a dielectric layer covers the plurality of rows of polycrystalline silicon lines and the plurality of columns of diffusion regions. Page 15 502324 6. The scope of the patent application; and a plurality of metal test fingers arranged on the dielectric layer, and each of the metal test fingers is electrically connected to each of the ion wells through a contact plug. 9. The test window array according to item 8 of the patent application, wherein each of the polysilicon lines has two near vertical side walls and a side wall is formed on each of the side walls. 10. The test window array according to item 9 of the patent application scope, wherein the side wall is composed of silicon nitride. 1 1. The test window array according to item 8 of the patent application, wherein the surface of the silicon substrate in each of the contact hole areas includes a metal silicide layer. 1 2. The test window array of item 8 in the scope of patent application is formed on the scribe line of a wafer. 1 3. The test window array according to item 8 of the patent application scope, wherein the plurality of columns of diffusion regions are separated by a shallow trench insulation (ST I) region. 1 4. The test window array according to item 8 of the patent application scope, wherein the plurality of rows of metal test fingers are close to orthogonal to the plurality of rows of polycrystalline silicon lines. I m Page 16