502145 A7 B7 五、發明説明（1 ) (發明之背景） 本發明係關於一種系統電路基板，及使用它之電腦系 統與電子機器，尤其是關於適用於高速記憶體之實裝的系 統電路基板，及使用它之電腦系統與電子機器。 近年來，在個人電腦等之電腦系統中。爲了提昇系統 性能，而進行記憶速度之改善。一般，記億速度係比 c P U速度慢。因此，雖使用高速C P U，記憶速度成爲 瓶頸，而無法進行提高充分之系統性能。爲了改善該現象 ，進行高速記憶體之開發，使用作主記憶之記憶元件係從 D R A M ( Dynamic Random Access Memory )至具 E D 〇 (Extended Data Out DRAM )模態之 D R A M，同步 DRAM，在最近開始使用Rambus公司之Rambus DRAM 等之高速記憶元件。 隨著此種記憶元件之高速化技術，系統基板上之記憶 存取之循環時間也年年被高速化，在現在須設計約4百 Μ Η z之高速記憶匯流排。在使用此種高速記憶匯流排時 ，爲了防止信號之反射等所產生之不方便，成爲須謀求嚴 密之阻抗匹配。 如此，在使用同步D R A Μ之習知之電腦系統中，事 先準備複數記憶體實裝區域於系統電路基板（稱爲母基板 )^視需要可將必需個數之iH憶體貫裝於區域加以使用。 此乃母板爲共通，而在每一製品製作改變實裝記憶電容之 系統上極方便之方法。由於在每一製品不必重新設計母板 ，因此也可減低成本。 本紙張尺度適用中國國家標準（CNS〉Α4規格（210X 297公釐） 請 先 閲 讀 背 I 事 項502145 A7 B7 V. Description of the invention (1) (Background of the invention) The present invention relates to a system circuit board, and a computer system and an electronic device using the same, and particularly to a system circuit board suitable for high-speed memory mounting. And computer systems and electronic machines using it. In recent years, in computer systems such as personal computers. In order to improve the system performance, the memory speed is improved. In general, the speed of recording billions is slower than c P U. Therefore, although high-speed CPU is used, the memory speed becomes a bottleneck, and it is impossible to improve the sufficient system performance. In order to improve this phenomenon, the development of high-speed memory is carried out. The memory elements used as the main memory are from DRAM (Dynamic Random Access Memory) to DRAM with ED (Extended Data Out DRAM) mode. Synchronous DRAM has recently been used. Rambus DRAM and other high-speed memory components. With the high-speed technology of such memory elements, the cycle time of memory access on the system substrate has also been increased year by year. Now, it is necessary to design a high-speed memory bus of about 400 MHz. When using such a high-speed memory bus, in order to prevent inconvenience caused by signal reflection, etc., it is necessary to seek strict impedance matching. In this way, in a conventional computer system using synchronous DRA M, a plurality of memory mounting areas are prepared in advance on a system circuit board (referred to as a mother substrate). If necessary, a necessary number of iH memories can be installed in the area for use . This is a common method for the motherboard, and it is a very convenient method for changing the installed memory capacitor for each product. Because there is no need to redesign the motherboard in each product, it can also reduce costs. This paper size applies to Chinese National Standards (CNS> Α4 size (210X 297mm)) Please read the following I
Η I I 訂 經濟部智慧財產局員工消費合作社印製 -4- 502145 A7 _____ B7 五、發明説明（2 ) 然而’在被要求嚴密之阻抗匹配的高速記憶系統中， 成爲也必需考慮記憶體本體之負荷電容。藉由記憶體之實 裝個數使記憶體之負載電容變化，結果，會使記憶匯流排 線之負荷阻抗變化。因此’在所有記憶體實裝區域有實裝 記憶時，或在記憶體實裝區域有空時，則記憶匯流排線之 負荷阻抗會不相同，成爲無法得到嚴密之阻抗匹配。因此 使用高速記憶匯流排時，則實際上難利用隨著需要實裝需 要個數之記憶體加以使用之上述方法。 (發明之槪要） 本發明係鑑於上述事項而創作者，其目的係在於提供 一種未依據實裝之記憶元件個數可將記憶匯流排線之負荷 阻抗設定在規定値，不必在每一製品重新設計系統電路基 板’而視需要可將需要個數之記憶體加以實裝並使用的系 統電路基板，及使用它之電腦系統與電子機器。 本發明之系統電路基板，其特徵爲具備： 經濟部智慧財產局員工消費合作社印製 設於記憶匯流排線上，用以實裝複數記憶元件的記憶 體貫裝區域’及 將用以補償依記憶元件之實裝個數之變化所產生之記 憶匯流排線之負荷阻抗之變化的電容性元件連接於記億匯 流排線的連接端子。 本發明之系統電路基板，係藉將隨著記憶元件之實裝 個數之電容値的電容性元件連接於記憶匯流排線，可補償 依記憶元件之實裝個數之變化所產生的記憶匯流排線之負 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） 一 " 讎5- 502145 A7 B7 五、發明説明（3 ) 荷阻抗之變化。因此，成爲不必依據所實裝之記憶元件之 個數即可將記憶匯流排線之負荷阻抗設定在規定値，不必 在每一製品重新設定系統電路基板，成爲隨著需要可將必 需個數之記憶體加以實裝而使用。 •使用該系統電路基板，可得到嚴密之阻抗匹配，可實 現可使用高速記憶匯流排的電腦系統。 記憶匯流排之負荷阻抗係在記憶體實裝區域近旁之所 定配線領域成爲比規定値高，而連接端子係設於所定配線 領域內之記憶匯流排線上，而藉由實裝之記憶元件之負荷 電容及電容性元件之電容使所定配線領域的記憶匯流排線 之負荷阻抗成爲規定値較理想。 連接端子係作爲錫銲用之實裝墊也可實現，或藉由腳 座等實現也可以。藉腳座加以實現時，則可裝卸自如地裝 設電容性元件。 經濟部智慧財產局員工消費合作社印製 作爲電容性元件，也可將電容値加以可設成可變之可 變電容性元件加以使用。如此，由於不必變更隨著記憶體 實裝個數所實裝的電容性元件之個數，或是每一個之電容 性，因此成爲可更提高電路基板之常用性。調整可變電容 性元件之電容値，係隨著記憶元件之實裝個數所進行就可 以。 (發明之實施形態） 以下參照圖式說明依本發明之系統電路基板’及使用 它之電腦系統，或電子機器之實施例。 本紙張尺度適用中國國家標準（CNS ) M規格（21〇X297公釐） -6- 502145 A7 ______B7_ 五、發明説明（4 ) (第一實施例） 在第1圖表示本發明之第一實施例的電腦系統之構成 。該電腦系統係筆記型個人電腦；該系統電路基板（也稱 爲母基板或系統基板）上，如圖示地，實裝有c P U匯流 排 1 ’ P C I ( Peripheral Component Interconnect )匯流 排 2，I S A ( Industry Standard Architecture )匯流排 3 ，記憶匯流排線4，C P U 1 1 ，主一 P C I電橋1 2， 內部記憶體1 4，記憶體擴張槽1 5，P C I — I S A電 橋17，其他各種PC I元件18 ，及B I〇S— ROM 1 9等。 C P U 1 1係用以控制整體本系統之動作者，除了實 行系統B I 0 S及操作系統之外，還實行各種應用程式。 主一 P C I電橋1 2係以雙向連接C P U匯流排1與 P C I匯流排2的匯流排橋接裝置；內部有用以存取控制 拆下自如地裝設於實裝在系統電路基板上之內部記憶體 1 4及記憶體擴張槽1 5之擴張記憶模組的記億體控制器 1 3。記憶體控制器係_圖示地經由記憶匯流排線4被連 接於內部記憶體1 4及記憶擴張槽1 5。 · 作爲內部記憶體1 4，使用Rambus規格之Rambus記 憶體等之高速半導體記憶元件1 4 1〜1 4 4。在系統電 路基板上設有用以實裝高速半導體記憶元件1 4 1〜 1 4 4之晶片的複數記億實裝區域，最大僅可實裝四個記 憶元件。記憶元件之實裝個數係配合電腦系統之製品模型 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再本頁) •裝· 訂 經濟部智慧財產局員工消費合作社印製 502145 A7 ____B7_ 五、發明説明（5 ) 等被決定。 又，在記憶體實裝區域之近旁，也設有將電容器等電 容性元件1 6連接於記憶匯流排線4所用之連接端子，及 該電容性元件1 6之實裝區域。在第1圖中，實裝區域係 表示作爲元件本身者。電容性元件1 6係使用於用以吸收 依記憶元件之實裝個數所產生之負荷電容之不同者。由此 ’不依據記憶元件之實裝個數，可將記憶匯流排線4之負 荷阻抗可對準於依據記憶匯流排介面規格的規定値。 PC I - I SA電橋1 7係雙向連接PC I匯流排2 與I SA匯流排3的橋接裝置，與主一 PC I電橋1 2 — 起，功能作爲本電腦系統之周邊晶片組。 請 先 閱. 讀 背 之 注 意 事 項 再 圹Λ % 本 頁 在 BIOS — R〇 MlΗ Order II Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 502 502145 A7 _____ B7 V. Description of the Invention (2) However, in high-speed memory systems that require strict impedance matching, it becomes necessary to consider the memory itself. Load capacitance. The load capacitance of the memory is changed by the number of installed memories, and as a result, the load impedance of the memory bus is changed. Therefore, when there is an installed memory in all the memory installation areas, or when the memory installation area is free, the load impedance of the memory bus line will be different, making it impossible to obtain strict impedance matching. Therefore, when using a high-speed memory bus, it is actually difficult to use the above-mentioned method for installing as many memories as needed. (Summary of the invention) The present invention was created in view of the above matters, and its purpose is to provide a load impedance of the memory bus line that can be set to a predetermined value without depending on the number of installed memory elements. Redesign the system circuit board, and if necessary, the required number of memories can be installed and used in the system circuit board, and the computer system and electronic equipment using it. The system circuit substrate of the present invention is characterized in that: it is printed on a memory bus line by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and is used to implement a memory penetrating area of a plurality of memory elements; The capacitive element of the memory impedance of the bus bar caused by the change in the number of components installed is connected to the connection terminal of the bus bar. The system circuit substrate of the present invention is capable of compensating the memory bus generated by the change in the number of installed memory elements by connecting the capacitive element with the number of installed capacitors to the memory bus. The paper size of the negative cable is applicable to the Chinese National Standard (CNS) A4 specification (210X29 * 7 mm). I quot5-502145 A7 B7 V. Description of the invention (3) The change of the load impedance. Therefore, it is possible to set the load impedance of the memory bus line to a predetermined value without depending on the number of installed memory elements, and it is not necessary to reset the system circuit board for each product, and it becomes possible to set the required number as required. The memory is installed and used. • Using this system circuit board, you can get tight impedance matching and realize a computer system that can use high-speed memory buses. The load impedance of the memory bus is higher than the specified wiring area in the predetermined wiring area near the memory installation area, and the connection terminal is located on the memory bus line in the predetermined wiring area, and the load of the installed memory element is The capacitance of the capacitor and the capacitive element makes the load impedance of the memory bus bar in a given wiring area a predetermined threshold, which is ideal. The connection terminal system can also be realized as a mounting pad for soldering, or it can be realized by a foot or the like. Capacitive components can be easily attached and detached when it is realized by the feet. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As a capacitive element, the capacitor can also be used as a variable capacitive element that can be set to be variable. In this way, since it is not necessary to change the number of capacitive elements installed with the number of memories installed, or the capacitance of each, it becomes possible to further improve the commonality of circuit boards. Adjusting the capacitance of the variable capacitive element can be performed with the number of memory elements installed. (Embodiments of the invention) Embodiments of a system circuit substrate according to the present invention and a computer system or an electronic device using the same will be described below with reference to the drawings. This paper size applies the Chinese National Standard (CNS) M specification (21 × 297 mm) -6-502145 A7 ______B7_ V. Description of the invention (4) (First embodiment) The first embodiment of the present invention is shown in FIG. 1 Of the computer system. The computer system is a notebook personal computer; the system circuit board (also referred to as the mother board or system board), as shown in the figure, is equipped with a c PU bus 1 'PCI (Peripheral Component Interconnect) bus 2, ISA (Industry Standard Architecture) bus 3, memory bus 4, CPU 1 1, main-PCI bridge 1 2, internal memory 1 4, memory expansion slot 15, PCI — ISA bridge 17, various other PCs I element 18, and BIOS-ROM 19 and so on. C P U 1 1 is used to control the actions of the entire system. In addition to implementing the system B I 0 S and the operating system, it also implements various applications. The main PCI bridge 1 2 is a bus bridge device that connects the CPU bus 1 and the PCI bus 2 bidirectionally; it is used internally for access control and can be detached and installed on the internal memory installed on the system circuit board. 14 and the memory expansion controller 15 of the expansion memory module of the memory controller 13. The memory controller is connected to the internal memory 14 and the memory expansion slot 15 via a memory bus line 4 as shown. · As the internal memory 14, a high-speed semiconductor memory element such as a Rambus memory of the Rambus specification is used. 1 4 1 to 1 4 4 The system circuit board is provided with a plurality of hundreds of millions of mounting areas for mounting high-speed semiconductor memory elements of 141 to 144, and only a maximum of four memory elements can be mounted. The installed number of memory components is a product model that matches the computer system. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before this page). Printed by employee property cooperative of property bureau 502145 A7 ____B7_ V. Invention description (5) etc. were decided. Further, a connection terminal for connecting a capacitive element 16 such as a capacitor to the memory bus line 4 and a mounting area of the capacitive element 16 are also provided near the memory mounting area. In Fig. 1, the mounting area is shown as the component itself. Capacitive element 16 is used to absorb the difference in load capacitance generated by the number of installed memory elements. Therefore, 'the load impedance of the memory bus line 4 can be aligned with the specifications of the interface of the memory bus, irrespective of the number of installed memory elements.' PC I-I SA bridge 1 7 is a bridging device that connects PC I bus 2 and I SA bus 3 bidirectionally. It functions as the peripheral chipset of this computer system together with the main PC I bridge 1 2. Please read it first. Read the notes before reading 圹 Λ% This page is in BIOS — R〇 Ml
儲存有系統B I〇S 經濟部智慧財產局員工消費合作社印製Stored System B I0S Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Basic I/O System )。系統B I〇S係一體系化用以控制本 電腦系統之硬體之功能者；實行系統之電源控制導通/斷 開，及系統起動處理等。 以下，參照第2圖，說明系統電路基板上之內部記憶 體周圍的實裝構造。 記憶匯流排線4係從記憶體控制器1 3至記憶擴張槽 1 5 ，延設在作爲系統電路基板所使用之印刷電路基板上 。在此，區域B係包含系統電路基板上之記憶體實裝區域 及電容性元件實裝區域的配線區域；又其兩外側之區域A 係分別朝記憶體控制器1 3及記憶擴張槽1 5延伸的配，線 區域。記憶匯流排線4係包含例如1 8位元寬之資料線， 8位元寬之位址/命令線，讀出脈衝信號線，寫入脈衝信 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -8 - 502145 A7 _______ B7 五、發明説明（6 ) 號線等多數信號線所構成，惟由於任一信號線之實裝形式 係相同，因此在此，代表各信號線僅表示一個信號線4工 〇 在區域B事先準備有用以實裝記憶元件1 4 1〜 1 4 4的四個記憶體實裝區域。在此等四個記憶體實裝區 域’分別設有記億元件實裝墊2 0 1〜2 0 4。又，實裝 區域係不是設於每一元件，成爲複數元件可實裝於一區域 也可以。 實際上，如第3圖所示地，在每一各記憶體實裝區域 ’相當於構成記憶匯流排線4之記憶信號線數（記憶元件 之梢數）的實裝墊（零件安裝孔）設於系統電路基板上， 而記憶匯流排線連接於所定墊。 又回到第2圖；在配線區域B之電容性元件的實裝區 域，也設置用以實裝電容性元件1 6之一對電容器實裝墊 205、 206。電容器實裝墊205係連接於構成記憶 匯流排線4之各信號線，而電容器實裝墊2 0 6係連接於 接地線。 構成記憶匯流排線4之各信號線4 1係在朝記憶體控 制器3及記憶體擴張槽1 5延伸之配線區域A，形成作爲 規定之阻抗（=2 8 Ω )，惟在區域B，如第2圖所示地 藉將配線之圖案寬度變窄小，形成比規定阻抗更高（例如 4 1 Ω )。此乃由於在記憶元件1 4 1〜1 4 4存有負荷 電容C，因此實裝記億元件1 4 1〜1 4 4時，則記憶匯 流排線之負荷阻抗僅降低該分量。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） - -9- —1-. ................................ m ------- 1 - m g-ii- ill; n (請先閲讀背面之注意事項再ϋι本頁) 訂 經濟部智慧財產局員工消費合作社印製 502145 A 7 B7 五、發明説明（7 ) ϋ· nn i·—— ml u mj nn nn in «ml I (請先閱讀背面之注意事項再 本頁) 將區域B的記憶匯流排線4之阻抗作爲L，而將區域 B之記憶匯流排線4之全電容成爲C，則區域B之記憶匯 流排線之負荷阻抗係可用#加以表示。亦即，若記憶元件 追加於記憶匯流排線4上，則記憶匯流排線4之負荷阻抗 係增加記憶元件，則成爲僅降低該負荷電容之分量。考慮 此狀況，在本實施例中，區域B之記憶匯流排線4本體之 負荷阻抗係設定在比例如4 1 Ω之規定値較高値。該値係 實裝有四個記憶元件1 4 1〜1 4 4時，藉由此等記憶元 件之負荷電容使區域B之阻抗設成規定之阻抗（=2 8 Ω )者。因此，在均實裝四個記憶元件1 4 1〜1 44之狀 態下，構成記憶匯流排線4之各信號線4 1之負荷阻抗係 區域A、B均相等（均爲2 8Ω)，不會發生阻抗之不連 續。因此記憶匯流排線4係不會失真也可傳送4 0 0 Μ Η z之高速信號。 經濟部智慧財產局員工消費合作社印製 但是，記憶元件之實裝個數比四個少時，區域Β之記 憶匯流排線4之負荷阻抗係與規定値不相同（會變少）， 產生阻抗之不匹配，而對於信號品質有影響。如此，在本 實施例中，在記憶體實裝區域之中央部事先設置電容器實 裝墊2 0 5，2 0 6，記憶元件之實裝個數比四個少時， 由此構成視需要可實裝電容性元件1 6，因此，記憶元件 之實裝個數爲四個以下時，隨著該個數，藉變更作爲電容 性元件1 6實裝之元件電容，可將區域Β之阻抗可配合在 既定値。 例如，以第2圖之虛線所示地，記憶元件1 4 2， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐) ~ •10- 502145 A7 B7__ 五、發明説明（8 ) 1 4 3係未實裝，而僅實裝記憶元件1 4 1 ，1 4 4之情 形，將具有記億元件1 4 2，1 4 3之兩個分量之負荷電 容的電容性元件1 6實裝在電容器實裝墊2 0 5，2 0 6 ’又在實裝所有記憶元件1 4 1〜1 44時，藉未實裝電 容性元件1 6，故可將區域B之阻抗配合在規定値。 又，電容器實裝墊205，206係實現作爲錫銲用 之實裝墊也可以，藉由腳座加以實現時，可裝卸自如地裝 設電容性元件，記憶元件之實裝數變更時之調整成爲容易 〇 又，電容性元件1 6係在區域B內連接於記憶匯流排 線4就可以，電容性元件1 6之實裝區域係不必在記憶體 實裝區域之中央部也可以。 經濟部智慧財產局員工消費合作社印製 又實際上，由於記憶元件1 4 1〜1 4 4係實裝於系 統電路基板上的單板記憶體，因此記憶元件數係在製造階 段被事先決定。因此，依據依記憶元件之實裝個數之負荷 電容之不相同而用以調整記憶匯流排線之負荷阻抗之變化 的電容性元件之電容也在製造階段被決定。如此，在工廠 發貨時，係在對應於記憶元件數之電容的電容器實裝於系 統電路基板之電容器實裝墊2 0 5，2 0 6之狀態，或是 成爲電容器未實裝地出貨。 又爲了變更電容器之電容，說明更換電容器本體，惟 藉將所定個數之電容性元件並聯地連接於實裝墊2 0 5， 206，未變更電容也可以。 依照第一實施例，由於將系統電路基板上之記憶匯流 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 502145 A7 _B7_ 五、發明説明（9 ) (請先閲讀背面之注意事項再本買) 排線的負荷阻抗，在用以實裝複數記憶元件之記憶體實裝 區域內設成比既定値更高値，且藉將電容性元件連接於記 憶匯流排線所用之實裝墊設在記憶體實裝區域內之匯流排 線，因此具有用以補償依據記憶元件之實裝個數之變化的 記憶元件之負荷電容之變化的電容値的電容性元件連接於 記憶匯流排線，可補償依據依記憶元件之實裝個數所發生 之負荷電容量之不相同的記憶匯流排線之負荷阻抗之變化 。因此，成爲不必依據所實裝之記憶元件之個數即可將記 憶匯流排線之負荷阻抗設定在規定値，不必在每一製品重 新設定系統電路基板，成爲隨著需要可將必需個數之記憶 體加以實裝而使用。使用該系統電路基板，可得到嚴密之 阻抗匹配，可實現可使用高速記憶匯流排的電腦系統。 以下說明本發明之其他實施例。在以下實施例與第一 實施例對應之部分賦予相同參照數字而省略詳細說明。 (第二實施例） 經濟部智慧財產局員工消費合作社印製 在第一實施例中說明適當地安裝隨著記憶元件之實裝 個數之電容的電容性元件加以說明’惟將使用可變電容之 元件的第二實施例說明如下。由於整體電腦系統之方塊圖 係與第1圖所示者相同，故省略其說明。 在此，代替在第一實施例所用之電容性元件1 6 ’設 置將電容値可設成可變的可變電容性元件3 0 3 °亦即， 在包含記憶體實裝區域之區域B之中央部，設有用以實裝 可變電容性元件3 0 3的一對電容器實裝墊3 0 1， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) .............................................................. 一 -12- 502145 A7 B7 五、發明説明（1〇 ) 3 0 2。電容器實裝墊3 0 1係連接於構成記憶匯流排線 4之信號線4 1，而電容器實裝墊3 0 2係連接於給與電 容控制用電源的電源端子。 作爲可變記憶匯流排線3 0 3係可使用例如使用P N 接合墊者等。將P N接合二極體之陽極連接於信號線4 1 側，並將陰極連接於電源端子3 0 2時，藉變更電源端子 3 0 3之電容控制用電源V，PN接合二極體之電容係如 第5圖所示地變化。 因此，藉事先決定記憶元件之實裝個數與電容控制用 電源V之關係，可容易地得到目的之阻抗。當然，實裝所 有記憶元件1 4 1〜1 4 4時，將可變電容性元件3 0 3 之電容實質上設成零就可以。又，在未能將可變電容性元 件3 0 3之電容設成零時，則將區域B的記億匯流排線4 之負荷阻抗値考慮可變電容性元件3 0 3之最小電容加以 設計就可以。 經濟部智慧財產局員工消費合作社印製 電容控制用電源V係藉由可變電源電壓發生電路 3 0 4所發生。在第4圖中，可變電源電壓發生電路 3 0 4係設於記憶體控制器1 3側，惟設置場所係不被限 定於此種。調整從可變電源電壓發生電路3 0 4所發生的 電容控制用電源V，係藉由傾斜開閉等以手動進行也可以 ，惟在控制系統B I 0 S之控制下，將控制資料設在可變 電源電壓發生電路3 0 4內之暫存器3 0 5，隨著該控制 資料之數値來可變控制電容控制用電源V之數値‘也可以。 使用第6圖說明此時之系統B I〇S之處理方法。當 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） '~ 一 13賺 502145 A7 B7 五、發明説明（n ) 本電腦系統被通電時，系統B I 0 S係首先進行各種硬體 之初期化處理等。此時檢驗記憶元件之實裝個數（步驟 S 1 0 1 )。在Rambus記憶體中，準備爲了控制該初期化 等所使用之專用信號線（S I , η，S I。u t等）。該信號 線係以菊花鏈連接於複數記憶元件1 4 1〜1 4 4。例如 經由該信號線，將各記憶元件內之控制暫存器從最接近於 記憶體控制器1 3之記憶元件依次地存取，由無法進行對 於次段之存取爲止之存取次數，可偵測記憶元件之實裝個 數。 之後，系統B I〇S係依據事先決定之記憶元件實裝 個數與電容控制用電源V之對應關係資訊，在可變電源電 壓發生電路3 0 4內之存儲器3 0 5設定適當之控制資料 (步驟S 1 〇 2 )。由此，隨著記憶元件實裝個數而可將 電容控制用電·源V之數値加以可變控制，可將可變電容性 元件3 0 3之電容配合記憶元件之實裝個數而成爲自動調 整。 經濟部智慧財產局員工消費合作社印製 如上所述，依照第二實施例，由於不必要更換隨著記 億體實裝個數變更電容所用的電容性元件，因此成爲可更 提高系統電路基板之廣用性。 本發明係並不被限定於上述之實施例，可實施各種變 形。例如，記憶體實裝個數之偵測，係也可藉由接點開關 等來進行。又，本發明係可適用裝載使用高速記憶體之高 速記憶匯流排之各種系統電路基板，不但可適用於電腦系 統之基板，也可適用於使用高速記憶體之遊戲機或錄影機 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐) " " •14- 502145 A7 B7 五、發明説明（12 ) ^ 等之各種電子機器之電路基板等。又僅裝載記憶元件，也 可適用在作爲記憶模組所使用之電路基板也可以。 如上所述地’依照本發明’不依據實裝之記憶元件之 個數成爲可將記憶匯流排線之負荷阻抗設定在作爲目的之 規定値，在每一製品不必重新設計系統電路基板，成爲隨 著需要可實裝所需個數之記憶體加以使用。 (圖式之簡單說明） 第1圖係表示使用本發明之第一實施例之系統電路基 板的電腦系統之構成的方塊圖。 第2圖係表示第1圖之系統電路基板之記憶體周邊之 實裝構造之一例的圖式。 第3圖係表示設於第2圖之系統電路基板之記憶元件 實裝墊與記憶匯流排線之關係的圖式。 第4圖係表示本發明之第2實施例的系統電路基板之 記憶體周邊之實裝構造的圖式。 經濟部智慧財產局員工消費合作社印製 第5圖係表示在第4圖所使用之可變電容性元件之電 壓對電容之特性的圖式。 第6圖係表示藉由第二實施例的電腦系統之系統 B I 0 S所實行之電容値調整處理之原理的流程圖。 (記號之說明） 1 C P U匯流排 2 P C I匯流排 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) -15- 502145 五、發明説明（13 ) 3 IS A 匯 流 排 4 記憶 1 1 C P U 1 2 主 — P C I 電 橋 1 3 記 憶 體 控 制 器 1 4 內 部 記 憶 體 1 5 記 憶 體 擴 張 槽 1 6 電 容 性 元 件 1 7 P C I — I S A 電 橋 1 8 P C I 元 件 1 9 B I 〇 S — R 〇 Μ 4 1 信 號 線 1 4 1〜1 4 4 記 憶 元 件 A7 B7 (請先閲讀背面之注意事項 訂 經濟部智慧財產局員工消費合作社印製 2 0 1〜2 0 4 記憶元件實裝墊 2 0 5，2 0 6 電容器實裝墊 302 電源端子 303 可變電容性元件 304 可變電源電壓發生電路 305 暫存器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16-Basic I / O System). System B IOS is a system that controls the functions of the hardware of this computer system; implements system power control on / off, and system startup processing. Hereinafter, the mounting structure around the internal memory on the system circuit board will be described with reference to FIG. 2. The memory bus line 4 extends from the memory controller 13 to the memory expansion slot 15 and is extended on the printed circuit board used as the system circuit board. Here, the area B is a wiring area including the memory mounting area and the capacitive component mounting area on the system circuit board; and the area A on both outer sides thereof respectively faces the memory controller 13 and the memory expansion slot 1 5 Extended distribution, line area. Memory bus line 4 includes, for example, 18-bit-wide data lines, 8-bit-wide address / command lines, read-out pulse signal lines, and write-in pulse letters. Paper standards are applicable to China National Standard (CNS) Α4 specifications. (210 × 297 mm) -8-502145 A7 _______ B7 V. Description of the invention (6) Lines and other signal lines are composed, but since the installation form of any signal line is the same, here, it means that each signal line is only A signal line 4 is shown. In the area B, four memory mounting areas for mounting the memory elements 1 4 1 to 1 4 4 are prepared in advance. These four memory mounting areas' are respectively provided with a memory component mounting pad 2101 to 204. In addition, the mounting area is not provided for each component, and a plurality of components may be mounted in one area. In fact, as shown in FIG. 3, in each of the memory mounting areas, the mounting pads (part mounting holes) are equivalent to the number of memory signal lines (the number of memory element pins) constituting the memory bus line 4. It is set on the system circuit board, and the memory bus is connected to the predetermined pad. Returning to FIG. 2 again, in the mounting area of the capacitive element in the wiring area B, a pair of capacitor mounting pads 205, 206 for mounting one of the capacitive elements 16 are also provided. The capacitor mounting pad 205 is connected to each signal line constituting the memory bus line 4, and the capacitor mounting pad 206 is connected to a ground line. Each of the signal lines 41 constituting the memory bus line 4 is formed in a wiring area A extending toward the memory controller 3 and the memory expansion slot 15 to form a predetermined impedance (= 2 8 Ω), but in the area B, As shown in FIG. 2, the pattern width of the wiring is narrowed to be smaller than a predetermined impedance (for example, 4 1 Ω). This is because the load capacitance C is stored in the memory elements 1 4 1 to 1 4 4. Therefore, when the memory element 14 1 to 1 4 4 is installed, the load impedance of the memory bus line is reduced by only this component. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm)--9- —1 -............... ....... m ------- 1-m g-ii- ill; n (please read the precautions on the back first, and then ϋ this page) Order Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 502145 A 7 B7 V. Explanation of the invention (7) ϋ · nn i · —— ml u mj nn nn in «ml I (please read the precautions on the back before this page) Use the impedance of memory bus 4 in area B as L, and the full capacitance of the memory bus line 4 in area B becomes C, then the load impedance of the memory bus line in area B can be expressed by #. That is, if a memory element is added to the memory bus line 4, the load impedance of the memory bus line 4 is increased by the memory element, and only the component of the load capacitance is reduced. Considering this situation, in this embodiment, the load impedance of the memory bus bar 4 body in the area B is set to be higher than, for example, 4 1 Ω. In this case, when four memory elements 1 4 1 to 1 4 4 are actually installed, the impedance of the area B is set to a predetermined impedance (= 2 8 Ω) by the load capacitance of the memory elements. Therefore, in a state where four memory elements 1 4 1 to 1 44 are all installed, the load impedance areas A and B of each signal line 41 constituting the memory bus line 4 are equal (both 2 8 Ω). Discontinuities in impedance occur. Therefore, the memory bus line 4 can transmit high-speed signals of 400 MHz without distortion. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, when the number of installed memory elements is less than four, the load impedance of the memory bus line 4 in area B is different from the specified value (will decrease), resulting in impedance. This does not match and has an impact on the signal quality. In this way, in this embodiment, a capacitor mounting pad 2 05, 2 06 is set in the center of the memory mounting area in advance, and when the number of the memory elements is less than four, the structure may be configured as required. Since the capacitive element 16 is installed, when the number of the memory element is four or less, the impedance of the area B can be changed by changing the capacitance of the element mounted as the capacitive element 16 with the number. Cooperate in the established 値. For example, as shown by the dashed line in Figure 2, the memory element 1 4 2 is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ • 10- 502145 A7 B7__ V. Description of the invention (8) 1 4 3 series is not installed, but only memory elements 1 4 1, 1 4 4 are mounted, and capacitive elements 16 having a load capacitance of two components of 14 billion, 1 4 3 are mounted. When the capacitor mounting pads 2 05, 2 0 6 'and all the memory elements 1 4 1 to 1 44 are mounted, since the capacitive elements 16 are not mounted, the impedance of the area B can be matched to the specified value. In addition, the capacitor mounting pads 205 and 206 may be implemented as soldering pads. When the capacitor mounting pads are implemented by feet, the capacitive elements can be detachably mounted, and adjustments can be made when the number of memory elements is changed It is easy. The capacitive element 16 may be connected to the memory bus line 4 in the region B, and the mounting region of the capacitive element 16 may not necessarily be in the center of the memory mounting region. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In fact, since the memory elements 141 to 144 are single-board memories mounted on the circuit board of the system, the number of memory elements is determined in advance during the manufacturing stage. Therefore, the capacitance of the capacitive element used to adjust the change in the load impedance of the memory bus line according to the load capacitance of the number of installed memory elements is also determined at the manufacturing stage. In this way, at the time of factory shipment, the capacitors with the capacitance corresponding to the number of memory elements are mounted on the capacitor mounting pads of the system circuit board, or the capacitors are shipped without mounting. . In order to change the capacitance of the capacitor, it is explained that the capacitor body is replaced. However, by connecting a predetermined number of capacitive elements in parallel to the mounting pads 205, 206, the capacitance may not be changed. According to the first embodiment, because the memory on the system circuit board is converged, the paper size is applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-502145 A7 _B7_ V. Description of the invention (9) (Please read the back first (Please pay attention to the purchase again) The load impedance of the cable is set higher than the predetermined value in the memory installation area where multiple memory elements are installed, and the capacitive element is used to connect the memory bus line. The mounting pad is a bus line provided in the memory mounting area, so a capacitive element having a capacitance to compensate for a change in load capacitance of the memory element according to a change in the number of the memory element is connected to the memory bus The cable can compensate the change of the load impedance of the memory bus cable according to the load capacitance that varies according to the number of installed memory elements. Therefore, it is possible to set the load impedance of the memory bus line to a predetermined value without depending on the number of the installed memory elements, and it is not necessary to reset the system circuit board for each product. The memory is installed and used. By using this system circuit board, strict impedance matching can be obtained, and a computer system that can use high-speed memory buses can be realized. Hereinafter, other embodiments of the present invention will be described. In the following embodiments, portions corresponding to those in the first embodiment are given the same reference numerals and detailed descriptions are omitted. (Second Embodiment) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the first embodiment, a description will be given of a capacitive element that appropriately installs a capacitor with the number of memory elements installed. A second embodiment of the element is explained below. Since the block diagram of the overall computer system is the same as that shown in Fig. 1, its explanation is omitted. Here, instead of the capacitive element 16 ′ used in the first embodiment, a variable capacitive element 3 that can be set as a variable capacitor 3 0 3 °, that is, in the area B including the memory mounting area The central part is provided with a pair of capacitor mounting pads 3 0 1 for mounting variable capacitive elements 3 0 3. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ... ........................................ ... I-12- 502145 A7 B7 V. Description of the invention (1〇) 3 02. The capacitor mounting pad 3 0 1 is connected to a signal line 41 which constitutes the memory bus line 4, and the capacitor mounting pad 3 2 is connected to a power terminal for supplying a power supply for capacitance control. As the variable memory bus line 3 0 3 series, for example, a person using a P N bonding pad can be used. When the anode of the PN junction diode is connected to the signal line 4 1 side and the cathode is connected to the power terminal 3 0 2, the capacitance system of the PN junction diode is changed by changing the power supply V for the capacitance control of the power terminal 3 03. It changes as shown in FIG. 5. Therefore, by determining the relationship between the number of installed memory elements and the power supply V for capacitance control in advance, the intended impedance can be easily obtained. Of course, when mounting all the memory elements 1 4 1 to 1 4 4, it is sufficient to set the capacitance of the variable capacitive element 3 0 3 to substantially zero. In addition, when the capacitance of the variable capacitive element 3 0 3 cannot be set to zero, the load impedance of the 100 million bus bar 4 in the area B is considered, and the minimum capacitance of the variable capacitive element 3 0 3 is designed. can. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The capacitor control power supply V is generated by a variable power supply voltage generating circuit 304. In Fig. 4, the variable power supply voltage generating circuit 300 is provided on the memory controller 13 side, but the installation location is not limited to this. The capacitance control power supply V generated from the variable power supply voltage generating circuit 3 0 4 can be adjusted manually by tilting the switch, etc. However, the control data is set to be variable under the control of the control system BI 0 S. The register 3 0 5 in the power supply voltage generating circuit 3 0 4 may be controlled in accordance with the number of the control data to change the number V of the capacitor control power supply V ′. The processing method of the system B IOS at this time will be described using FIG. 6. When this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) '~ 13 earns 502145 A7 B7 V. Description of the invention (n) When this computer system is powered on, the system BI 0 S series first performs various hardware Initialization process, etc. At this time, the number of installed memory elements is checked (step S 1 0 1). In the Rambus memory, dedicated signal lines (S I, η, S I. u t, etc.) are prepared for controlling the initialization and the like. The signal lines are daisy-chained to the plurality of memory elements 1 4 1 to 1 4 4. For example, the control register in each memory element is sequentially accessed from the memory element closest to the memory controller 13 via the signal line, and the number of accesses until the access to the next segment cannot be performed can be Detect the number of installed memory components. After that, the system BIOS sets the appropriate control data in the memory 3 0 5 of the variable power supply voltage generating circuit 3 0 4 based on the information on the correspondence between the number of installed memory elements and the power supply V for capacitor control in advance ( Step S 1 〇 2). Therefore, as the number of memory elements is installed, the number of capacitor control power and source V can be variably controlled, and the capacitance of the variable capacitive element 3 0 3 can be matched with the number of memory elements installed. Become automatic adjustment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as described above, according to the second embodiment, since it is not necessary to replace the capacitive element used to change the capacitor with the number of installed batteries, it becomes a system circuit board that can further improve Versatility. The present invention is not limited to the embodiments described above, and various modifications can be made. For example, the detection of the number of installed memory can also be performed by a contact switch. In addition, the present invention is applicable to various system circuit substrates equipped with high-speed memory buses using high-speed memory. It is applicable not only to computer system substrates, but also to game machines or video recorders using high-speed memory. China National Standard (CNS) A4 specification (210X 297 mm) " " • 14- 502145 A7 B7 V. Description of the invention (12) ^ and other electronic circuit boards and other electronic equipment. It can also be used as a circuit board used as a memory module by mounting only memory elements. As described above, according to the present invention, the load impedance of the memory bus line can be set as the purpose without depending on the number of installed memory elements. It is not necessary to redesign the system circuit board for each product, and it becomes It is necessary to use the required amount of memory. (Brief description of the drawings) Fig. 1 is a block diagram showing a configuration of a computer system using a system circuit board of a first embodiment of the present invention. Fig. 2 is a diagram showing an example of a mounting structure around a memory of the system circuit board of Fig. 1; Fig. 3 is a diagram showing a relationship between a memory element mounting pad and a memory bus line provided in the system circuit board of Fig. 2. Fig. 4 is a diagram showing a mounting structure around a memory of a system circuit board according to a second embodiment of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5 is a graph showing the voltage vs. capacitance characteristics of the variable capacitive element used in Figure 4. Fig. 6 is a flow chart showing the principle of the capacitance adjustment process performed by the system B I 0 S of the computer system of the second embodiment. (Explanation of symbols) 1 CPU bus 2 PCI bus This paper size is applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) -15- 502145 V. Description of the invention (13) 3 IS A bus 4 Memory 1 1 CPU 1 2 Main — PCI bridge 1 3 Memory controller 1 4 Internal memory 1 5 Memory expansion slot 1 6 Capacitive element 1 7 PCI — ISA bridge 1 8 PCI element 1 9 BI 〇S — R 〇Μ 4 1 Signal line 1 4 1 ~ 1 4 4 Memory element A7 B7 (Please read the precautions on the back first and order it printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 0 1 ~ 2 0 4 Memory element mounting pads 2 0 5, 2 0 6 Capacitor mounting pad 302 Power terminal 303 Variable capacitive element 304 Variable power supply voltage generating circuit 305 Register This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -16-