TW501259B - Fabrication method for an aluminum fuse in a copper process - Google Patents

Abstract

The present invention provides a metal fuse fabrication method and the structure of the metal fuse to inhibit the cracking of dielectric layer beneath the copper material due to the high laser energy required to melt copper during laser fuse cutting process. A fuse is fabricated using aluminum as the major material component and the fabrication is integrated into the semiconductor manufacturing process so that the fuse is fabricated together with other devices. Furthermore, a laser alignment mark is fabricated using the same aluminum-containing metal as the fuse fabrication does because the luster of the metal is easier to identify than that of copper and thus easier to align. The metal is also more resistant to corrosion.

Description

V. Description of the invention (1) Field of the invention: The present invention is located in the copper material due to the use of copper as the dissolution image, so that the background of the invention: In recent years, there is a spare memory in the technology of conductor manufacturing. The damaged bits have been proposed in years [RT Smith and Circuits, vol. Spare memory bits and fuses cut the molten wire with polycrystalline silicon as the amount, making this redundant but cutting the semiconductor element with the element wire Difficult amounts can destroy polycrystalline silicon metal layers. The spare memory unit 2 in the integrated circuit is especially suitable for the production of fuses. Due to the high melting point and easy oxidation of the copper material, the protective layer is prone to cracking. The wire is still in a path condition even after being cut. Concentrating on the rapid increase in the density of memory elements in integrated circuits, the semi-J ^ replica 隹 ’, in order to increase production yield, replaces in-process design concepts in the component design element (redundancy) to maintain the integrity of circuit operation. Earliest, at 1 9 6 4 again. Ten Concepts' [; produced by the Bell group in 979 • D. Chlipala, IEEE J. Solid-State SC-16, PP. 5 0 6- 5 1 4, Oct, 1981]. The normally functioning bits are connected by fuses, the earliest material is formed on a silicon substrate, and the steps of laser energy cutting (laser cu 11 i ng) are used to cut off the 70 energy between each other. The effect of replacing damaged bits. The rapid increase in component density, and then the fabrication of multi-layered metal interconnects, increase the substrate under the laser energy required for the polycrystalline silicon using laser energy and the laser energy required during the cutting step. Therefore, the current fuse has been redesigned as an example of a process element for making eight layers of wires, as shown in Figure 1.

Page 4 501259 5. Description of the invention (2) shows that on a semiconductor substrate 10 with an active device and a multilayer wire, a dielectric layer 27 is deposited, and the lithography technology is used to define the dielectric layer 27. After the via hole 17 is filled, a conductive substance is filled in the via hole 17; then, another metal wire layer is formed. However, due to the process design, the current eight layers of metal are used as the middle layer of the sixth metal layer, and the same must be shown at the same time. Continuing, the deposited dielectric layer defines the metal wire 18 and the molten metal wire 18 and In the current process of fuse 62, for the production of the above wires, the material with the 'electromigration' is used to reduce the complexity of the process. It is also connected to the metal wire i 8 and still refers to the seventh dielectric layer shown in Figure 1. And the eighth layer is the same as that of the first layer after the dielectric layer is deposited, and the laser is aligned with the mark position. Finally, when the dielectric layers 29, 30, 31, and 32 are fabricated and removed in a engraved manner during the cutting step, In the embodiment of making ^ τρ ^ ^ ^ mm layer, the fuse will be made, as shown in Figure 1. Therefore, the fuse position is defined in the sixth step of the definition; the steps are as follows 28 on the dielectric layer 27 Above, after using the lithography technique to position the wire 62, a conductive material is filled in to complete the production of the sixth layer of metal. The RC delay time is reduced. Therefore, the process has low resistance and low electromigration. Copper metal is used as the conductive material. Due to various considerations in process cost, the fuse 62 and other metal layers are all made of copper. The formation of the sixth dielectric layer, the seventh metal layer, and the conductive layer 2 is the same as the method described above, and then a via hole, a metal wire, or Cu is filled in the conductive material. After the layer holes 19 and 21, the metal wires 20 and 22, and the Cu laser alignment mark 61 of the dielectric f, most of the dielectric layer 3 on the substrate 62 is used, so it is easy to control the laser energy.

501259

Five ^ UizDy Description of the Invention (4) In addition, the use of steel metallization results in less alignment in the process. U U transport marks 6! Easy oxygen Do not enter the sheep under the lamp-process steps. Summary of the invention:

The main object of the present invention is S1 structure, which adopts a manufacturing method for a metal fuse and reduces laser cutting energy. Gold is used as a fuse material. Therefore, another aspect of the present invention, which is required by the present invention, is a 3 dimensional structure, so that there are various types of metal fuse manufacturing methods and wires. 4 from the clothes' no need to make a separate fusion of the invention _ said & 9 its structure, its laser alignment 棹 J to make a metal fuse process method and recording pad-from the production, increase gold and melt the wire And use the following steps to achieve the above-mentioned items: the first I dog, two less in and out of the eight-layer metal connection of the semiconductor substrate using chemical rolling: wire two :! Electricity 'is continued to form a solder pad, a laser alignment mark and ...: two:] and on the dielectric layer 1, and according to the solder pad, the laser alignment mark §? , ',:, Φ and the pattern uses anisotropic etching to define the pad pad in the dielectric layer: shoot 1 quasi mark and fuse bit 1, remove the remaining H μ on the substrate and continue to deposit aluminum silicon copper The alloy is on the surface of the substrate. Finally, the chain stone copper alloy on the 2222 is removed to complete the production of solder pads, laser alignment marks and fuses. Figure number description:

Page 7 V. Description of the invention (5)

Tian Yan aligned 20 0 —the seventh layer of wire 220 —the eighth layer of metal_ 310- the second dielectric layer 5 0 0 —the fourth dielectric layer 6 0 〇-shattered steel 6 2 0-pad 1 0- Substrate 1 8-metal wire 2 0-metal wire 2 2-metal wire 28-dielectric layer 30-dielectric layer 3 2-dielectric layer 6 2-fuse 2 1 0-dielectric hole 300-first dielectric Layer 320-third dielectric layer 51Q-fourth dielectric layer 6 1 0-laser alignment mark 6 3 0 _ fuse

Detailed description of the invention ·

This method can be used in semiconductor manufacturing. In order to solve the problem of laser cutting, the laser energy needs to be melted due to the melting of copper materials, which leads to the copper material, and the electrical layers are prone to cracks. To make the wire even after cutting = forming the path condition. The following examples will use the process of making the main components of the super large volume t-circuit, and then continue, the process of forming an eight-layer wire and pad structure is explained. Technical means of the present invention. First, as shown in FIG. 3A, a semiconductor substrate 10 is provided.

Page 8 501259

The semiconductor stone substrate 10 includes electrical components and six layers of metal connections (not shown) of a completed static random access memory (SRAM). Then, a first dielectric layer 3 is deposited. 〇, and the first dielectric layer 300 using lithography technology to define the position of the seventh layer of gastric metal wire, the first dielectric layer 300 is a chemical vapor deposition (chemical vapor deposition; CVD) or spin on process deposition of silicon oxide or other dielectric materials such as HSQ and MSQ, etc. The thickness of the dielectric layer is between 5000 angstroms and 900 angstroms. Then, a conductive material is filled at the position of the seventh layer of wires, which is firstly deposited metal copper on the surface of the substrate by sputter or physical vapor deposition (PVD) method. On the surface of the substrate and the position of the metal wires in the dielectric layer 300, an etch-back step such as chemical mechanical polishing (CMP) is used to remove copper on the surface of the substrate to form a seventh layer of wires 200. Again, referring to FIG. 3A, a second dielectric layer 310 having a thickness between 5000 angstroms and 9,000 angstroms is formed on the first dielectric layer 300 and the seventh conductive line 2 Q 0. 'Deposition silicon oxide or other dielectric materials using chemical vapor deposition (CVD) or spin coating. Subsequently, after the position of the via hole 2 10 is defined in the second dielectric layer 3 i 0, copper metal is continuously filled in the via hole 2 1 0 to connect the two metal layers; the metal of the dielectric hole 210 The filling method is the same as that of the seventh-layer metal wire 200 described above. After copper metal is deposited, the etch back step is performed to remove the copper on the surface of the substrate. Continuer ’continued to produce the eighth metal wire layer, and the method is the same as described above.

501259 V. Description of the invention (7) The seventh layer of conductive wire 200 is formed in the same way. The third dielectric layer 320 is deposited first. After the eighth layer of metal wire 2 2 0 is defined, it is filled with copper metal to form the eighth layer The metal wire 2 2 0 completes all the wire manufacturing, but in the embodiment of the present invention, the fuse structure is not made together when the eighth layer metal wire or other layers of metal wire are manufactured. This is the present invention. Focus. The focus of the present invention is to fabricate fuses and laser alignment marks together with solder pads. The steps are as follows. As shown in FIG. 3B, a protective layer 500 'is first deposited using low pressure chemical vapor deposition (i. w —pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) deposits of silicon oxide or nitrogen with a thickness between 90 and 100 angstroms Silicon material, connection, as shown in Figure 3C, using the lithography method to define the position of the solder pad 6 2 0, the laser alignment mark 6 1 0, and the fuse 6 3 0; the lithography method described in detail For example, it includes spin-coating a positive or negative photoresist layer on the fourth dielectric layer 5000. After the photoresist layer is exposed using a photomask containing a pattern, a developing step is performed to partly block the photoresist. Then, according to the photoresist remaining on the substrate surface, the fourth dielectric layer 500 is subjected to anisotropic etching such as plasma etching, and the photoresist pattern is transferred to the fourth dielectric layer 500 as defined in Positions of the solder pad 620, the laser alignment mark 610, and the fuse 630. Next, referring to FIG. 3D, an aluminum-silicon-copper (AlSiCu) material is deposited in the positions of the fourth dielectric layer 5 1 0 and the pad 6 2 0, the laser alignment mark 6 1 0 and the fuse 6 3 0. , Using sputtering or physical vapor deposition to form an aluminum-silicon-copper alloy with a thickness between 900 and 100 angstroms, and finally, as shown in Figure 3e, using a chemical mechanical polishing method Al-Si-Cu on the fourth dielectric layer 5

Page 10 V. Description of Invention (8) 600 Excluding +630. For 塾 62G, laser alignment mark 6iG and melting wire process, the fuses used by its aluminum silicon copper are all aluminum silicon copper. All are metal. Heart: Only 1% of Shi Xi is contained and the melting point of the copper containing 0.51 is 660. . When cutting with a thousand lasers, because of the aluminum metal, the amount of protection under the molten wire is much lower than that of copper. If problems are encountered, ° cracks are less likely to occur and In addition, there are known technologies. In addition, the two shots made of aluminum-silicon-copper metal are susceptible to oxidation or rot in the process: copper, which is less easy to distinguish, and can increase the metal used for alignment during the process. The metal described above uses the better of the wire to make the scope of the present invention, so we are familiar with this technology :::: Invention, but not limited to making small changes and adjustments, will still be clear without loss. Appropriately, without departing from the spirit and scope of the present invention, Dukang, the essence of the invention, and the status of implementation are also considered .... Seen as a further illustration of the present invention. A schematic cross-sectional view of the process of the three layers above the metal connection. Figure 2 is a schematic cross-sectional view of the process of the fuse located at the uppermost layer of the multilayer metal connection in the conventional art. Process profile FIG. 3B is a schematic cross-sectional view of a process of forming a fourth dielectric layer on a multilayer metal connection in an embodiment of the present invention.

FIG. 3C is a schematic cross-sectional view of a process for defining positions of a pad, a fuse, and a laser alignment mark in a fourth dielectric layer according to an embodiment of the present invention. FIG. 3D is a schematic cross-sectional view of a process for depositing a conductive material in an embodiment of the present invention. FIG. 3E is a schematic cross-sectional view of a process for forming a solder pad, a fuse, and a laser alignment mark in an embodiment of the present invention.

Page 12

Claims (1)

-1- 501259 6. Scope of patent application—one—one and one—The scope of patent application: 1. A method for manufacturing a metal melting wire (in eta 1 fuse), which includes: (a) a top layer that has been manufactured A dielectric layer is formed on the semiconductor substrate of the metal connection; (b) a photoresist with a pad and a fuse pattern is formed on the dielectric layer; (c) the dielectric layer is formed on the dielectric according to the pad and the fuse pattern The electrical pads define the pads and fuse positions; (d) remove the photoresist on the dielectric layer; (e) deposit an AlSiCu alloy on the dielectric layer and the pads And a fuse position; (f) removing the aluminum silicon copper alloy on the dielectric layer. * 2. The method for manufacturing a metal fuse according to item 1 of the scope of patent application, wherein the step (b) includes a laser alignment mark pattern. 3. The method for manufacturing a metal fuse as described in item 1 of the scope of the patent application, wherein the definition of the pad and the fuse position uses an anisotropic etching method. 4. The method for manufacturing a metal fuse according to item 1 of the scope of the patent application, wherein the dielectric layer is oxidized. 5. The method for manufacturing a metal fuse according to item 1 of the scope of the patent application, wherein the dielectric layer is silicon nitride. 501259 6. Scope of patent application 6 · The method for manufacturing a metal fuse as described in item 1 of the scope of patent application, wherein the inscription > 5X copper is deposited using a spattered bell (s p u 11 e r) method. 7 · The method for manufacturing a metal fuse as described in item 1 of the scope of patent application, wherein said copper chip is physical vapor deposition (physica 1 va ρ 〇r deposition; PVD) ° 8. The method for manufacturing a metal fuse according to item 1, wherein the metal connection uses copper (Cu) metal as a wire material. 9. A fuse manufacturing method, comprising: (a) defining a pad, a fuse, and a laser alignment mark on the semiconductor substrate, wherein the semiconductor substrate has been manufactured with a multilayer metal connection; And the top of the semiconductor substrate is a dielectric layer; (b) depositing an AlSiCu alloy on the dielectric layer and the positions of the pads and fuses; (c) removing the The aluminum-silicon-copper alloy on the dielectric layer. 10. The method for manufacturing a fuse according to item 9 of the scope of the patent application, wherein the definition of the pad and the position of the fuse on the semiconductor substrate includes: (a) forming a pad, a fuse and a laser The photoresist of the alignment mark pattern is on the dielectric layer; (b) the non-isotropic etching technique is used to escape according to the pad, fuse and laser alignment mark pattern. The solder is defined in the dielectric layer. Pads, fuses and thunder Page 14 501259 6. Scope of patent application: Alignment of the alignment marks; (C) Remove the photoresist on the dielectric layer. 1 1. The method for manufacturing a fuse according to item 9 in the scope of the patent application, wherein the dielectric layer is silicon oxide. 12. The method for manufacturing a fuse according to item 9 in the scope of the patent application, wherein the dielectric layer is silicon nitride. 1 3. The method for manufacturing a fuse as described in item 9 of the scope of the patent application, wherein the bauxite copper alloy is deposited using a method of low plating (s p u 11 e r). 1 4. The method for manufacturing a fuse according to item 9 in the scope of the patent application, wherein the copper alloy of Lu Shixi uses a physical vapor deposition method (physica 1 vapor deposition; PVD) ° 1 5. Item 9: The method for manufacturing a fuse, wherein the Au-Cu connection uses Cu (Cu) metal as a wire material. 1 6. The structure of a metal, fuse (meta 1 fuse), includes: a semiconductor substrate, wherein the semiconductor substrate has been prepared with a multilayer metal connection; a dielectric layer, located on the semiconductor substrate Above; a wire-dissolving structure located in the dielectric layer, wherein the wire-dissolving junction Page 15 501259 6. The scope of patent application is composed of Mingshixi copper alloy (A 1 S i C ua 1 1 0y); a laser alignment mark structure is located in the dielectric layer, where The laser alignment mark structure is composed of an aluminum silicon steel alloy (A 1 S i Cu a 1 1 oy); and a pad structure is located in the dielectric layer. 1 7. The metal fuse structure according to item 16 of the scope of the patent application, wherein the semiconductor substrate is an electrical component containing a static random access memory (SRAM). 18. The metal fuse structure according to item 16 of the scope of patent application, wherein the dielectric layer is oxidized. 19. The metal fuse structure according to item 16 of the scope of patent application, wherein the dielectric layer is silicon nitride. 20. The metal fuse structure according to item 16 of the scope of the patent application, wherein the aluminum-silicon-copper alloy is deposited using a sputter method. 2 1. The metal fuse structure according to item 16 of the scope of the patent application, wherein the ingot copper alloy is a physical vapor deposition method (p h y s i c a 1 vapor deposition; PVD). Page 16