TW501235B - A method to form a low parasitic capacitance pseudo-SOI CMOS device - Google Patents

Abstract

A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated S/D extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.

Description

501235

[Background of the Invention] (1) Background of the Invention The present invention relates to the manufacture of integrated circuit devices, and more particularly = to a method for forming an electric circuit with a raised area and low parasitic capacitance in the manufacture of integrated circuits. Crystal method. (2) Description of conventional techniques. Current methods for reducing the source / drain capacitance usually include forming a source / dead region overlying an insulator on silicon (SOi). However, the SOI device is often affected by the floating body effect, which is difficult to overcome. It is desirable to provide a method for forming a pseudo SOI device with the advantages of SO I in the source / drain region, and It will eliminate this floating body effect. / A U.S. Patent No. 5,683,9 24 (Chan et al.) Teaches a method for forming the source, drain / drain regions. However, this method relies on the rise of the field oxide & isolation region to form a polycrystalline silicon interface on the source / drain region. In the method, it will be difficult to form a local interconnection using the raised south source / drain region. U.S. Patent No. 5,275,9 60 (Yamaguchi et al.) Teaches the formation of a raised polycrystalline silicon source / drain region followed by a τ-type gate. U.S. Patent No. 5,8 27,7 6 8 (L i η et al.) Discloses the formation of elevated source / drain regions 1 where the patterning of the polycrystalline silicon layer is performed before CMP, the source / drain regions Because it is formed by diffusion rather than implantation, it is impossible to carry out self-pairing of 2 stone in this method. U.S. Patent No. 6,015,740 (MUic_Strkalj.) Teaches a method for forming raised source / dead regions. U.S. Patent No. g, ㈣1, 6 9 7 (Chang et al.) Discloses a raised source / drain process for the polycrystalline silicon

Page 8 501235 V. Description of the invention (2) The __ layer is not flattened. US Special Spear-A method using selective epitaxy ^ 5, 84 3, 826 (Hong) to reveal a high source / drain method. Rise of the i-crystal at the top of the selective epitaxy [Summary of the Invention] One of the main objectives of the present invention is ^ ^

An effective and extremely manufacturable method for providing CMOS devices in the manufacture of integrated circuits. / Pseudo shallow trench isolation (pseudo-SOI) Another method of the present invention, the source /, and μ′Λ in the invention is to provide a pseudo-SOI device It is formed on Shi Xi during manufacturing. Another method of CMOS device of the present invention is M, where H is to provide a pseudo SOI interconnect. The source / drain region can be extended to serve as a local The source of the source / drain region is to provide a method of forming a body with an elongation and acting as a local interaction: the elevating source ... yet another method of the present invention, the JL ascending ancient , Ma: / Qi provides a method to form a pseudo S〇1 and the crystal is formed on the silicon, J: Zhong Xuan retrogradation /% r 1 4 extension to function as a local interconnect. /, And the source / drain The area can be extended to another aspect of the present invention. A device, a device, a capacitor, a capacitor, a capacitor, a capacitor, a capacitor, a capacitor, and a capacitor. The / drain region is formed on the body, and the transistor is formed on Shi Xi

Page 9 501235, Invention Description (3) The area can be extended to function as a local interconnect. According to the purpose of the present invention, & method of a pseudo-SOI device in a region, 70% ///, with a south source / drain is used as a local interconnect, the middle region for the isolation phase can be extended to- In semiconductor substrates, multiple === shallow trench isolation regions are provided with extended parts manufactured in active "2 = source / non-polar-hard cover curtain layers are covered in and above each gate plate, where the closed electrode On the side wall: On the pole, the 'dielectric gap wall is formed on each pole and the semiconductor substrate ::::: /// to cover the gate electrode and the hard cover curtain layer, Xiao polycrystalline = ^ back grinding' The end point of the grinding is the closed electrode, which: owes :: = money, so that the polycrystalline layer is lower than the isolation of the Xidou Renxiang Hao active interval Ai & on the shallow trench isolation area. : ,,, Jin Xiyu, will

The engraving shift of the spar slab of r ~ Ra is reduced. # _L A The local interconnection in the interval is desired, and it is covered in birch: adjacent active isolates the active area. ^ The Xijing silicon layer has not been removed by etching. + The source / drain region can be extended to ^ private. Or, the 'the hard mask layer is removed' is in contact with the shallow trench isolation. The drain region is completed in the production of a raised source circuit adjacent to the gate electrode to have a raised θ, and the transistor is formed in the integrated electrode and the pole / drain. [Figure No. Comparative description] 3 Gate electrode 10 Monocrystalline silicon semiconductor substrate M Shallow trench isolation region 14 Gate oxide layer 501235 V. Description of the invention (4) 16 Gate electrode 18 Hard cover curtain layer 20 Source / inverted region 20A Source Source / drain 20B source / drain 20C source / drain 20D source / drain; 22 bulkhead; 26 second polysilicon layer; 30 raised source / drain region 34 self-aligned silicide Layer 36 dielectric layer; 38 metal plug 40 metal line 42 protective layer [description of preferred embodiment] Now refer to FIG. 1 in more detail. It is a part of a partially completed integrated circuit device, which has a single crystal silicon semiconductor substrate 10 therein, and a shallow trench isolation (ST I) region 12 is formed in a manner known in the art. As shown in FIG. 2 As shown, a gate oxide layer 14 is deposited on the surface of the substrate by chemical vapor deposition (CVD) or thermal growth. The gate oxide layer has a thickness between about 15 and 100 angstroms. A polycrystalline silicon layer 16 is deposited on

Page 11 501235 V. Description of the invention (5) The gate oxide layer has a thickness of between about 1000 and 300 angstroms, and a hard mask layer 18 is deposited on the polycrystalline stone. On the layer, it has a thickness between about 2000 and 2000 Angstroms, which includes, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The hard mask layer is patterned in a conventional manner and is used to pattern and etch the polycrystalline silicon and the gate oxide layer to form a gate electrode as shown in FIG. 3; The doped source / drain extension or lightly doped non-polar (LDD) 2 0 is formed in the substrate by ion implantation, which uses at least the gate electrode 16/18 as the ion implantation. Masks can also be used-separate ion implant pattern masks (NM0S and PM0S), or appropriate LDD pocket / aperture (p0cket / halo) implants. Referring now to FIG. 4, a low dielectric constant layer is deposited on the surface of the substrate 'and is removed by anisotropic etching, leaving a spacer 22 on the side wall of the gate electrode. The spacer material layer should have a dielectric constant of less than 4.0. Secondly, any original oxide is removed from the surface of the substrate (especially the active area adjacent to the gate electrode) using a hydrofluoric acid (HF) immersion solution or a steam bath. Secondly, a second polycrystalline silicon layer 26 is deposited on the substrate to a thickness between about 15 and 300 Angstroms, and the polycrystalline silicon layer 26 is deposited larger than the gate electrode 16/18. Height, as shown in Figure 5. Referring now to FIG. Β, the polycrystalline silicon layer 26 is polished using chemical mechanical polishing (CMP), and the polishing end point is the hard mask layer 18. Now, the polycrystalline stone layer 26 is slightly worm-etched, so that the polycrystalline stone layer 26 is lower than the hard mask layer 18, as shown in FIG. After CMP, about one third of the gate stack thickness is removed by etching against the second polycrystalline silicon layer 26.

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5. Description of the invention (6) The second polycrystalline silicon layer 26. The polycrystalline silicon layer 26 is now shown in the shallow trench isolation region, and during active engraving, the hard mask 18 will extend to the shallow trench isolation region because the shallow trench isolation region is extremely polarized. thick. Prototype and etch to divide by forming an open area, as shown in Figure 8. On the etched gate electrode 16 and the polycrystalline silicon region 26. This does not significantly increase the capacitance. If it is desired to use the polysilicon region 26 as a local interconnect, the patterning of the polysilicon between the source / drain of only two transistors is omitted. For example, 'as shown in Figure 8, the source / drain 20c and ㈣ are isolated from each other, because the polycrystalline silicon layer on the shallow trench isolation region that isolates 20C and 20D has been removed for a while Said Shi Xi layer 26 forms a local interconnection between source / inverted regions 20a and 20B. The process of the present invention allows the polycrystalline silicon layer to be used as a local interconnection without increasing the capacitance and Leakage. Ben Maoming's clothing uses a mask to form source / drain polycrystalline silicon on the source / drain region. This allows the polycrystalline silicon to function as a transistor source / drain, self-aligned silicided local interconnects, with significantly reduced parasitic capacitance and increased junction leakage. The use of this source / drain polycrystalline silicon can significantly increase the bulk density. The planarization has nothing to do with the chemical mechanical polishing used in the subsequent dielectric. The hard cover 18 is now removed with, for example, hot phosphoric acid, as shown in Figure 9. Now, the inter electrode 16 and the polycrystalline silicon layer 26 are doped by ion implantation. The N-pass device is doped separately from the p-channel device. For example, the n-channel device is doped with Kun at a dose of about 2 £ 15 to 5 £: 15 at 0 m / cm2.

Page 13 501235 V. Description of the invention (7) The energy between the four is about 40 to 80 K e V. The P-channel device is doped with boron. The dosage is between about 2E 1 5 to 5E1 5 a tom / cm2 and the energy is between about 3 to 8 KeV. The dopant is activated by rapid heating annealing between about 1000 and 1050 t: This will form an elevated source /; and a pole region 30, as shown in FIG. 10 . Doping by ion implantation (rather than diffusion) allows better dopant concentration and junction depth control by adjusting the dose and energy.

The gate 16 and the source / drain region 20 are metallized 34, as shown in the figure. For example, a layer of metal such as titanium is deposited on the substrate. A rapid heating process (RTP) will cause the metal to react with the underlying polycrystalline silicon to form a self-aligned silicide layer 34 on the polycrystalline silicon surface, as shown. The unreacted metal on the partition wall 22 and the shallow trench isolation area 12 is removed by the meal. Continue processing in the manner known in the art--q-1-for example, it is shown that the surface electrical layer 36 covers the self-aligned silicided gate electrode and rises; the electrode / drain region on. The dielectric layer 36 may be, for example, borophosphosilicate glass. A contact opening is formed through the dielectric layer to complete the electrical connection. For example, ^^ metal plug 38 is connected to a self-aligned silicified raised source / drain region η μ = connected to a metal line 40 overlying it. Form a pile

. The integrated circuit device is completed with only 42 layers. The manufacturing process of the present invention provides a manufacturing method for manufacturing a pseudo-SOI CMOS device. The formed source / drain region 30 is a part of the body 1 "= a rising region on the shallow trench isolation region 12. The transistor: the electrode P% is on a silicon substrate to avoid floating body effects. The invented sum pole can be extended to act as a local interconnect and via parasitic capacitance

501235

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501235 Brief description of the drawings In the drawings that form the content of the description, the following drawings are shown: Figures 1 to 11 are cross-sectional views and schematically illustrate preferred embodiments of the present invention. Fig. 12 is a cross-sectional view schematically illustrating an integrated circuit device manufactured according to a preferred embodiment of the present invention.

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Claims (1)

J Shenying's patent scope is in the method of manufacturing integrated circuits > transistor methods, including the right, the south source / drain region, \, U 6 negative · \ trench isolation region is set in a Feng, the area isolates adjacent active areas; i, where the shallow trench isolation electrode is connected to the source; the semiconductor substrate in and above the active area is made to cover I to each of the gates On the electrode, a hard cover is formed; 丨 an electrical gap wall is formed on the side wall of the gate electrode for a long time, and a plate; s' M covers the gate electrode and the semiconductor substrate The pound I ag is: owing,: 3 ":, the grinding end point is on the hard cover layer; the nuclear electrode Γ Xi Xi layer returns money, so the polycrystalline Xi layer is lower than the closed enemy / > U: : Isolation of the active zone is desired, and it will be covered there ;: the polycrystalline stone layer on the away zone is removed at a later time; the implanted two-layer hard cover curtain layer is removed; and ΐΐϊ :::; , The raised source / non-polar region is in the closed polycrystalline silicon layer, and in the fabrication of the integrated circuit 2. Rushen = special ^ jDi = the source / drain region of the electricity Crystal The formation of silicon oxide, nitrogen: silicon method 'wherein the hard cover layer is composed of di-emulsified stone and lice silicon oxide and the thickness of the female is about -20 to 200 angstroms. 'Asia has a method of 3 .: Ϊ 4 around item 1', wherein the dielectric spacer comprises a material having a W electric suspending number less than 4.0. 501235 6. Application scope of patent " 4. The method of item No. VII of the patent application, wherein the polycrystalline silicon layer has a thickness between about 100 and 300 Angstroms. 5. The method according to the first item of the patent application, wherein the step of regrinding the polycrystalline silicon layer includes chemical mechanical polishing. 6. The method according to the first item of the patent application, wherein the step of etching back the polycrystalline silicon layer is performed until the polycrystalline silicon layer is lower than one third of the gate height. 7. The method according to item 丨 of the patent application scope, wherein local interconnections in adjacent active sections are desired, and the polycrystalline silicon layer covering the shallow trench isolation area is not removed in a moment. 8. The method according to item 1 of the scope of patent application, wherein the step of implanting the ion includes: a dose of 2] £ 15 to £ 5: 15 at 0 m / cm2 of arsenic ions to enable S40 to 80 KeV An N-channel device is formed by implanting in the polysilicon gate electrode and the raised source / drain region. 9 · The method of claim 1, wherein the ion implantation method comprises implanting a boron ion at a dose of 2E15 to 5E15 at 0m / cm 2 with an energy of 3 to 8 KeV into the polycrystalline silicon gate. The electrode and the raised source / drain region form a p-channel device. 10. The method of item 1 in the scope of patent application, wherein the step of driving the ions includes a rapid heating annealing between about ^ ⑽ to ^ ". U. The method of item 丨 in the scope of patent application After the step of implanting and driving the ions, the method further includes metal silicidation of the gate electrode and the raised source / drain region. 1 2.-In the manufacture of integrated circuits Formation of a raised source / drain region Page 18 501235 6. The method for applying a patent scope transistor includes: providing a shallow trench isolation region in a semiconductor substrate, wherein the shallow trench isolation region isolates adjacent active regions, and polysilicon gate electrode The connected source / drain extensions are manufactured in and above the semiconductor substrate in the active area, and a hard mask layer covers each of the gate electrodes; a dielectric gap is formed on each of the gates Depositing a polycrystalline silicon layer on the sidewall of the electrode to cover the gate electrode and the semiconductor substrate; The polycrystalline stone layer is ground back, and the grinding end point is at the hard mask layer. Second, the polycrystalline silicon layer is etched back, so that the polycrystalline silicon layer is lower than the gate electrode. Second, the isolation in the adjacent active section As desired, the polycrystalline silicon layer covering the shallow trench isolation area is etched away; secondly, the hard mask layer is removed; ions are implanted and driven to form the raised source / drain A pole region in the polycrystalline fragment layer adjacent to the gate electrode, metal fragmentation of the gate electrode with the rising south source electrode and the pole region; A dielectric layer is deposited, covering the gate electrode and the raised source / drain region, and making an electrical connection in an opening through the dielectric layer to electrically connect to a portion of the gate electrode And raise the source / drain region to complete the fabrication of the integrated circuit. 1 3. The method according to item 12 of the scope of patent application, wherein the hard cover curtain layer is composed of Page 19 6. The scope of the patent application: Monolithic oxide and nitrided stone disk tube g. The dielectric spacer includes the polycrystalline silicon layer having the polycrystalline silicon layer back to D, and the polycrystalline silicon layer having a thickness of about 200. To 200 Angstroms " Select from among the groups of, and, and have 14 · Such as the scope of patent application No. 12: $ method Contains materials with a dielectric constant less than 4.0. 15. The method according to item 12 of the patent application range is about 100 to 300 Angstroms in thickness. / 16 · If the method of the scope of patent application No.12, the step of grinding includes chemical mechanical polishing17 · If the method of the scope of patent application No.12, the step of etching is carried out to // Up to the electrode height. The spar layer of Haixi is lower than one-third of the idle pole. 1 · As the method of removing heat from the local interconnect A in the patent scope of Shenyan, it is desirable that the interconnect is adjacent to the active area. As far as possible, the polycrystalline silicon layer is not removed by etching. The method of the 192 specialists and 12 items above, where the ion implanted μ / step 3 has the arsenic ion at a dose of 2E15 to 5E15 atom / cm2 + implanted into the polysilicon gate with energy of 40 to 80 KeV Pole " and the pole area, and the shape of the channel device. Neutralize the source 202. The method according to item 12 of the patent application, wherein the ion implantation includes implanting the ion at a dose of 2E15 to 5E15 atom / cW at an energy of 3 to 8 K eV. The polysilicon gate electrode forms a p-channel device in the raised source / dead region. 2 1 · The method according to item 12 of the patent application, wherein the step of driving in the ions includes rapid heating annealing at a temperature between about 1000 to 1 050 ° C. Page 20 IHHI 501235 6. Application scope 22. —A method for forming a transistor with a raised source / drain region in the manufacture of integrated circuits, including: setting a shallow trench isolation region on a semiconductor In the substrate, the shallow trench isolation region isolates an adjacent active region, and a polysilicon gate electrode and a connected source / drain extension are fabricated in and above the semiconductor substrate in the active region. A cover layer covers each of the gate electrodes; a dielectric spacer is formed on a side wall of each of the gate electrodes; A polycrystalline silicon layer is deposited to cover the gate electrode and the semiconductor substrate; the polycrystalline silicon layer is polished back, and the polishing end point is on the hard mask layer; secondly, the polycrystalline silicon layer is etched back, so that The polycrystalline silicon layer is lower than the gate electrode; secondly, where the isolation of the adjacent active region is desired, the polycrystalline layer layer covering the shallow trench isolation region is engraved and removed in the adjacent active region; The local interconnection of the interval is desired, and the polycrystalline silicon layer covering the shallow trench isolation region is not removed by etching; secondly, the hard mask layer is removed; Implanting and driving ions to form the raised source / drain region in the polycrystalline silicon layer adjacent to the gate electrode; metal silicidating the gate electrode and the raised source / drain region Depositing a dielectric layer overlying the gate electrode and the raised source / drain region; and making an electrical connection in an opening through the dielectric layer to electrically connect to a portion Page 21 501235 6. The gate electrode and raised source / drain region within the scope of the patent application complete the fabrication of the integrated circuit. 2 3. The method according to item 22 of the scope of patent application, wherein the hard mask layer is selected from the group consisting of silicon dioxide, silicon nitride and silicon oxynitride, and has a range of about 200 to 2 0 0 Angstrom thickness. 24. The method of claim 22, wherein the dielectric spacer comprises a material having a dielectric constant less than 4.0. 25. The method of claim 22, wherein the polycrystalline silicon layer has a thickness between about 100 and 300 angstroms. 2 6. The method of claim 22, wherein the step of back grinding the polycrystalline silicon layer includes chemical mechanical polishing. 27. The method of claim 22, wherein the step of etching back the polycrystalline silicon layer is performed until the polycrystalline silicon layer is lower than one third of the gate electrode height. Page 22