TW409424B - Field effect transistors with vertical gate side walls and method for making such transistors - Google Patents

Abstract

The present invention discloses a Metal oxide semiconductor Field effect transistor (MOSFET) comprising a drain region and source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further comprises a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process, implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack. The present invention further discloses a method for the formation of field effect transistors (FETs) and general, and metal oxide field effect transistors (MOSFETs) in particular, comprising the following steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIF) process; depositing a side wall layer; removing the side wall layer from horizontal surface of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers. The present invention further discloses a Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that is fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.

Description

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 11 409424 A7 B7 V. Description of the Invention (1) Technical Field The present invention relates generally to (MOSFET), and in particular a metal oxide semiconductor field effect transistor with a vertical gate sidewall. BACKGROUND OF THE INVENTION Field-effect transistors (FETs) are the basic building blocks of today's integrated circuits. Such transistors can be constructed on traditional substrates (such as silicon substrates) or silicon insulator substrates. In both cases, the so-called deep implantation in the substrate is used to improve the performance of the transistor, to provide heavy impurity insulation of complementary metal oxide (CMOS) integrated circuits, to reduce the current gain of parasitic vertical transistors, and to reduce parasitic locking. Effects, and the above are just some of the reasons for using deep implants. In CMOS technology, such deep implants are called p-wells or n-wells. If NMOS transistors (ρ-type wells) and PM0S transistors (η-type wells) are to be formed within the same matrix, such p-type wells or η-type wells need to be deeply implanted. In addition to these deep implants, threshold adjustment implantation (VT adjustment implantation) and penetration implantation are also commonly used to set the appropriate threshold voltage (V τ) of each transistor and prevent penetration. A conventional MOSFET 10 is shown in FIG. 1A. Such a MOSFET is generally formed on a silicon substrate 1 1 and includes a doped source region 14 and a doped drain region 12, and the source region 14 and the drain region 12 are respectively disposed in a gate. The left and right sides of the conductor 1 3. The gate conductor 13 is separated from the channel 17 by the gate oxide layer 15, and the channel 17 is located between the source region 14 and the drain region 12. LOCOS or multi-buffered plastic LOCOS insulation (not shown) is commonly used to provide insulation for adjacent transistors. -4---. — ^ 1-—II ^^ 1 »Taxi, 〇 {. II--ί-_ (Please read the note on the back " Matter # to fill in this page) The standard of this paper applies Chinese national standards ( CNS) A4 specifications (210X 297 mm) A7 A7 B7 V. Description of the invention (2 Miscellaneous: Degree and distance (tangent line Hpa_Hpa) as a function relationship is shown in Figure 2 = the diagram is a schematic diagram, and is only used to show the known, based on The MOSFET of the present invention. The use of these. These hybrids '21} / ten thousand centimeters. The interface 18 leading to the channel 17 is not subject to the inclined sidewalls 16 from the hybrids 1, two due to the horse gate pillar 13, which is the arsenic concentration. With the MOSF ^ T Φ function: Decreasing (segmented concentration of * 18). In the traditional, deeper cloth plants (such as boron; P-type) and threshold-adjusted indium p-type) extend through the entire length of the transistor. In-depth planting hunting is achieved by 2 materials technology. These implants are usually implemented when the actual heart preparation matrix is formed, and the binding concentration of B + In is about 2 * 10Λ {17} / cm3. πNote The traditional process cannot provide the threshold adjustment and penetration implantation which is limited to the channel ^ 7 and below. Objective 'There are also known FET manufacturing methods that can achieve a F E T with a threshold adjustment implant and / or penetration implant that is clearly defined and only below the channel. * There is background technology related to various aspects of implanting impurities. U.S. Patent No. 4,471,523 and U.S. Patent No. 5,547, m are two examples, and the above two patents are currently assigned to the right holders of this patent application. The size and shape of the polylithium gate, which is particularly important in traditional and future reduction MOSFETs, and its quality. In order to manufacture memory chips and remote-control devices with higher integration densities than we can currently achieve, we must find a way to further reduce the gates used for such wafers and devices, and to improve the accuracy of manufacturing such gates. -5 --------- ^ ------ '11 ------ (Please read the note at the back of' Fatigue before filling this K ') Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The Consumer Cooperation of the Central Government Bureau of the Ministry of Finance and Economics, printed by the agency 409424 A7 s ^ ____ V. Description of the invention (3) The basic components of a traditional MOSFET 10 are shown schematically in Figure 1 ^ This FET 10 is generally composed of silicon The matrix η includes a doped source region 14 and a doped drain region 12, and the source region 14 and the drain region 12 are respectively disposed on the left and right sides of the polysilicon gate 13. The gate pillar i 3 is separated from the channel 17 by the oxide layer 15 and the channel 17 is located between the source region 14 and the drain region 12. Under the polysilicon gate 1 3, the oxide layer! 5 Acts as a gate oxide 'In conventional FETs' the gate oxide under the polysilicon gate is thicker because the portion of the oxide layer i 5 that was not covered by the polysilicon gate during polysilicon RIE is attacked' as follows As mentioned, please note that the source / channel and drain / channel junctions are not defined as sudden changes. The closer to the actual channel, the lower the impurity concentration, that is, the source / channel and drain / channel junctions 18 are not clearly defined. This is mainly caused by the inclined side wall 16 of the gate 13, and the inclined side wall 16 allows the hybrid rabbit to reach the hard matrix near the edge of the gate (overlapping the gate). When the drain region I 2 is planted from the top, When the source region is 14, this results in an increase in the source and drain resistance, high overlap capacitance 'and an unclearly defined effective channel length, which may lead to deterioration of device performance. In the latest technology, silicon active ion etching (RiE) and photoresist masks are used to define the polysilicon gates of many MOSFETs, and these MOSFETs include complementary metal oxide semiconductor (CMOS) FETs. The RIE process must meet Two requirements. The poly gate should have completely vertical side walls, and in addition, it must be ensured that the RIE process stops at the gate oxide 15 at the bottom of the poly silicon gate 13 and that the gate oxide 15 is not damaged. —Generally speaking, gate oxides! 5 is very thin (in the range of a few nanometers) and becomes thinner and thinner when the FET is further reduced. When processing the entire wafer, the thickness of the polysilicon layer will change, and the polysilicon layer (please read the precautions on the back before filling out this page). Installation * -0 5. Description of the invention (4)-Etched to become crystal Polysilicon gate of all MoSFETs. To ensure that all water gates are properly defined from f, the etch time must be adjusted so that all polysilicon gates are etched down to the thin interlayer oxide 15, and these polysilicon gates consist of a thick polysilicon layer. A polysilicon gate on one section of the wafer. However, the excessive etching of this animal leads to a reduction in the local thickness of the gate oxide 15 adjacent to the polysilicon gate 13 (shown schematically in Figure i), because the polysilicon etching process is not sufficiently selective (please note the high selectivity It means that an etching process only attacks the material it wants to etch, such as polysilicon in this example, but does not attack the gate oxide). In other words, the conventional polysilicon RIE etching process not only attacks polysilicon, but also the oxide layer 15 ^ Due to the low selectivity, the thickness of the oxide layer 15 adjacent to the polysilicon layer 13 is lower than the original thickness of the oxide layer The thickness (see below the polysilicon gate 13) is shown schematically in Figure 1. The essence of the currently used RIE polysilicon etching window process is improved selectivity, which will reduce the directionality of the etching and cause unwanted non-vertical (tilted) polysilicon gate sidewalls 16. In other words, when a conventional polysilicon RIE process is used, the layer 15 is attacked, and thus its thickness varies throughout the wafer. Polysilicon RIE chemistry can be adjusted to improve the polysilicon / oxide selectivity, but then the RIE name becomes more isotropic, resulting in more inclined sidewalls. Printed by the Central Government of the Ministry of Economic Affairs and Consumer Cooperatives --- 11-n --- I-J 1- T. 1 _ (Please read the precautions for the reasons and fill in the original education} as mentioned earlier When shrinking the MOSFET, the gate oxide must become thinner. It should be immediately clear that the thinner the gate oxide, the less it can accept over-etching. In other words, the etching selectivity must be improved to make the polysilicon gate very small. The size of the gate oxide thickness of the CMOS FET below 0.1 micron, such as less than 3 nanometers, any over-etching will damage the device's efficiency. 1 ^^^ Applicable to China National Standard ((^ 5) 6 4 Specification (210 \ 297 公 犮) ^ 0d424 A7 ___ ~~-__ ^ V. Description of the invention (5) The gate length LG of a conventional transistor is defined by photolithography and a subsequent RIE step, as discussed briefly above. Because The resolution of the photolithography method is equal to the wavelength of the exposed light, so the gate length is limited to about 150 nm. Traditional photolithography methods cannot be used to make smaller gates. The state-of-the-art manufacturing technology can use 248 nm Irradiation to produce 250 nm wide features. Currently, when trying to get below 150 Light-based construction methods are the bottleneck when it comes to micron-sized structures. The most advanced lithography systems used to make current DRAMs, for example, are very expensive. The semiconductor industry wiring diagrams required 18 in 2001. The nanometer cutting edge manufacturing method 'will require 70 nanometer manufacturing method in 2011. 3 When moving to smaller feature sizes, other processes, such as x-ray etching,' become attractive 'but required The investment is extremely large. Therefore, the technology that is compatible with most of the existing processes is of great value in nature. The Central Consumers Bureau of the Ministry of Economic Affairs has printed a MOSFET manufacturing method with no known MOSFET manufacturing method that can achieve sub-lithographic length. And vertical (non-inclined) side-wall gated MOSFETs. In addition, traditional techniques are not suitable for making reduced FETs, and these FETs have gate lengths of 150 nm and smaller 'and non-destructive open oxides less than 5 nm thick The background technology with some broad interests is related to certain aspects of the invention, such as U.S. Patent No. 4: 758,528, U.S. Patent No. 4,43〇, 791, and U.S. Patent No. 4,636,822, and the above three patents are currently assigned to the patentee of the clothing patent application. This patent application is related to U.S. Patent Application No. 08 / ... (the applicant's Reference __ -8- Standards applicable to 1 national standard (CNS) Λ4 is present (210X297 mm) ~~~~-: A7 409424 ___B7 V. Description of the invention (6)-tu I II ..... I --If I * 's -I ^^ 1 1------I— IX »3'-=-0 (Please read the note r on the back before filling this page) The number is FI 9-97-165 ), The name is 'FIELD EFFECT TRANSISTORS WITH IMPROVED IMPLANTS AND METHOD FOR MAKING SUCH TRANSISTORS'; US Patent Application No. 08 / .... (Applicant's reference number is FI 9-97-166), and the name is " METHOD FOR MAKING FIELD EFFECT TRANSISTORS HAVING SUB-LITHOGRAPHIC GATES WITH VERTICAL SIDE WALLS " and U.S. Patent Application No. 08 / .... (Applicant's reference number is FI 9-97-164) and the name is " FIELD EFFECT TRANSISTORS WITH VERTICAL GATE SIDE WALLS AND METHOD FOR MAKING SUCH TRANSISTORS ", and all three patent applications were filed on the same day It is currently assigned to the right holder of the present invention. These patent applications are mentioned here for reference. There are currently no known MOSFET manufacturing methods that can implement MOSFETs with vertical (non-slanted) sidewalls. In addition, conventional techniques are not suitable for manufacturing reduced FETs, and these FETs have non-destructive gate oxides with a thickness of less than 5 nm. It is an object of the present invention to provide FETs with threshold adjustment implants and / or penetration implants, and these implants are only located below the channel. Printed by the Central Laboratories of the Ministry of Economic Affairs, Consumer Cooperatives One of the objectives of the present invention is to provide FETs with a well-defined threshold adjustment implant and / or penetration implant. Another object of the present invention is to provide a method for constructing a FET with a threshold adjustment implant and / or a penetration implant, and the implants are only located below the channel. Another object of the present invention is to provide an application In order to have a clear boundary -9- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 409424 A7 B7 V. Description of the invention (7) The threshold adjustment and / or penetration FET. It is an object of the present invention to provide a method for forming MOSFETs which have well-defined channel lengths below 150 nm. It is an object of the present invention to provide a MOSFET having a well-defined channel length, a small source and drain resistance, and a minimum overlapping capacitance. An object of the present invention is to provide a MOSFET having a reduced size, and particularly a MOSFET having a size smaller than 0.1 micron. It is an object of the present invention to provide a method for forming MOSFETs, which have clearly defined channel lengths, the smallest source and drain resistances, and the smallest overlapping capacitances. Another object of the present invention is to provide a method for forming MOSFETs, and the MOSFETs have a reduced size, and particularly a size less than 0.1 micron. SUMMARY OF THE INVENTION The above-mentioned objective can be achieved by providing a novel and original method for constructing a FET, which allows fabrication of a threshold adjustment implant and / or a FET implanted directly under the channel region. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs I n '-!---I— 1 * · 0Ί--n-Hi 1—] l ^ i— Ti -¾., V5-i (Please read the first Note: Please fill in this page again.) This method includes the following steps: • forming the dielectric stack on the semiconductor structure; • defining the etching window on the dielectric stack, and the etching window has the lateral size and shape of the gate hole to be formed; The reactive ion etching (RIE) process defines the gate of the dielectric stack by transferring the etching window to the dielectric stack: -10- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 409424 Central Bureau of Standards of the Ministry of Economic Affairs — Printed by Industrial and Consumer Cooperatives Λ7 B7 V. Description of the invention (8) • Planting threshold adjustment impurities and / or penetrating impurities through the gate hole; • Depositing a gate conductor so that the gate conductor fills the gate hole; • Removing some gate conductors 'And these gate conductors cover the half of the conductor structure surrounding the gate hole; • Remove at least a portion of the dielectric stack. This original method replaces—parts of these traditional MOS and CMOS process steps—usually used to form the gate conductor and used to form the threshold adjustment implant. There are different ways to modify the above process, and the detailed description will describe this. Some of the advantages of this original process are: • Threshold adjustment implant and / or penetration Pegasus is located directly below the channel: • Threshold adjustment implant and / or penetration implant is automatically calibrated to be formed in the gate hole Brake conductors; • Threshold adjustment and / or expansion of the penetration area is clearly defined and can be accurately controlled (please note that there are always some horizontal and vertical diffusions). The achievement of these advantages is mainly due to the fact that the threshold adjustment implantation and / or penetration implantation are implanted through the holes formed between the dielectric stacks. The MOSFET according to the present invention has a source / drain junction surface capacitance lower than that of the conventional MOSFET, and this leads to an improvement in performance. The aforementioned goals can be achieved by providing a novel and original method for constructing FETs. This method includes the following steps: • Forming a dielectric stack on a semiconductor structure: • Defining an etch window on a dielectric stack: -11-This paper size is applicable to China National Winter Standard (CNS) A4 (2l0x 297). ^ ϋ-HE-·-'士 r --- 1 ^^^ 1 ^^^ 1 nn ffJ I · {谙 Read the notes on the back before filling in this page) Λ7 B7 ^ 09424 V. Description of the invention (9 Defining the gate hole of the dielectric stack by using active ion engraving (gjE) to build α, to transfer money engraved windows to the dielectric stack;

In--I It-1 ^^-^-D (Please read the notes on the back > 0 before filling in this page) Deposit a side wall to see; Remove the side wall layer from the horizontal surface of the dielectric stack and gate hole so that The sidewall spacer still exists' and this reduces the lateral size of the gate hole; a gate conductor is deposited so that the gate conductor fills the gate hole; some closed conductors are removed, and these gate conductors cover the part surrounding the free-hole structure; a Removing at least a portion of the dielectric stack; and removing the sidewall spacers. This original method uses the aforementioned sequence of steps to replace the traditional Mos or CMOS manufacturing steps (—Shao Fen, and the steps in this part are usually used to define idle conductors. The above process can be modified in different ways, and The detailed description will describe this. Reading the detailed description and the drawings should make clear the advantages of this method. One of the advantages: traditional photolithography steps can be used to form sub-lithographic gates. Another advantage is that the gates The side walls of the pillars are vertical. The Consumer Co-operative Society of the Central Standards Bureau of the Ministry of Economic Affairs has stated that the aforementioned goals can be achieved by providing a novel and original method for forming FETs. This method includes the following steps: • Forming a dielectric stack on A semiconductor structure, and the semiconductor structure includes at least an entire oxide layer: • An etch window is defined, and the etch window has a lateral size and shape of a gate post: -12- The dimensions of this paper are applicable to Chinese national standards ( CNS) A4 specification (210 X297 Gongchu) 409424 A7 B7 Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China (5) Invention Description (1〇) The reactive ion etching (RIE) process defines the gate hole of the dielectric stack by transferring the etching window to the dielectric stack; • depositing a gate conductor so that the gate conductor fills the gate hole: • removing some gate conductors, and the gate conductors cover and surround The semiconductor structure part of the gate hole: • Remove at least a part of the dielectric stack. This original method uses the aforementioned step sequence to replace a part of a traditional MOS or CMOS process step, which is usually used for The definition of the gate conductor. The above process can be modified in different ways, and the detailed description will describe this. Reading the detailed description and the drawings should make clear the advantages of this method. However, some advantages of the side wall of the gate post are vertical. Another advantage of the original structure is that the thickness of the SiO_ {2} pad oxide is uniform, that is, the thickness of the pad oxide is uniform on the top of the source region and the non-electrode region, and is uniform throughout the wafer. It will not change. This will then ensure that the depth of the source-drain junction is not beta altered throughout the wafer. In conventional devices, where the thickness of the entire oxide changes, the source and The depth of the pole junction is not uniform. This is particularly important for extended junctions. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in detail below with reference to the following schematic shapes (not depicted in terms of physical size ratios): Figure 1A is the basic structure of a traditional FET The figure shows the cross section of the basic structure of the FET. -13, i ^^^^ 1 1 ^ 1 ^ 1 _ 1 (Please read the note on the back before filling this page ) 409424 V. Description of the invention (11)

Hpa) is a schematic diagram of the functional relationship. Fig. 2A is a schematic cross section of the basic structure of a FET according to the present invention. Figure 疋 is a schematic diagram of the relationship between the impurity concentration and the distance (along HpA_HpA) of the FET according to the present invention. Figure 3A shows the tf-substrate, which is covered by a pad oxide and a nitride layer. Figure jB shows an intermediate manufacturing step after the photoresist has been patterned for STI or Locs insulation. FIG. 3C shows an intermediate manufacturing step in which a photoresist has been used as a mask to etch the STI channel. Figure 3D shows an intermediate manufacturing step in which the STI channel has been filled with a TEOS layer. Figure 3E shows an intermediate manufacturing step in which part of the TEOS and nitride layers have been removed by planarization. Figure 3F shows an intermediate manufacturing step in which a deep implant is passed through the nitride layer. Figure 3G shows an intermediate manufacturing step in which additional layers have been formed. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs fn 1—-ί ---.------- si _ ϋ ----- Ding «3 -1 (Please read the notes on the back before filling this page ) Figure 3 shows the intermediate manufacturing steps after the photoresist has been added, subjected to photolithography, and a gate hole with a vertical sidewall has been formed. Fig. 31 shows an intermediate manufacturing step 'in which the threshold adjustment implantation and / or penetration implantation is introduced into the substrate through a gate hole. Figure 3 J is an enlarged view of one of the gate holes 'after the photoresist has been removed' and the TEOS and pad oxide at the bottom of the gate hole have been etched away. -14- This paper size applies to Chinese National Standards (CNS > A4 size (210 × 297 public epidemic) 409424 Λ7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs B7. V. Description of the invention (12) Figure 3 K shows an intermediate manufacturing step 'Where the gate hole is filled with polysilicon. Please note that' before the gate hole is filled ', a thin gate oxide layer is formed at the bottom of the gate hole. Figure 3L shows an intermediate manufacturing step in which the polysilicon has been planarized. Figure 3M shows an intermediate manufacturing step in which a dielectric stack containing many layers has been removed so that a polysilicon gate with vertical sidewalls is left. Figure 3N shows an intermediate manufacturing step in which impurities are introduced to define the source region Figure 4 is a schematic cross-section of another basic structure of a MOSFET according to the present invention. Figure 5 A shows a substrate, and the substrate is covered by a pad oxide and a nitride layer. Figure 5 B shows an intermediate manufacturing step after the photoresist has been patterned for etching with ITO or LOCOS insulation. Figure C shows an intermediate manufacturing step in which the photoresist has been used to etch the STI. The trench is masked. Figure 5D shows an intermediate manufacturing step, in which the STI channel has been filled with a TE0S layer. Figure 5E shows an intermediate manufacturing step, in which a portion of the TE0s and nitride layer has been flattened. Figure 5F shows an intermediate manufacturing step, in which an additional layer has been formed. Figure G shows that the photoresist has been added, has been patterned by photolithography, and has formed a middle after a gate hole with a vertical sidewall. Manufacturing steps. _-15- This paper size applies to Chinese National Standard (CNS) M specification (2) 〇 > &297; Bus, 1 · (Please read the notes and notices on the back before filling this page) kl B7 409424 V. Invention Explanation (13) Figure 5H is an enlarged view of one of the interrogated holes after the photoresist has been removed and teOS has been removed. Figure 5I shows an intermediate manufacturing step in which a sidewall layer has been deposited. Figure 5J shows a The intermediate manufacturing step 'where the sidewall layer has been removed from the horizontal surface leaving the sidewall spacer layer in the gate hole. Figure 5K shows an intermediate manufacturing step' where the gate hole is full of dreams. Please note that the closed hole is filled _ A thin oxide layer or other insulating layer is formed at the bottom of the gate hole. Figure 5L shows an intermediate manufacturing step 'where polysilicon has been removed by planarization. Figure 5M shows an intermediate manufacturing step which contains many layers The dielectric stack has been removed so that a poly-second pillar with vertical sidewalls is left. Figure 5N shows an intermediate manufacturing step in which impurities are introduced to define the source region and the electrode region. Figure 6 is a MOSFET according to the invention The Other-Basic Structure Figure 7A shows the tf — substrate, and the substrate is covered by — pad oxide and a nitride layer. Figure 7B shows the photoresist has been patterned for STi or Locus insulation. One of the intermediate manufacturing steps after etching. Figure 7C shows an intermediate manufacturing step, and the middle photoresist has been used as an etching mask to etch the TI channel. Figure 7D shows an intermediate manufacturing step 'where the m channel is full A TEOS layer. I-I-. ^^ 1 I----] ^ — I * 1---1 ^ — II-— ^ 1 — ^ 1 \ ~ »» -Β (锖 Read the first (Please fill in this page for remarks.) 16- Α7 Β7 409424 Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (14) Figure 7E shows an intermediate manufacturing step, in which TEOS and one of the nitride layers have been borrowed. It is removed by planarization. Circle 7F shows an intermediate manufacturing step, in which an additional layer has been formed. Figure 7G shows that after the photoresist has been added, it has been patterned by lithography, and a gate hole with a vertical sidewall has been formed. One of the intermediate manufacturing steps. Figure 7 Η is an enlarged view of one of the gate holes, after the photoresist has been removed, and the bottom of the gate hole After the TEOS and pad oxide have been etched away. Figure 71 shows an intermediate manufacturing step in which the gate hole is filled with polysilicon. Please note 'Before the gate hole is filled, a thin gate oxide layer is formed on the bottom of the gate hole. Figure 7J shows an intermediate manufacturing step in which polysilicon has been removed by planarization. Figure 7K shows an intermediate manufacturing step in which a dielectric stack containing many layers has been removed so that a polysilicon gate with vertical sidewalls is left Figure 7L shows an intermediate manufacturing step in which impurities are introduced to define the source and drain regions. Fig. 8 is a schematic cross section of another example according to the present invention. Fig. 9 is a schematic cross section of another example according to the present invention. Explanation of preferred examples In the following description, a semiconductor of doped with η + or P + means a heavily doped semiconductor. These semiconductors usually have an impurity concentration of at least 1〇Λίΐ9 > ^ 1 (^ {22} / cubic centimeter 3 !! or 1) doped region—generally ^; 1 * 10Λ {ί7} to 1 * 10Λ {18 } / Cm3 impurity concentration. And or, the doped region has a concentration of about 10Λ {16) / cm3. -17- This paper size applies to Chinese national standard (CNS > Α4 size (2! 0 × 297 mm) ~ -------^^^^ 1 ^^^^ 1 Iff ^^^^ 1 ^^^ ^ 1 ^^^ 14 1 / fl ^ i ^^^^ 1 ~ ...... ^^^^ 1ΎJJ. Λ ", \ έ (谙 Please read the note on the back of the 'Implementation before filling this page) Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 409424 ΑΊ Β7 V. Description of Invention (15) When the word FET is used in this article, it means any type of field effect transistor, including MOSFET, CMOS FET, NMOS, PMOS, Etc. The FET 20 according to the present invention is shown in FIG. 2A, and the FET 20 is formed on a semiconductor substrate 21. For example, the substrate may be a silicon substrate 3. In this example, the drain region 22 and the source region 24 are formed by It is defined by n + impurities. Elements that are very suitable as n-type impurities include phosphorus, rhenium, and antimony. For example, in this example: using antimony as an impurity. To define a p-type source region and a drain region, Boron, indium, and gallium can be used. Polysilicon gate 23 is located on top of the thin silicon dioxide gate oxide 2s, as shown in Figure 1A, and the electrodes for contacting the gate, source and drain electrodes have not been shown. Threshold adjustment and wear Through planting The region 71 is located directly below the drain region 22 and the source region 24. The size and shape of the implantation region 71 are clearly defined. The implantation region 71 is calibrated to the gate conductor 23. Please note that the threshold adjustment implantation is usually formed near the surface And wearing '& 铉 y is slightly below the threshold adjustment placement: the position (depth) of the threshold adjustment placement area and the penetration placement area is mainly controlled by the corresponding quality energy of the placement The penetration implantation area is used to prevent the penetration current from flowing between the drain region 22 and the source region 24. The direction of this penetration current is parallel to the channel and cannot be controlled by the channel. The functional relationship between concentration and distance (tangent line Η 〖-Η〗) is shown in Figure 2b. 凊 Note that this figure is intended for 7JT, and is only used to show the known MOSFET (see Figure 1B) and the The basic difference s between the MOSFETs is to define the source region 24 and the electrode region 2 2. Use arsenic to implant D. The concentration of these impurities is approximately 1 * 10Λ {21} / cm ^ ^ The interface to the channel 27 is 29 Steep and well-defined. When using gate holes to form the gate conductor 23 'may " 18-paper ruler Applicable to China National Standards (CNS) 210X297 public p-: Please read the back of ii. Matters needing attention before filling out this page. Binding Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ A7 ^ 09424 _____ 5. Description of Invention (16) — Obtain such a well-defined joint, which will be explained below. Because the gate conductor 23 has a vertical side wall 2 6 ′, the source electrode and the electrode implantation can be introduced into the substrate 31 so that when the electrode / channel or the source / channel junction surface 29 is crossed, the crushing concentration will decrease sharply. According to the present invention, a deep implant 70 (such as a butterfly) is introduced into the substrate through a part of the dielectric stack, and the dielectric stack is used to form a gate hole. Once this gate hole is formed, the threshold adjustment implant and / or penetration implant 71 (such as indium) can be implanted to the area below the channel 27 through this hole. Indium is very suitable because indium ions do not diffuse as quickly and easily as other impurities. In other words, the size and shape of the threshold adjustment implantation area and / or the penetration implantation area 71 remain almost the same even if heat treatment is subsequently required. According to the invention, this is done before the gate conductor is formed in the gate hole. As shown in Fig. 2B, the in-depth implantation 7o (in the case of CMOS is # 布 植), which defines the background, has a concentration of approximately 1 * 10 (16) / cm3. In this example, the concentration of the threshold adjustment planting 71 is about 2 * 10λ {17) / cubic male knife ° rent / idea. These threshold adjustment plants are located directly below the channel 27, that is, the concentration below the channel. A substantial increase. One advantage of this original structure is that its effectiveness is improved. Another advantage is that it effectively prevents penetration without increasing source / drain resistance. The penetrating implant region can be designed to minimize the short-channel effect and the reduction of the barrier caused by the drain ’without affecting the source / drain capacitance. In the following, a more detailed description of the present invention will be provided by a sequence of steps (shown in Figures 3A-3N). It should be noted that these steps do not have to be performed in the order shown and explained = manufacturing method according to the invention Also suitable for forming FETs with very thin gate oxide (5nm) and with sub-lithography-19-this paper size '(Please read the precautions on the back before filling this page} Central Ministry of Binding Printed by the Consumer Cooperative of the Bureau of Staff 409424 V. Description of the Invention (A 7 B7 17 The printed FET of the gate is printed by the Consumer Cooperative of the Standards Bureau of the Ministry of Economic Affairs. In the example described below, it is on the substrate 30. This base is based on the present invention -The FET structure is beginning to be overwhelmed.-The horse-sound inter-oxide layer 35 and the nitride layer 31 are overlaid. For example, the substrate 30 may be a horse silicon substrate. An 8 nm thick silicon dioxide layer may be used as a pad Oxide. The thickness of the upper porosity layer is usually between 5 nanometers and 20 t micrometers. Oxidation can be made by a lambda or furnace treatment. Layer 5 can be obtained by rapid thermal processing (RTP) nitrogen-material layer jl may contain silicon nitride and may have about 9 Thickness of nanometers. The lice compound layer 31 can be produced by using the m. Refined process using a high temperature and low pressure chemical vapor deposition (LPCVD) process. For example, there are other deposition methods for use-including% slurry enhanced chemical vapor deposition method (The pEcvD is similarly 'nitride can be sputtered. Then, the single-layer photoresist j 2 is rotated to the nitride layer 3 j. This photoresist layer is photolithographically. 2 This is then patterned to define the etching. The window 33 is used to perform the subsequent axial engraving step, as shown in FIG. 3B. In addition to using a single layer photoresist, a multilayer photoresist, or any other mask, such as a hard annealing mask, is etched. The shape of W 3 3 is etched The size and size of the shallow trench insulation (s τι) trenches that are subsequently etched are adapted to the lateral dimensions. This STI (also known as field oxide insulation) is commonly used in MOS and CMOS technologies to provide insulation between adjacent transistors. The STI can be replaced by LOCOS (Local Oxidation of Silicon) or multi-buffered LOCOS. As shown in Figure 3C, the photoresist pattern is now transferred to the underlying layered structure by appropriate etching techniques. This step is not critical a S TI Channel 3 4 Depth DSTI It is 100 nm or deeper. When using a suitable insulator to fill it -20- This paper is sized to the Chinese National Standard (CNS) A4 (210X297 male f) nn III ^^^^ 1 ^^^^ 1 ^^^ ^ 1 n1 ^^ ^^^^ 1 ^^^^ 1 p »nr i ^^ pn HI WPJ 3,-=-° (Please read the notes on the back before filling out this page) 409424 A7 B7 V. DESCRIPTION OF THE INVENTION (18) Before the STI channel, it can be thermally grown into a thin oxide layer 46 within the channel 34. This method is particularly suitable if the channel 34 is to be filled with tetraethylnormal silicic acid (TEOS), which is a deposited oxide. The deposited TEOS usually has a surface state 3 on the interface to the silicon substrate 30. This surface state is not desired. In this example, photoresist 32 is removed, a thin thermal oxide 46 is formed and then TEOS is deposited so that all ST I channels 34 are filled to the bottom, as shown in FIG. 3D. TEOS can be deposited using a low pressure chemical vapor deposition (LPCVD) process. For example, many other materials can be used to obtain TEOS, as long as there is sufficient insulation between adjacent transistors (these crystals are not shown in Figures 3A-3N). One advantage of TEOS is that it provides a very good stop layer for any subsequent chemical mechanical polishing (CMP) planarization step. As shown schematically in FIG. 3E, the upper surface of the structure is now planarized by CMP. For example, in this example, CMP removes too much TEOS 36 and stops at the nitride layer 31. Surface 37 above layer 31 is now completely flat. After the CMP is performed, the thickness of the nitride layer 31 is slightly reduced to about 75 nm. The in-depth implantation 70 is now introduced into the matrix, as shown in Figure 3F. In CMOS technology, p-well implantation and n-well implantation are structured so that NMOS and PMOS transistors can be integrated on the same substrate. This example uses sheds as impurities. Shelf ions are implanted through the nitride layer 31. Because this ion implantation is a high-energy process, nitrides have little effect on the penetration depth of the ions. In the traditional CMOS process, the nitride layer -21-this paper size applies the Chinese National Standard (CNS) Λ4 specification (2Ϊ〇 × 297 common trend) ^^ 1 ^^^ 1 ^^^ 1 ^^^ 1 ^ ^^ 1 ^^^ 1 »Taxi-11 n ^ i ^^^ 1-IT -¾ '1 (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Λ7 ------------- Β7 Five 'invention description (Ί9) ~ 疋 is removed before constituting ice into the planting. However, according to the present invention, the nitrogen 2 layer is used to establish a dielectric stack, which will be discussed below. The nitride layer can be completely removed before ion implantation, but this will add additional and unnecessary processing steps. . In a subsequent step (see Fig. 3G), the electricity on the pad oxide layer 35 is completed; by forming an additional layer on the planarized surface 37. In this example, the dielectric stack includes: • a nitride nitride layer 31 (reduced to about 75 nm thick); • a silicon nitride layer 3 g (about 50 nm thick); and •-TEOS layer 39 (approximately 60 nanometers thick). TEOS and nitrides can be deposited using the LpcvD process. For example, materials such as silicon or nitrides and their corresponding oxides are preferred because of existing device technology. Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs ...........- *-..... 1--· ^ II-I _______ H Ding- ° (Please read the back first Note " Please fill in this page again) TE0S is very suitable as the top layer of the dielectric stack, because TEOS can use RIE to precisely etch. TE0s etched using RIE have a smooth surface 3 which can serve as an excellent hard mask for subsequent RIE etches because the photoresist pattern can be transferred to TEOS exactly. However, it should be noted that TEOS is removed when the pad oxide at the bottom of the gate hole is etched, and this will be discussed below with reference to Figures JJ. The dielectric stack can also contain a polymer, or it can contain many polymer layers. Any other dielectric stack can be used. ', To be protected3. This stack can be etched in one way, and gate holes with vertical sidewalls can also be used. Constructed in this way. It is also important that highly selective etchants are available for engraving gate holes, which will be discussed below with reference to Figures 3 (a) and 31 (b). Dielectric stack-and one or more included in the dielectric stack-This paper size applies to Chinese National Standard (CNS) A4 (210X 297 gigabytes) 409424 Printed by A7, Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs (20) Multilayer-should be compatible with existing device technology. The dielectric stack may include only nitride. This nitride-only stack can be etched without damaging the dream and hafnium oxide. In this example, the dielectric stack is formed on a semiconductor structure, which already includes some layers and structural components, such as STI4L0c0s. It should be noted that dielectric stacks can be constructed from any type of semiconductor structure, including simple substrates, pre-treated substrates, a semiconductor device containing other circuits, and so on. The protruding gate post is used herein to explain the gate structure protruding from the semiconductor structure. The post can have any shape and size. In a subsequent step, a photolithography process is used to define the lateral size of the gate hole to be formed. This step is not shown because there are many different ways to do this. Basically, an etched window 40 is provided in the photoresist mask 48 (see Fig. 3), and the size and shape of the etched window is approximately the same as the lateral size and shape of the gate hole to be formed. In the following, the constitution of the gate hole is explained. The gate formation RIE process is used to transfer the etched window 40 provided in the photoresist 48 to the dielectric stack (note that in this example the dielectric stack includes a nitride layer; 31, a nitride layer 38, and a TEOS layer 39). The gate formation RIE process can be optimized to ensure that the various layers of the dielectric stack are properly etched. There are many RJE steps that can be performed, and the RIE steps are all optimized to etch the corresponding layers of the dielectric stack. When the TEOS layer 39 is etched, for example, the selectivity to nitride should be appropriately selected. The selectivity to nitride is 3: 1 or better, which means that TEOS is etched three times faster than nitride. Deposit-23- This paper size applies to China National Standards (CNS) A4 (210X297 mm) mu nm · ^^ —i ------- al ^ i -1, \ = ° (Please read first Note on the back, 'Implementation matters, please fill out this page again.) 409424 A7 B7 V. Description of the invention (21 Many constructions can be conveniently constructed around the dielectric stack. Good structure < E process on κ on vertical sidewall is available. Once the window is etched Having accurately transferred to the TEOS layer 39, a second RIE frame can be implemented. This second frame is designed to have a high selectivity for #oxide 35. 5: 1 or better nitride is 1 whole oxide (select The selectivity is preferably at least 10: I. In this example, the second step of the gate formation RIE process is to design the etched gaseous layers 3 8 and 3 1 'and stop at the pad. The oxide layer 35 is shown in FIG. 3; [. This second RIE step is the last RIE step from a sequence of separately optimized RIE steps. It is important to select the pad oxide 疋 5: 1 or better, because otherwise the whole oxide layer 3 5 may be strongly attacked and its thickness may be reduced. Gate hole 40 The degree of dgate (the depth is approximately equal to the thickness of the dielectric stack Dstack in Figure 3G). The height of the foot gate, including the gate oxide, and both of which are yet to be formed. Between 00 nm and 200 nm 'but can be much higher than 2000 nm. The gate length of future CMOS FETs will be 150 nm and even lower. Such short gates can use this Original process to easily make the width of 3 traditional gate electrodes (protruding from the paper plane) can be between 2 microns and 50 microns. After the gate holes of the dielectric stack have been defined 40, threshold adjustment impurities and / or Penetrate the impurities to the matrix 30, as shown in Figure 3 I. It should be noted that according to the present invention, threshold adjustment impurities or penetration impurities' or threshold adjustment impurities and penetration impurities can be planted through the gate hole 4 0 (Threshold adjustment of the planting area and the penetrating planting area are not shown as two separate areas for the sake of simplicity.) This can be used -24 This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm ) (Please read the note on the back of the note before filling out this page) --- Order! Central Standards Bureau of the Ministry of Economic Affairs | Industrial and Consumer Cooperatives ’Seal 409424 A7 _________—_ B7 V. Description of Invention (22) Implemented in a way that is accurately controlled, because the gate hole 40 only allows impurities to reach directly below the basic product The shape and size of the gate hole 40 thus define the threshold adjustment shape and size of the planting area and the planting area 71. However, it should be noted that due to the lateral and longitudinal diffusion of these planting areas, The border can heal some. Threshold adjustment impurities and penetrating impurities are implanted using an ion implantation process and implanted with boron at a voltage of about 50 kiloelectron volts (ke V), and indium at a voltage of j 50 ke v. The concentration of impurities in the threshold adjustment and penetration of the planting area is generally between 1Moα {17} / cm3 and 1 * 10 eighty {18} / cm3. According to the present invention, the peaks of the Gaussian distribution of the threshold-adjusted implanted region are close to the gate oxide 28 = > The peaks penetrating the implanted region are generally about 0 "micrometers deep. Due to the fact that the threshold adjustment implantation areas and / or penetration implant adjustment areas are formed by implanting impurities through the gate hole 40, such implantation areas can be accurately positioned so that they do not touch the drain region And source region. Printed by ifin l ^ i ^ i tm ^^^^ 1-^^^ 1 ». ^^^ 1 · II ^^^^ 1 I— I 1 (Please read the back first (Please note this page and fill in this page again) Then the residue of the pad oxide 3 5 can be removed from the bottom of the gate hole 40. This can be done by using an H F impregnation. H F is very suitable because it attacks oxides 35 and TEOS 39. HF does not attack the silicon substrate 30. Before removing TEOS 3 9 and pad oxide 3 5 at the bottom of gate hole 40, the photoresist is removed. After TEOS 39 and pad oxide 35 are completely removed, please refer to FIG. ′ To form an accurately defined gate oxide 49, as shown in FIG. 3K. The thickness and quality of the gate oxide 49 are not related to the thickness and quality of the pad oxide layer 35. The gate oxide can also be thicker than the #oxide, if you want to do so. Before forming the gate oxide 49, a sacrificial oxide layer (not shown) can be formed at the bottom of the gate hole 40. This sacrificial oxide layer is then subjected to ___ -25- This paper method is applicable to the Chinese national standard j ^ y.A4 (2) 〇 > < 297Read — 409424 A7 B7 V. Description of the invention (23-Ministry of Economic Affairs) The Central Zhangxin Bureau employee ’s consumer cooperation went to print the family name and the structure was heated. Such a short sequence of steps may cause the gate hole 40 to 300m to be damaged (due to the gate structure RIE and ion implantation) Recoverable. In another example, the RIE process used to form the gate hole can be designed as a dielectric stack and the pad oxide layer 35 is etched. In this case, the second RIE etch process must be selective for silicon. Suitable, because otherwise the gate hole 40 & silicon 30 will be etched away. Once the silicon 30 is exposed to the bottom of the gate hole 40, the gate oxide layer 49 may be formed by oxidation, as described above. Before the gate oxide layer 49 is formed, the threshold adjustment impurities are implanted. Then, a sacrificial oxide layer can be grown. As described above, the sacrificial oxide layer can be about 2 nm thick. As shown in FIG. 3K Shows that polysilicon 41. is now deposited in the gate hole 40 and located in the dielectric Overlying the uppermost layer 38. It is important to ensure that the polysilicon 41 completely fills the gate hole 40. The polysilicon can be deposited by LPCVD (e.g. at about 65 ° C). As mentioned earlier, it can be deposited Amorphous silicon replaces polysilicon. Amorphous silicon can then be converted into polysilicon at a later time. Polyfragmentation can be free of impurities or dopants. Impurities can be introduced into polysilicon after polymerization, k. This original process One advantage is that the polysilicon gate does not have to be doped with impurities when the source and drain regions are implanted. ^ Polysilicon gates can be silicified (polymerized) in one of the subsequent manufacturing steps, and-seal it Electricity is deposited to protect the gate during subsequent processing, if it is considered to be Thai. Θ ^ ® As mentioned earlier, 'any metal material suitable as a gate conductor can be filled " to gate hole 4 0 ^ The present invention is not limited to polysilicon. Please read the notice on the back and fill it in.> 5 Installed on this page Oxygen Dielectric Order-26 This paper size applies to China National Standard (CNS) A4 (210X297 cm) ) 409424 A7 —— ______B7 V. Description of the invention (24) ~~ After the material of the gate conductor 41, a planarization step can be performed. CMP is suitable to implement planarization. After planarization, the uppermost layer 38 of the dielectric stack is exposed, as shown in Figure 3l. Last but not least The dielectric stack must be removed. The nitride layers 38 and 31 are removed using hot phosphoric acid. After the dielectric stack is completely removed, a protruding gate 4 i with vertical sidewalls 42 is exposed, as shown by circle 3 M. Now This process can be continued using standard CMOs technology, such as the book by R'A. Colcla ster " micr0 eiecir〇nics pr〇cessing, has been based on device design " Chapter 10, pages 266 to 269 This book was published by John Wiley & Sons in 1980. In the slave step, the source region 43 and the drain region 44 can be defined by implanting appropriate I impurities, if not done earlier, as shown in Figure 3N. The channel 45 (below the gate 41 and between the pole 44 and the source 43) is thus defined. The channel length is approximately the same as the gate length, because the source / channel and; and pole / channel interfaces are very steep and change abruptly (well-defined), and the overlap is minimised, as discussed earlier. Employees of the Central Bureau of Standards of the Ministry of Economic Affairs can eliminate the source and drain junctions of the cooperative's printed and expanded government. They can be formed by spreading out from a polysilicon layer to replace the standard source and source regions obtained by implantation. The polysilicon layer is formed in a region to be doped. To form the FET, an electrode must be provided. Suitable electrodes are made of a conductive material 'especially a metal, such as gold, aluminum, molybdenum, tantalum, copper, copper' or ITO (indium oxide), and the conductive material is by evaporation and etching, or Other techniques to deposit D In addition, it can now constitute a metallized ___________ 27 'paper ^^ applicable to the country) A4 specifications (21〇χ ^ 7 公 楚 _) A7 402424 5. Description of the invention (25) Connect adjacent FETs. -I 1 ----— ^^ 1-! 1 ^: I —:--IJ ^ i I ^ 1 »* τ (please read the notes on the back first before filling out this page) A traditional CMOS will be provided below A brief summary of the process. The traditional process received a summary explanation to highlight the essential differences between the original process and the traditional process. After forming ST or LOCOS insulation, the nitride layer and pad oxide layer are removed. It is then usually grown into a sacrificial oxide layer. Now, in-depth implantation of wells p and / or n is performed, and then the threshold-adjusted implantation process is performed. As shown in Fig. 1B, the 'ρ well and the η well are deeply implanted and the threshold adjustment implantation is extended to the entire wafer. After ion implantation, the sacrificial oxide is removed and grows into a gate oxide layer. In a subsequent step, a polysilicon layer is deposited. This polysilicon layer is then defined by photolithography and RiE etching. The result of this process is a MOSFET 10 with a slanted ramp 16, as shown in Figure 1A. The foregoing examples and other examples described above can be modified in various ways' as explained in summary below. The n + -type impurity region may be replaced with a p + -type impurity region, for example. The size and shape of the impurity region can be changed. The substrate can be a silicon substrate doped with ρ-type impurities or η-type impurities, or a silicon insulator (SOI) substrate, but these are just some possible modifications. In-depth well implantation can be used to define the P-type impurity region in the η-type impurity-doped substrate β. The Central Bureau of Standards of the Ministry of Economic Affairs's consumer cooperation du printed within 'for example. This allows n-type FETs (also known as n-channel FETs or NMOS) to be formed in the p-type impurity region, while p-type FETs (also known as p-channel or PMOS) can be directly formed in the matrix doped with n-type impurities. In CMOS technology, 'P-well or η-well diffusion is performed before forming the source and drain regions. This original method is very suitable for constructing a transistor with a ground plane. This may be -28- This paper · size applies to Chinese National Standard (CNS) A4 specification (2 丨 0 × 297 gong) 409424 A7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (26 by guiding high concentration Impurities are achieved through the gate hole to a high-concentration impurity-doped substrate (large- • force 1 10Λ {19} / cm). For the device area, low-concentration epitaxial growth can be used (approximately 1 * 1.8).丨 丨 5 丨 / cubic centimeter). Due to the fact that the implantation of impurities is performed through the gate hole, the impurities can be accurately localized and calibrated under the gate conductor to be formed. It is assumed that the concentration of the impurity is high enough (about 1 * 1〇α {19} / cubic centimeter), the performance of these impurities is almost like a metal ground plane. NMOS and PM0S FETs can be formed by this original process ^ MOSFETs with different channel types and structures can be made on the same Within the substrate. The process according to the present invention also has great potential for making devices below 0.05 microns. Please note that devices below 0.1 microns are devices with a gate length L < 01 microns. The width and length of the gate hole I can be determined by In the planting Before the threshold adjustment and / or the penetration of impurities, a sidewall spacer is formed to reduce it. Alternatively, before the threshold adjustment impurities are implanted, the sidewall spacers are first formed, and then the spacer layers are removed, and the impurities are penetrated before the implantation. Before forming the second cell, the size and shape of the corresponding implanted area can be controlled more accurately. The FET according to the present invention can be used in many different types of circuits, such as high-policy logic, low-power logic, or high-density memory devices.丨 The medium package is high and the multi-billion-bit group M. These originality are easy to be combined with other .. and these other components are examples of fasting, resistors, two ... 1 memory cells , Etc. 'Because the size of m of the present invention is very small 2: manufacturing, they are also suitable for connecting organic displays or liquid crystal displays --------------------- order (please read first Note on the back. Please fill in this page if you have any questions) -29 ·

409424 Α7 Β7 4-Printed by the Consumers' Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China 5. Description of the invention (27 In another aspect, the structure of the second FET 120 according to the present invention is shown in the figure. Semiconductor means a semiconductor doped with a high concentration of impurities. These semiconductors usually have an impurity concentration of at least 10Λ {18} to 10Λ {22} / cm3. When the word MOSFET is used herein, it means Any kind of MOSFET field-effect transistor, including CMOS FET, Wake Up, PMOS, etc. At the same time, it means that the transistor will be covered in the place where no oxide acts as the gate pillar and the insulating layer between the channels. In addition to the traditional Any kind of insulating layer other than oxides, such as nitride layers, can be used. The following description will focus on the polysilicon gate. 3 It should be noted that except for polysilicon, any material suitable as a gate conductor can be used. Polysilicon can be replaced by tungsten, for example. Similarly, a layered structure of polysilicon and silicide, or the like, can be used as a gate. In addition to polysilicon, amorphous silicon can be filled in the gate hole And later on Note 3 This amorphous silicon can then be converted into polysilicon by subsequent heat treatment. 3 The FET 120 according to the present invention is shown in Figure 4 => FET 20 is formed on a semiconductor substrate 121. For example, the substrate can be silicon Substrate, for example. In this example, ^ and polar region U2 and source region 124 are defined by mass. Elements commonly used as n-type impurities include phosphorus, arsenic, and bomb. To define P-type source Boron, indium, and gallium can be used in the region and the drain region. The polysilicon gate 123 is located on the thin silicon oxide (Si0—⑺) gate oxide ⑯128. Please note that the surface of the structure surrounding the money structure is a pad of oxide. Covered by the rest, the oxide layer is usually defined before the shallow insulation channel is defined (not shown in Figure 4) ^ -30- (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 409424 A? 5. Description of Invention (28) to deposit. As shown in Figure 1A, the electrodes used to contact the gate, source, and drain electrodes have not yet been shown. It should be seen that the side wall 126 of the poly gate 123 is a vertical source / channel and drain / channel junction surface 129 (also referred to as a source / channel and; and a pole / channel interface) is clearly defined and It is a sudden change because there are no inclined gate walls' and when the source and drain regions are planted, these inclined gate walls can allow final impurities to enter the area below the gate edge. The interface 129 is almost vertical, and the effective channel length LGeff is therefore mainly defined by the length L0 of the gate post 126, because there is minimal overlap. Going further-note that the gate length LG is shorter than what can be achieved using conventional photolithography techniques. Such a gate is referred to herein as a sublithographic gate. A FET with a sublithographic gate has a gate conductor < transistor, and at least one lateral dimension (gate length or gate width) of the gate conductor is shorter than the minimum feature size that can be achieved by conventional photolithography. In other words, the gate length and / or gate width is 50 nm or less. According to the present invention, the gate hole is formed by transferring a mask window to a dielectric stack. A side wall layer is then formed and the side wall layer is removed from the horizontal surface so that the inverted wall spacer layer remains within the gate hole. The width of the gate hole minus the thickness of the sidewall spacer defines the length L (} and width of the gate post to be constructed. The verticality of the gate sidewall provides the least overlap, and therefore reduces the source-drain resistance and the overlap capacitance. Again, a more detailed description will be provided with reference to the sequence of steps (shown in Figures 5-8-5L) according to the present invention. It should be noted that these steps do not-must be performed in the order shown and explained. According to this The manufacturing method of the invention is not suitable for constituting a FET. In the following example, the structure of the anode according to the invention starts at 4-(please read the note on the back ^-matters before filling out this page).

409424 A7 B7 V. Description of the invention (29 Matrix 13. This matrix is covered by a rhenium oxide layer and a nitride layer 131. For example, 'matrix 30 may be a broken matrix. A 10 nm thick dream dioxide layer 135 may be It is a rhenium oxide. The thickness of the rhenium oxide layer is usually between 5 nanometers and 20 nanometers. 3 The oxide layer 135 can be made by rapid tertiary process (RTP) or furnace process. The nitride layer 131 can be Contains nitrogen cutting and may have a thickness of about ⑽ nanometers. The nitride layer 131 may be made by using a high temperature and low pressure chemical vapor deposition (LPCVD) process, for example, there are other deposition methods available, including electro violet strengthening Chemical vapor deposition (LPCVD). Similarly, the nitride can be subjected to low-level emission. Then, a single layer of photoresist is rotated to the nitride layer 131. By conventional photolithography, the photoresist layer 132 is then patterned to define The money engraved window 133 is used to perform the following I engraving step, as shown in Figure 5B. In addition to using a single layer photoresist, a multilayer photoresist or any other mask, such as the shape and size of a hard annealing mask f 133 Definition is then subject to The horizontal dimension of the engraved shallow trench insulation (sTI) structure. This type of STI (also known as field oxide insulation) is commonly used in M0S and CM0S technologies to provide printing to employees' cooperatives of the Central Standards Bureau of the Ministry of Economics of neighboring transistors. Insulation can be replaced by LOCOS (Local Oxidation of Silicon) or multi-buffered LOCOS instead of s TI. As shown in Figure 5C, 'the photoresist pattern is now transferred to the underlying layered structure by appropriate sleeve engraving technology. This step is not critical. The depth DSTi of the STI channel 134 can be 100 nm or deeper. Before the STI channel is filled with a suitable insulator, it can be thermally grown into a thin oxide layer. 46 Within. If the gully 1 34 is filled with tetraethyl normal silicic acid (TE0s), the paper size applies the Chinese National Standard (CNS) A4 specification (2! Ox2i > 7 Gongchu) Central Bureau of Standards, Ministry of Economic Affairs Printed by the Employee Consumption Cooperative's Society 409424 V. Description of the Invention (30) This method is particularly suitable, and TEOS is a deposited oxide. The deposited TEOS usually has a surface state on the interface to the silicon substrate 130 .This surface state is not desired. In this example, 'the photoresist 132 is removed—thin thermal oxide I " is formed and then TEOS is deposited so that all STI channels 134 fill the bottom' as shown in FIG. 5D. TEOS can use low | chemical vapor deposition ( LPCVD) process, for example, many other materials can be used to replace TEOS, as long as there is sufficient insulation between adjacent transistors (the transistor is not shown in Figures 5A-5L). One of the advantages of TEOS is that it provides a A very good barrier layer gives any subsequent chemical mechanical polishing (CMP) planarization step. As shown schematically in Figure 5E, the upper surface of the structure is now utilized

To flatten, for example. In this example, the CMP removes too much TEOS 136 and stops at the nitride layer 131. The surface ι37 above layer 131 is now completely flat. After the CMP is performed, the thickness of the nitride layer 131 is slightly reduced to about 75 nm. In the step-by-step field (see FIG. 5F), the dielectric stack on the plutonium oxide layer us is completed by forming an additional layer on the planarized surface 137. In this example, the dielectric stack includes: • a silicon nitride layer 131 (reduced to about 75 nanometers thick); • a silicon nitride layer 1S8 (about 50 μm thick); and a TEOS Layer 139 (approximately 60 nm thick). TEOS and nitrides can be deposited using LPCVD processes, for example. For compatibility with existing <device technology, it is best to use, for example, tritium or gasification nn I -11----II &gt; m D ^ i ^^^ 1----— I— V J. (Please read the notes on the back before filling in this page) -33-

409424 a7

V. Description of the invention (31) The employees of the Central Standards Bureau of the Ministry of Economic Affairs consume printed materials and their corresponding oxide materials. TEOS is very suitable as the top layer of the dielectric stack, because te0s can be accurately etched using RIE. TE0s etched by RIE have a smooth surface. It can serve as an excellent hard mask for subsequent RIE etching, as the photoresist pattern can be exactly transferred to TEOS. However, it should be noted that TEOS is removed when the pad oxide at the bottom of the gate hole is etched, which will be discussed below with reference to FIG. 511. The dielectric stack may also include a polymer, or it may include many polymer layers. Any other dielectric stack can be used, as long as it is ensured that the stack can be etched in one way, and the gate holes with vertical sidewalls can be constructed in this way. It is also important that highly selective etchants are available for etching the gate holes, which will be described below with reference to Figs. 5G and 5H. When selecting the uppermost layer of the dielectric stack, the following facts should also be taken into account: the sidewall layer constituting a subsequent step can be easily removed from the uppermost horizontal surface. In addition, the dielectric stack-and one or more layers included in the dielectric stack-should be compatible with existing device technology. The dielectric stack may include only nitride. This nitride-only stack can be etched without damaging the silicon and pad oxide. In this example, the 'dielectric stack is formed on a semiconductor structure, which already includes some layers and structural components, such as S τ I or LOCOS channels. It should be noted that the dielectric stack can be constructed of any kind of semiconductor structure, including a simple substrate, a pre-treated substrate, a semiconductor device containing other circuits, and so on. The protruding gate post is used herein to explain the gate structure protruding from the semiconductor structure. The column can have any shape and size, as long as at least two of these side walls ___. 34_ This paper size is applicable to Chinese National Standards (CNS) / \ 4 square grid (210X297 mm) (Please read the precautions on the back before filling (This page]). Τ ''-° Printed by the Industrial and Commercial Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 409424; 5. Description of the invention (32) The side wall is vertical, that is, perpendicular to the semiconductor structure. In a subsequent step, A photolithography process is used to define the lateral size of the question hole 140 to be formed. Reading the following description should make it clear that the actual size of the gate post M1 to be formed within the gap hole 40 is smaller than the gate hole size. This step is not Shown because there are many different ways to define the lateral size and shape of the gate hole 140. Basically, a photomask 140 is provided in the photoresist mask 148 (see FIG. 5G), and the size of the etched window The shape and shape are approximately the same as the lateral size and shape of the gate hole 140. Please note that the length of the etching window ι40 defines the length of the gate hole 140. In the following, the gate hole structure is explained. The gate formation RIE process is used to transfer For photoresist! 48 etch window 140 to dielectric stack (please note that in this example this dielectric stack contains nitride layer 131, nitride layer 138 'and TE0s layer 139). The gate formation Rm process can be optimally To ensure that the various layers of the dielectric stack are properly etched. Many RIE steps can be performed and each of these RIE steps is optimized to etch the corresponding layers of the dielectric stack. When etching the TEOS layer 139, for example, for nitrogen The selectivity of the compound should be appropriately selected. 3 The selectivity to nitride is 3: 1 or better. This means that TEOS is etched at twice the rate of nitride. There are many that can be conveniently used throughout the dielectric stack. A perfectly constructed vertical side E process is available. Once the engraved window 140 has been accurately transferred to the TEOS layer 139, a second RiE step can be implemented. This second Rm step is &amp; High selectivity. Selectivity of 5: 1 or better nitriding to phase oxygen over whole oxide is suitable. Selectivity is preferably at least 10: 1. _____ -35- Read the notes on the back and fill in (This page) 袈-丁,-11 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 409424; Ί15. Description of the Invention (33) In this example, the second step of the gate formation RIE process is to be designed as a monolithic dielectric The stacked nitride layers 138 and 31 are stopped at the pad oxide layer 135 'as shown in Fig. 5G. This second RIE step is the final step of a sequence of RIE steps that are optimized separately. It is important that the selectivity for the replacement oxide is 5: 1 or better, because otherwise the pad oxide layer 135 may be strongly attacked and its thickness may be reduced. After the gate hole 140 is formed, a portion of the dielectric stack may be removed (described below), or processing may be continued without removing any of these layers. In this example, the TEOS layer 1 3 9 is It is removed before continuing processing. In this case, the depth of the gate hole D40 is approximately equal to the combined thickness dstack of layers 131 and 138 (see Figures 5H and 5F). The depth Dgate defines the height of the gate post 141, including the gate. Oxide, and both are yet to be formed. The pillars that act as gates are usually higher than 100 nanometers, and especially between 100 nanometers and 200 nanometers. The gate length of future CMOS FETs will be 150 nm or even lower. Such short gates (also called sub-lithographic gates; 150 nm or less;) can be easily fabricated using the original process. The width of the conventional interfacial electrode (protruding from the surface of the paper) can be between 2 microns and 50 microns. At the same time the gate width can be sub-lithographic, if desired. After the gate hole 140 is defined by RIE #etching, a thin side wall layer 160 is now deposited. As shown in FIG. 5I, it is better not to remove the pad oxide 135 before the sidewall layer 60 is deposited (see FIG. 5H). The layer Ⅵ can be a nitride layer, and the nitride layer closely matches the vertical sidewall of the gate hole. The thickness of such a nitride layer can be accurately controlled. The next etching step is now performed to remove the sidewall layer 16 () from the horizontal surface. -36- The paper ^ dimensions are applicable to Chinese National Standard (CNS) A4 specifications-: (Read the notes on the back of the poem before filling out this page) Pack -π A 7 B7 409424 5. Description of the invention (34) A cover type RIE can be used (Or another etching process). Because the thickness of the horizontal portion of the sidewall layer 160 is relatively thin, compared to the thickness of the vertical portion (the vertical portion is the portion covering the sidewall of the gate hole 140), these horizontal portions can be vertical without attacking too much. Partially removed. When this etching step is completed, the sidewall spacers 161 having a clearly defined thickness will remain, as shown in FIG. 5J. The sidewall spacers 161 reduce the length of the gate hole 140. The length of the gate hole minus twice the thickness of the sidewall layer 160 defines the length L g of the gate 141 to be formed.

The residue of the oxide 13 5 can now be removed from the bottom of the gate hole 140. This can be done by using an HF dip. HF does not attack the silicon substrate 130. Before removing TEOS 139 and pad oxide 135 at the bottom of the gate hole 140, the photoresist is removed. An accurately defined gate oxide 149 can now be formed. As shown in FIG. 5J, the thickness and quality of the gate oxide 149 are not related to the thickness and quality of the pad oxide layer Π5. The gate oxide 149 may also be thicker than the pad oxide. If desired, C. Before forming the gate oxide 149, a sacrificial oxide layer (not shown) may be formed on the bottom of the gate hole 140. The sacrificial oxide layer is then etched away and the structure is heated. This short sequence of steps allows the possible damage to the silicon 130 at the bottom of the gate hole (caused by the gate hole forming RIE) to be restored. In another example, the RIE process used to construct the gate hole can be designed to not only dielectric stack Moreover, the pad oxide layers 35 are all etched at the same time. In other words, the RIE process stops at the silicon substrate 130. In this case, the selectivity of the second RIE etching process for silicon must be appropriate, otherwise the gate hole -37- This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X2H mm) ----- ---- Equipment-(Please read the note on the back before filling this page) *-° Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 35) A bottom of 140 (send money will receive money.-Once broken 13G is exposed to the gate hole 140, it can grow into a sacrificial oxide layer, as described previously. Here is more Υ λ is the silicon The RIE damage is the most severe. The sacrificial oxide layer may be about 2 nm thick. Next, the nitride sidewall layer is formed and configured so that the sidewall spacer 161 remains on the vertical surface of the free hole. At this step After being exposed, the sacrificial oxide layer is removed (money engraved) and is formed by oxidation-the gate oxide layer 149, as described above. Before the oxide layer 149 is formed, the structure can be removed by HF immersion, For example, as shown in Figure 5K, polysilicon 141 is now deposited on the gate The holes 1505 are located above the uppermost layer 138 of the dielectric shell. It is important to ensure that the polysilicon 141 completely fills the gate hole 140. Polysilicon can be deposited by LpcVD (e.g. at about 65 ° C) As mentioned earlier, amorphous silicon can be deposited instead of polysilicon. Amorphous silicon can then be converted to polysilicon at a later time. The bite can be free of impurities or dopants. Impurities can be during the deposition of polysilicon, Or after 'introduction to polysilicon. One of the advantages of this original process is that the polysilicon gate does not have to be doped with impurities when the source and drain regions are implanted. Polysilicon gates can be used in one of the subsequent manufacturing steps. Subject to silicification (polymerization), and a cover dielectric is deposited to protect the gate during subsequent processing, if deemed appropriate. As mentioned earlier, any material suitable as a gate conductor can be &quot; filled &quot; To the gate hole 140. The present invention is not limited to polysilicon gates. After the material 141 serving as the gate conductor is deposited, a planarization step may be performed. The CMP process is well-suited to flatten the robe. 38- This paper is in standard size National Standard (CNS) A4 specification (210X297 public trend) (Please read the note on the back-t · Matters before filling out this page) r Ding printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 彡 09424 a? ----- ------ B7 V. Description of the Invention (36) The uppermost layer 138 of the mass stack is exposed, as shown in Figure 5L. Finally, the most important thing is that the dielectric stack must be removed. In this example, All dielectric stacks are removed. The nitride layers 1 3 and 1 ^ 1 are removed using hot phosphoric acid. If the sidewall spacers are the same; the materials of the dielectric stack are the sidewall spacers. 61 is removed with the dielectric stack. If the sidewall spacer 161 and the dielectric stack contain different materials', they can be removed separately. After the dielectric stack and the sidewall spacers 161 are completely removed, a protruding gate 141 having a vertical sidewall 142 is exposed, as shown in FIG. 5M. This process can now be continued using a standard CMOS technology, such as the book by RA Colcla ster "micro electronics processing and device design" Chapter 10, pages 266-269, and this book is by John Wiley & Sons was released in 1980. In the subsequent steps, the 'source region 143 and the drain region 144 can be defined by implanting appropriate impurities, if not done earlier, as shown in Fig. 5n. Channel I 4 5 (below gate 14 1 and between drain 1 4 4 and source 1 4 3) is therefore defined ^ The channel length is approximately the same as the gate length because the source / channel and drain / channel The interface is steep and abruptly changed (well-defined), and overlap is minimized, as discussed earlier. The gate length LG can be shorter than the length that can be defined by the traditional process. The gate length can be formed by the steps of the original sequence described above. The diffusion source-drain junction can be formed by a Polysilicon or dielectric layer (such as BSG, borosilicate glass) is diffused to replace the standard source and source region obtained by implantation, and the polysilicon layer is composed of -39 to be doped. -This paper size applies Chinese national standard CNS) A4 size (2Gx 297 male Chu Ί ~~ '~~ ^^ 1 ^^^ 1 ^^ — ^ 1 I in ^^^ 1 I.-I- I n ^ — VJ --11 (Please read the notes on the back before filling out this page) 409424 Λ 7 Β7 V. Description of the Invention (37) Area. To complete the FET, an electrode must be provided. The appropriate electrode is made of a conductive material, In particular, metals such as gold, metal, metal, aluminum, copper, or ITO (Indium Easy Oxide) are made, and the conductive material is deposited by evaporation and etching, or other techniques. In addition, It is now possible to form a metallization pattern to connect adjacent FETs. The foregoing examples and other examples described above can be used in various ways It is modified as explained below. The η + -type impurity region can be replaced by a p + -type impurity region, for example, the size and shape of the impurity region can be changed. The matrix can be a silicon matrix doped with a p-type impurity or an n-type impurity, or Silicon Insulator (SOI) substrate, and this is just some possible modifications. Well placement can be used to define the p-type impurity region within the n-type impurity-doped substrate, for example. This allows the formation of n-type FETs (also known as n-channel FETs or NM0S) is in the p-type impurity region, and the p-type FET (also known as the p-channel FET or PM0S) can be directly formed in the matrix of the n-type impurity. In CMOS technology, the diffusion of the p-well or the n-well is a source friend. The drain region was previously implemented = NMOS and PMOS FETs can be constructed using this original process. MOSFETs with different channel types and structures can be fabricated within the same substrate. A wafer can also be manufactured, some of which have a photolithography gate and Other transistors have longer gates. It is possible to remove only a portion of the dielectric stack, instead of removing the entire dielectric stack, to obtain the protruding gate 14 1 as shown in FIG. 5M. The process according to the invention has a great Force can be used to make devices below 0,5 microns. Please note that devices below 0.1 microns are gate length L &lt; -40 from 0.1 microns-This paper size applies to China National Standard (CMS) A4 specifications (210X297mmt) I nn 1--*-----n 1 ·----Jl ^ i \ -s (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409424_b 」__ 5 2. Description of the invention (38) device. This original process is very suitable for manufacturing high-density multi-gigabit DRAM. The FET according to the present invention can be used in many different kinds of circuits, such as high-efficiency logic, low-power logic, or high-density memory devices, including high-density gigabit DRAMs, as mentioned earlier. These original FETs can be easily combined with other components, such as capacitors, resistors, diodes, memory cells, and so on. Because the FETs of the present invention are small in size and easy to manufacture, they are also suitable for connection to organic displays or liquid crystal displays (LCDs). On the other hand, the structure of another FET 2 20 according to the present invention is shown in FIG. 6 In the following description, a semiconductor doped with n + or p + impurities means a semiconductor doped with a high concentration of impurities. These semiconductors typically have an impurity concentration of at least 10a {18} to 10A {22} / cm3. When the word MOSFET is used in this article, it means any kind of MOSFET field effect transistor, including CMOS FET, NM0S, PMOS, and so on. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China 11 (Please read the note on the back and fill in this page before proceeding.) The following description will focus on polysilicon gates. It should be noted that with the exception of polysilicon, any material suitable for use as a gate conductor can be used. Polysilicon can be replaced by tungsten, for example. Similarly, a layered structure of the capture and desertification objects, or the like, can be used as a gate. In addition to polysilicon, amorphous silicon can be "filled in" the gate hole, which will be explained later. This amorphous silicon can then be converted to polysilicon by subsequent heat treatment. -41-This paper is for China National Standard (CNS) A4 specification (2 丨 0X 297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409424 A7 _. B7 V. Description of the invention (39) ~ According to the invention (FET 220 is shown in Figure 6. FET 220 12 is formed on the semiconductor substrate 221. For example, this substrate may be a hacking substrate, for example. In this example, the 'drain region 222 and the source region 224 are defined by η + · quality. It is very suitable for η type The impurity elements are phosphorus, arsenic, and antimony. To define the P-type source and drain regions, boron, indium, and gallium can be used. Polysilicon gate 223 is located in the thin silicon dioxide (SiO_ {2}) gate oxide 228 Note that the surfaces surrounding the gate structure are covered by the rest of a pad oxide layer, and the pad oxide layer is usually deposited before defining a shallow insulation channel (not shown in Figure 6). As shown in the figure As shown in 1 A, the electrodes used to contact the gate, source and drain are not affected. It should be seen that the side wall 226 of the polysilicon gate 223 is vertical. The source / channel and drain / channel interface 229 (also referred to as the source / channel and non-electrode / channel interface) is clearly defined and is Suddenly changed because there are no slanted gate sidewalls' and these sloped gate sidewalls allow impurities to enter the area below the gate edge when the source and non-polar regions are implanted. The interface 229 is almost vertical. The effective channel length is therefore mainly By the length of the gate post 226 to define the foot 'because there is minimal overlap. In other words, the size and shape of the gate mask window defines the channel length' because this mask window is transferred to the dielectric stack, where this mask window defines the gate The length and width of the pillar. The gate-side perpendicularity provides the least overlap, and therefore reduces the source-drain resistance and the overlap capacitance. Another advantage of this original structure is that the thickness of SiO_ {2} pad oxide 225 is between The source region 224 and the drain region 222 are uniform, that is, the thickness of the pad oxide does not change throughout the wafer. In addition, the composition of the thin gate oxide 228 may be independent of the hafnium oxide layer 225 And will not be polysilicon Exposed by the RIE process, and if using traditional MOS manufacturing methods, gate oxidation -42- This paper size is applicable to the Chinese family standard (CMS) A4 specification (210X297 mm) (Please read the notes and precautions on the back first (Fill in this page) Binding 409424 A7 __________B7 V. Description of the Invention (4〇) Product 228 will be exposed by the polysilicon RIE process. The following steps will be provided with reference to a sequence according to the present invention (shown in Figure 7 and 7L). It should be noted in more detail that it should be noted that these steps are not necessarily performed in the order shown and explained. The manufacturing method according to the present invention is particularly suitable for forming FETs having very thin gate oxides (5 nm). In the exemplary towel described below, the construction of a FET according to the present invention begins with a substrate 230. This substrate is covered by the Lu oxide layer 235 and the nitride layer 231. For example, the 'matrix 230 may be a silicon matrix. 8 nm thick silicon dioxide layer 23 :) can be used as pad oxide 3 The thickness of the pad oxide layer is usually between 5 nm and 20 nm. The oxide layer 235 can be formed by rapid thermal processing (RTP) or furnace processing. The nitride layer 231 may include silicon nitride and may have a thickness of about 90 nm. The nitride layer 231 can be formed by using a high temperature and low pressure chemical vapor deposition (LPCVD) process, for example. Other deposition methods are available, including plasma enhanced chemical vapor deposition (Lpc VD). Likewise, nitrides can be subjected to sputtering. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ~ ΐ 衣 ----- ~ lir (Please read the precautions on the back before filling this page) Then, the single-layer photoresist 232 is rotated to the nitride layer 231. This photoresist layer 232 is then patterned by a conventional photolithography method to define an etching window 233 and then perform the remaining steps of the tile, as shown in FIG. 7B. In addition to using a single layer of photoresist, a multilayer photoresist or any other mask, such as a hard tempered mask. The shape and size of the etch window 233 define the lateral dimensions of the shallow trench insulation (STI) structure track which is then etched. This type of s τ (also called field oxide insulation) is commonly used in MOS and CMOS technologies to provide insulation between adjacent transistors. Can use LOCOS (Zhen local oxidation) or multi-buffer type -43- This paper size is applicable to Chinese National Standard (CNS) A4 format (210X 297 public trend) 409424 A7 B? Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 'Explanation (41) LOCOS to replace STI. As shown in Figure 7C, the photoresist pattern is now transferred to the underlying layered structure by appropriate etching techniques. This step is not critical. The depth Dsti of the STI. Channel 234 may be 100 nm or deeper. Before using a suitable insulator to fill the STI channel, a thin oxide layer 246 can be thermally grown within the channel 234. This method is especially suitable if the channel 234 is filled with TEOS, and TEOS is a deposited oxide. The deposited TE0S usually has a surface on the interface to the silicon substrate 230. status. This surface state is not desirable. In this example, the photoresist 232 is removed, a thin thermal oxide 246 is formed and then TEOS is deposited so that all the STI channels 234 are filled to the bottom, as shown in Figure 7D. TEOS can be deposited using a low pressure chemical vapor deposition (LPCVD) process, for example. Many other materials can be used to replace TEOS 'as long as there is sufficient insulation between adjacent transistors (these transistors are not shown in Figures 7A-7L). One advantage of TEOS is that it provides a very good stop layer for any subsequent chemical mechanical polishing (CMP) planarization step. As shown schematically in Figure 7E, the upper surface of the structure is now using CMP

To flatten 'for example. In this example, CMP removes too much tOS 2 j 6 and stops at the nitride layer 23 丨. The upper surface of layer 2S is now completely flat. After the CMP is performed, the thickness of the nitride layer 231 is slightly reduced to about 75 nm. In a subsequent step (see FIG. 7F), the dielectric stack over the pad oxide layer 235 is completed by forming an additional layer on the planarized surface 237. -44 -»--I--— ^ 1-1 * ^------ I TJ«, -mouth (please read the notes on the back before filling out this page) 5 409424 A7 B7 、 Description of the invention (42 ) Printed by a member of the Central Standards Bureau of the Ministry of Economic Affairs and a Consumer Cooperative. In this example, the dielectric stack contains: • —silicon nitride nitride layer 23 1 (reduced to approximately 75 nm thick); • —silicon nitride nitride Layer 238 (approximately 50 nanometers thick) · 'and • — TEOS layer 23 9 (approximately 60 nanometers thick). TEOS and nitrides can be deposited using LPCVD processes, for example. For compatibility with existing device technologies It is best to use, for example, silicon or nitride and their corresponding oxide materials. TEOS is very suitable as the top layer of the dielectric stack, because te0s can be accurately etched by RIE. TE0s are etched by RI £. Has a smooth surface. It can be used as an excellent hard mask for subsequent RIE etching because of photoresist The sample can be transferred to TEOS exactly. However, it should be noted that TEOS will be removed when the pad oxide at the bottom of the hole is etched, and this will be discussed below with reference to FIG. 7H. The dielectric stack can also contain polymer, or It can contain many polymer layers. Any other dielectric stack can be used, as long as the stack can be etched in one way, and gate holes with vertical sidewalls can be constructed in this way. Highly selective etchants are available It is also important to etch the gate holes, which will be described below with reference to Figures 7G and 7H. The dielectric stack-and one or more layers included in the dielectric stack-should be compatible with existing device technologies. Contains only nitride, as discussed with reference to Figure 9. This nitride-only stack can be etched without damaging the silicon and pad oxide. In this example, the 'dielectric stack is formed on a semiconductor structure, and the The semiconductor structure already contains some layers and structural components, such as S TI or please read the back note first

I Binding -45- This paper size applies to Chinese National Standard (CNS) A4 (210X 297) 40942 ^ A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (43) LOCOS channel. It should be noted that the dielectric stack can be constructed of any kind of semiconductor structure, including simple substrates, pre-treated substrates, ~ semiconductor devices containing other circuits, and so on. The protruding gate post is used herein to explain the gate structure protruding from the semiconductor structure. The pillar can have any shape and size, as long as the sidewalls are vertical, that is, perpendicular to the semiconductor structurea. In a subsequent step, a photolithography process is used to define the size of the gate pillar to be formed. (Closed length ^ degree LGATE and gate width Lwidth) and shape. This step is not shown because there are many different ways to define the lateral size and shape of the gate post. Basically, in the photoresist mask 248, an etched window 240 is provided. (See Fig. 7G), and the size and shape of the etching window are approximately the same as the lateral size and shape of the gate post to be formed. Please note that the length of the etching window 24o is the length of the gate hole, and the length of the gate hole then finally defines the gate length Lgate. This gate length LGATE then determines the effective channel length. In the following, the constitution of the gate hole is explained. Gate structure] ^ ΙΕ process is used to transfer the etching window 240 provided in the photoresist 248 to the dielectric stack (please note that in this example, the dielectric stack includes a nitride layer 23 1, a nitride layer 238, and a TE0S layer 239) . The gate formation RIE process can be optimized to ensure that the various layers of the dielectric stack are properly etched. Many RIE steps can be performed, and the parent tier 3 RIE steps are optimized to etch the most corresponding layers of the dielectric stack. When the TEOS layer 2S9 is etched, for example, the selectivity to the nitride should be appropriately selected. The selectivity to the nitride is 3: 1 or better. This means that the TE0S is etched at the rate of the nitride three times. There are many excellent vertical sides that can be conveniently constructed around the dielectric stack. -46- The paper flower scale is applicable to the Chinese National Standards (CNS) to specifications (21〇χΓ9? Mm) ~~ ------ installed --- --- 1T C, please read the iit and matters on the back before filling this page) A7 409424 V. Description of the invention (eg) The RIE process of the wall is available. Once the etch window 240 has been accurately transferred to the TEOS layer 239, a second rie step can be performed. This second RiE step is designed to be highly selective for pad oxide 235. A selectivity of 5: 1 or better over pad oxides is suitable. The selectivity is preferably at least 1 0: 1 a. In this example, the second step of the gate forming RIE process is to design the nitride layers 238 and 231 of the dielectric stack and stop at the pad oxide layer 23 5 ′ as shown in FIG. 7 G. This second positive step is the last rie step from a sequence of separately optimized RIE steps. It is important that the selectivity for the pad oxide is 5:; or better, because otherwise the pad oxide layer 23 5 may be strongly attacked and its thickness may be reduced. The depth dgate (approximately equal to the thickness of the dielectric stack Dstack of FIG. 7F) of the gate hole 24 defines the height of the gate post, including the gate oxide, and both of these are yet to be formed. The height of the pillar t serving as a gate is usually between 100 nm and 200 nm (HGATE). In the future, the gate length of CMOS PTO will be 15nm or less. Such short gates can be easily produced using the original process. The width of the traditional gate electrode (protruding from the surface of the paper) is between 2 microns and 50 microns. After holes 240 between the dielectric stacks have been defined, residues of pad oxide 235 can be removed from the bottom of gate hole 240. This can be done by using an Hf immersion. HF is very suitable because it attacks oxides 235 and t £ s 239. HF does not attack the hard matrix23. Before removing TEOS 23 9 and pad oxide at the bottom of the interfacial hole 240, the photoresist is removed. After the complete removal of TEOS 2 3 9 and the whole oxide 235, please refer to Figure 7H, which can constitute __ -47- degrees applicable to Chinese national standards i CNS) ------ --------- install ------ Order (please read the notes on the reverse side before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed 409424 A7 B7 V. Description of the invention (45) Accurately defined gate oxide 249, As shown in Figure 71. The thickness and quality of the gate oxide 249 are not related to the thickness and quality of the pad oxide layer 235. The gate oxide can also be thicker than the whole oxide if desired. -Before forming the inter-oxide 249, a sacrificial oxide layer (not exposed) may be formed on the bottom of the gate hole 240. The sacrificial oxide layer is then etched away and the structure is heated. This short sequence of steps makes the gate hole 邛 silicon 2.0 (possibly damaged (due to the gate hole forming RIE) recoverable. In another example, the RIE process used to construct the gate hole can be designed as a dielectric, The stack and pad oxide layer 235 are etched. In this case, the selectivity to silicon for the first RIE etching process must be appropriate, because otherwise the bottom 240 of the meso 240 would be subject to money.-Once bit 23 Exposed to: the bottom of the hole 240, the gate oxide layer 249 may be formed by oxidation, as described above. Before the gate oxide layer 249 is formed, a sacrificial oxide layer may be grown, as described above. It is more important here, because the RIE damage of silicon is the most serious. The sacrificial oxide layer can be about 2 nanometers thick. Printed by the Central Bureau of Standards of the Ministry of Economy—Printed by Industrial and Consumer Cooperatives_ Button Clothing— (Please read the (Please note that this page is to be filled out again.) 4 The polysilicon 241 shown in Figure 71 is now deposited on the gate hole 24 and is located on top of the dielectric shell stack 238. It is important to ensure that the polyhard 241 fills the gate hole 24G after winter The fragmentation can be achieved by LpcVD (for example at about 65 ° C 〇)) to deposit. As mentioned earlier, amorphous silicon can be deposited instead of polysilicon. Amorphous sand can then be converted into agglomerates at a later time. Into the earth, water and stone. | One of the advantages of the original process { There can be no impurities or doped f 3 impurities when the source and non-poles are in the poly-second period, or during -48-

A7 409424 __— B7 V. Description of the invention (46) ~ _-I m ^ i-----I m ^^^^ 1 δ (Please read the note on the back and * items before filling out this page) The polysilicon gate does not have to be doped with impurities when it is planted. Polysilicon gates may be silicified (polymerized) in one of the subsequent manufacturing steps, and a cover dielectric is deposited to protect the gate during subsequent processing, if deemed appropriate 3 As mentioned further above, any Materials suitable as gate conductors can be filled to the gate hole 240. The invention is not limited to polysilicon gates. After the material 241 serving as the gate conductor is deposited, a planarization step may be performed. The CMP process is well suited to implement planarization. After planarization, the uppermost layer 238 of the dielectric stack is exposed, as shown in Figure 7J. 4 Last but not least, the dielectric stack must be removed. The nitride layers 2j8 and 231 are removed using linoleic acid. After the dielectric stack is completely removed, a protruding gate post 241 having vertical sidewalls 242 is exposed, as shown in FIG. 7K. This process can now be continued using a standard CMOS technology, such as the book "micr0 electronics processing and device design" by RA Colclaster, chapter 10, pages 266-269, and this book is by John Wiley &amp; Sons was issued in 1 980. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives In subsequent steps, the source region 243 and the drain region 244 can be defined by implanting appropriate impurities, if earlier If this is not done, as shown in Figure 7L = channel 2 4 5 (below the question post 2 4 1 and between the drain 2 4 4 and the source 2 4 3) is therefore defined. The channel length is approximately the same as the gate Length, because the source / channel and drain / channel interfaces are steep and abruptly changed (well-defined), and overlap is minimized, as discussed previously. The source-drain junction for diffusion can Polysilicon layer diffuses outwards to construct -49- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297g t) 409424 A? B7 5. Description of the invention (ordered) into 'in place of' obtained by planting Standard source and source regions, and the Constructed in the region to be doped, in this way, very shallow junctions can be obtained, as required by short-channel FETs.-An example is shown in the IBM Technical Notes Bulletin Board, Volume 2 'July 1991, 287- Page 290, titled "Source-drain Formation for Cmos Transistors Formed by Outdiffusion from PolysiiiconH 〇 To make this FET redundant, electrodes must be provided. Suitable electrodes are made of conductive materials, especially metals' such as gold, aluminum, molybdenum, Made of Zhao, 'copper, or ITO (Indium Tin Oxide)', and the conductive material is deposited by evaporation and etching, or other techniques3 In addition, it can now be formed-metallized patterns to connect adjacent FET. The foregoing examples and other examples mentioned above can be modified in various ways, as summarized below. Staff of the Ministry of Economic Affairs, Central Standards Bureau, Consumer Cooperative Society, printed n + type impurity regions, and p + type impurity regions can be used. Instead, for example, the size and shape of the impurity region can be changed. The substrate can be a broken substrate 'or a broken insulator (S 01) substrate doped with p-type impurities or n-type impurities, and this is just some possibilities. Modification, well placement can be used to define the p-type impurity region within the matrix doped with n-type impurities. For example, this allows the formation of n-type FETs (also known as n-channel FETs or NMOS) in p-type impurity regions' while p-type FETs ( (Also called p-channel FET or PMOS) can be directly formed on a matrix doped with n-type impurities. In CMOS technology, p-well or n-well diffusion is performed before forming the source and drain regions. NMOS and PMOS FETs can be constructed by this original process. MOSFETs with different channel types and structures can be fabricated within the same substrate. In addition to removing all dielectric stacks to obtain protruding gate posts 241, -50- This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) A7 B7 V. Description of the invention (shown in Figure 48, yes, For removing a part of the dielectric stack, please refer to Fig. 8. For example, only the layers 239 and 238 can be removed. In other words, the r-nitride layer 2 j 1 is not removed in this case. The electrode and the source are implanted to form a hole 250 in the nitride layer 2S1, as shown in FIG. 8. The impurity can be implanted to the region 251 of the substrate 23 through the hole 250. In defining the source and electrode regions ( After not being shown), a source-drain contact can be formed in the hole 25. Another example is described in accordance with FIG. 9. This other example is characterized in that the dielectric stack contains only nitrides (layers 261 and 263). The TEOS layer does not exist. In this case, 'the depth of the gate hole 264 (Dgate) and the thickness of the dielectric stack (DSTACK)' and the thickness of the dielectric stack are then equal to the height (hgatje) of the gate post to be formed. In standard FETs, since polybit RIE is commonly used to define closed posts, The thickness of the hafnium oxide above the pole and non-electrode regions is uneven. Because the source and non-electrode regions are implanted through an uneven pad oxide layer, the depth of the source and drain regions will be distributed throughout the wafer. Change. Another advantage of this original process is that the height and consistency of the wafer's height and the contour and size can be guaranteed. The process according to the present invention also has great potential to produce less than 0.05 Weiwei (device. Please note that devices below 0 "microns are devices with a gate length L <0. ^ This original process is very suitable for manufacturing high-density billions of bits of dram = FETs according to the present invention can be used in many different types Circuit, for example, please read the note of δ # * Matters then-fill out this page and bind it. Printed by the Central Consumers Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives -51 409424 A7 B7 V. Invention Description (49) Efficiency logic, low power logic High-density memory devices, including high-density gigabit DRAMs, as mentioned earlier. These original FETs can be easily combined with other components, such as capacitors, resistors, etc. , Diodes, memory cells, etc. Because the FETs of the present invention are small and easy to manufacture, they are also suitable for connecting organic displays or liquid crystal displays (LCD). --I — ^ 1---fl ^ n I-1 ^ 1 I TV -1 (Please read the interface precautions before filling out this page) Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs-52- This paper size applies Chinese National Standards (CNS) Ad Specifications ( 210X297 mm)

Claims (1)

The Youth Case Office Chinese application for the original (May 1989) of the old β8 years old 〆 〆 止 repair / correction / replenishment The Ministry of Economic Affairs Central Government Bureau Bureau Shellfish Consumer Cooperatives printed, applied for patent scope 1. A metal oxide semiconductor A field-effect transistor (MOSFET), the transistor includes: a drain region and a source region, and the wave region and the source region are adjacent to a channel region, and a gate oxide is located on the channel region: A gate conductor perpendicular to the side wall and above the gate oxide; the transistor further includes a threshold adjustment implantation area and / or a penetration adjustment area, and these are calibrated to the gate conductor and are limited to those below the gate conductor A region. 2. The transistor according to item 1 of the scope of patent application, wherein the threshold adjustment implantation region and / or the penetration adjustment region are limited between the drain region and the source region. 3. For the transistor of item 1 of the scope of patent application, wherein the threshold adjustment planting area and / or the penetration adjustment area have a range between 1 * 1 〇λ {17} / cm3 and 1 * 10Λ {18} Impurity concentration per cubic centimeter. 4. The transistor of item 1 of the patent application park, wherein the threshold adjustment implantation region and / or the penetration adjustment region are configured so that these regions do not contact the drain region and the source region. 5. For example, the transistor and / or the penetrating adjustment area shed (B) of the patent application Fangu. 6. For example, the transistor and / or indium (In) in the penetrating adjustment area of the patent application. 7. The transistor to the substrate of the transistor as described in the first patent application. 8. For example, the transistor of the patent application Fangu No. 1 wherein the threshold adjustment planting area is in which the threshold adjustment planting area is introduced into the p well to be deeply implanted and the n well is introduced into the well to be planted u ^ — ^^^^ 1 1— n ^ i H4 111 t— ^^^^ 1 — ^^ 1 · n ^ i _ ___. 一 -aj (Please read the precautions on the back before filling this page) This paper uses the Chinese country CNS, Chinese version of the Chinese Youth Case Application (May 89), old β8 years old, repair, correction, repair, repair, repair, repair, repair, repair, repair, repair, repair, correction, repair, print, apply for patent scope1 A metal oxide semiconductor field effect transistor (MOSFET), the transistor comprising: a drain region and a source region, and the wave region and the source region are adjacent to a channel region, and one is located above the channel region. Gate oxide: a gate conductor having a vertical side wall and located above the gate oxide; the transistor further includes a threshold adjustment implanted area and / or a penetration adjustment area, and the calibration is performed on the gate conductor 'and Limited to one area below the gate conductor. 2. The transistor according to item 1 of the scope of patent application, wherein the threshold adjustment implantation region and / or the penetration adjustment region are limited between the drain region and the source region. 3. For the transistor of item 1 of the scope of patent application, wherein the threshold adjustment planting area and / or the penetration adjustment area have a range between 1 * 1 〇λ {17} / cm3 and 1 * 10Λ {18} Impurity concentration per cubic centimeter. 4. The transistor of item 1 of the patent application park, wherein the threshold adjustment implantation region and / or the penetration adjustment region are configured so that these regions do not contact the drain region and the source region. 5. For example, the transistor and / or the penetrating adjustment area shed (B) of the patent application Fangu. 6. For example, the transistor and / or indium (In) in the penetrating adjustment area of the patent application. 7. The transistor to the substrate of the transistor as described in the first patent application. 8. For example, the transistor of the patent application Fangu No. 1 wherein the threshold adjustment planting area is in which the threshold adjustment planting area is introduced into the p well to be deeply implanted and the n well is introduced into the well to be planted u ^ — ^^^^ 1 1— n ^ i H4 111 t— ^^^^ 1 — ^^ 1 · n ^ i _ ___. 一 -aj (Please read the precautions on the back before filling this page) This paper uses the Chinese country Kneading rate (CNS), 409424 b C8 --- --- PS, patent application range '' to the substrate of the transistor 〃 9. For the transistor of the scope of application 丨, the drain region and source region All form a steep slope joint with the channel. 10. The transistor according to item 1 of the patent application scope, wherein the drain region and the source region are doped with P-type impurities. 11. For example, the transistor of the scope of application for patent i, wherein the drain region and the source region are doped with n-type impurities. 12. The transistor according to item 1 of the scope of patent application, wherein the gate conductor comprises a polycrystalline silicon. The transistor according to item 1 of the scope of patent application, wherein the gate conductor comprises a crane. Η. The transistor as described in the first item of the patent application scope, and the transistor is a sub-0.1 micrometer device 'and has a gate length L of less than 0.1 micrometer. 15 * If the transistor in the patent application item 1 'where the gate oxide has a thickness in the range of several nanometers' "16. · If the patent in the patent application item 1 where the transistor is a PMOS' NMOS, or CMOS transistor. Π. The transistor of item 1 of the patent application, wherein the channel region contains a dream that is not doped with impurities. Printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumer Cooperatives * 1 ^^ — I n TJ .¾ T * (Please read the note on the back before filling in this page) 18_If you apply for the first scope of the patent application A crystal, wherein the threshold adjustment implantation region and / or the penetration adjustment region include boron (B) and indium (In). 19. If the transistor in the first item of the patent application scope, the interface between the source region and the drain region, and the interface between the drain region and the channel region are clearly defined. 20 · As for the transistor in the first item of the patent application scope, where the source region and the drain region are ___ -2- this paper degree is applicable to the Chinese national standard (CNS &gt; A4 now (2 丨 0X297 mm) 409424 b C8 --- --- PS, the scope of the patent claim 'to the substrate of the transistor 〃 9. For the transistor of the scope of application 丨, the drain region and the source region all form a steep joint with the channel. 10. If the transistor in the scope of the patent application is applied to item 1, the drain and source regions are doped with P-type impurities. 11. If the transistor in the scope of the patent application is applied to item i, the drain and source regions are doped. There are η-type impurities. 12. For example, the transistor of the scope of the patent application, wherein the gate conductor contains a polycrystalline silicon, as described in the scope of the patent scope of the patent application, the gate conductor contains a crane. The transistor of item 1 of the patent scope, and the transistor is a sub-0.1 micron device, and has a gate length L of less than 0.1 micron. 15 * As the transistor of the item 1 of the patent scope, wherein the gate oxide has Thickness in the range of several nanometers "16. If the transistor in the first item of the patent application, The transistor is a PMOS 'NMOS, or CMOS transistor. Π · As in the patent application Fanyuan No. 1 transistor, where the channel area contains dreams do not contain impurities. Central Ministry of Economic Affairs Ministry of Economic Affairs Consumer Cooperatives Print * 1 ^^ — I n TJ .¾ T * (Please read the note on the back side before filling in this page) 18_If you apply for the transistor in the first scope of the patent application, the threshold adjusts the planting area And / or the penetrating adjustment region includes boron (B) and indium (In). 19. If the transistor of the scope of application for the first item of the patent, wherein the interface between the source region and the drain region, and the drain region and the channel region The interface is clearly defined. 20 · If the transistor in the first patent application scope, the source region and the drain region ___ -2- This paper is applicable to Chinese national standards (CNS &gt; A4present grid (2 丨0X297mm) The slopes of the interface printed by π and patent application of the Central Standards Bureau of the Ministry of Economic Affairs of the ABCD, and the interface between the drain region and the channel region are very steep. Β 21. A kind of metal oxide Semiconductor field effect transistor (MOSFET) method, the method includes the following Step: Construct a dielectric stack on the semiconductor structure; define an etch window on the dielectric stack, and the etch window has the lateral size and shape of the gate hole to be formed; transfer the etch window by using a reactive ion etching (RIE) process To the dielectric stack to define the gate hole of the dielectric stack; planting threshold adjustment impurities and / or penetrating adjustment impurities through the gate hole; depositing a gate conductor so that the gate conductor fills the gate hole; removing covering around the gate hole Gate conductor of the semiconductor structure portion; removing at least a portion of the dielectric stack. 22. According to the method of item 21 in the scope of patent application, the threshold adjustment impurities and penetration adjustment impurities are planted through the gate hole. 23_ The method of claim 21, wherein the dielectric stack includes at least one pad oxide layer. 24. The method of claim 21, wherein the dielectric stack includes a nitride layer, and preferably a silicon nitride layer. 25. The method according to item 21 of the patent application, wherein the dielectric stack includes a tetraethylnormal silicic acid (TEOS) layer. 26. The method of claim 23, wherein the thickness of the pad oxide layer is between 5 nm and 20 nm. 27. The method of claim 21, wherein the etching window is defined by using a photoresist and a subsequent photolithography process. _ -3- This paper ruler and free-use Chinese home appliance (CNS) M wash grid (2 丨 〇χ297mm) (Please read the precautions on the back before filling this page); ^ _ Order ABCD Central The slopes of the interface printed by π, patent application scope, and the interface of the drain region and the channel region are very steep in the standard bureau ’s consumer cooperatives. 21. A kind of metal oxide semiconductor field effect crystal (M 〇SFET) method, the method includes the following steps: forming a dielectric stack on the semiconductor structure; defining an etch window in the dielectric stack, and the etch window has the lateral size and shape of the gate hole to be formed; by using active ions Etching (RIE) process to transfer the etch window to the dielectric stack to define the gate hole of the dielectric stack; planting threshold adjustment impurities and / or penetrating adjustment impurities through the gate hole; depositing a gate conductor Full gate hole; removing gate conductors covering portions of the semiconductor structure surrounding the gate hole; removing at least a portion of the dielectric stack. 22. According to the method of item 21 in the scope of patent application, the threshold adjustment impurities and penetration adjustment impurities are planted through the gate hole. 23_ The method of claim 21, wherein the dielectric stack includes at least one pad oxide layer. 24. The method of claim 21, wherein the dielectric stack includes a nitride layer, and preferably a silicon nitride layer. 25. The method according to item 21 of the patent application, wherein the dielectric stack includes a tetraethylnormal silicic acid (TEOS) layer. 26. The method of claim 23, wherein the thickness of the pad oxide layer is between 5 nm and 20 nm. 27. The method of claim 21, wherein the etching window is defined by using a photoresist and a subsequent photolithography process. _ -3- This paper ruler and free-use Chinese home appliance (CNS) M wash grid (2 丨 〇χ297 mm) (Please read the precautions on the back before filling this page); ^ _ Order 409424 A8 B8 C8 __ D8 patent application scope (please read the notes on the back before filling this page) 28. If the method of patent application scope item 21, the etching window is transferred by using a series of reactive ion etching (RIE) steps To the dielectric stack. 29. The method of claim 28, wherein each step of the series of active ion etching (RIE) steps is optimized for the corresponding layer of the dielectric stack to be etched. 30. The method of claim 28 in the scope of the patent application, wherein the sequence of reactive ion etching (RIE) steps is optimized to etch a gate hole with vertical sidewalls passing through the dielectric stack. 31 The method according to item 23 of the patent application park, wherein the rubidium oxide layer at the bottom of the gate hole is removed after the step for defining one gate hole of the dielectric stack. 32. The method according to item 31 of the scope of patent application, wherein the entire oxide layer at the bottom of the gate hole is removed by using wet etching. 33. The method according to item 31 of the scope of patent application, wherein the planting of the threshold adjustment impurities or the planting of penetrating impurities is performed before the rubidium oxide layer is removed. 34. For the method of applying for item No. 3 丨 in the scope of patent application, where the threshold is adjusted for the impurity cloth, printed by the male workers' consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, or the cloth that penetrates the impurities is implemented after the pad oxide layer is removed. 35. The method according to item 2 of the patent application scope, in which a thin gate oxide is formed at the bottom of the gate hole after the step of planting a threshold for adjusting impurities or penetrating impurities a. 36. The method of item 35, wherein the thin gate oxide is formed by heating. 409424 A8 B8 C8 __ D8 Patent application scope (please read the precautions on the back before filling this page) 28. For the method of patent application No. 21, the etching window is by using a series of reactive ion etching (RIE ) Step to transfer to the dielectric stack. 29. The method of claim 28, wherein each step of the series of active ion etching (RIE) steps is optimized for the corresponding layer of the dielectric stack to be etched. 30. The method of claim 28 in the scope of the patent application, wherein the sequence of reactive ion etching (RIE) steps is optimized to etch a gate hole with vertical sidewalls passing through the dielectric stack. 31 The method according to item 23 of the patent application park, wherein the rubidium oxide layer at the bottom of the gate hole is removed after the step for defining one gate hole of the dielectric stack. 32. The method according to item 31 of the scope of patent application, wherein the entire oxide layer at the bottom of the gate hole is removed by using wet etching. 33. The method according to item 31 of the scope of patent application, wherein the planting of the threshold adjustment impurities or the planting of penetrating impurities is performed before the rubidium oxide layer is removed. 34. For the method of applying for item No. 3 丨 in the scope of patent application, where the threshold is adjusted for the impurity cloth, printed by the male workers' consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, or the cloth that penetrates the impurities is implemented after the pad oxide layer is removed. 35. The method according to item 2 of the patent application scope, in which a thin gate oxide is formed at the bottom of the gate hole after the step of planting a threshold for adjusting impurities or penetrating impurities a. 36. The method of item 35, wherein the thin gate oxide is formed by heating. Α8 Β8 C8 D8 409424 Application for patent scope 37. For the method of patent application No. 35, where the thickness of the thin gate oxide is less than 5 nm a 38_ For the method of patent application No. 21, where the gate conductor Contains polysilicon or 39. The method according to item 21 of the patent application, wherein the chemical mechanical polishing (CMP) process is used to remove some gate conductors, and the gate conductors cover the dielectric stacking portion surrounding the gate hole. 40 'The method as claimed in item 21 of the scope of patent application' and the transistor is a sub-0.1 micrometer device 'and has a gate length L of less than 0.1 micrometer. 41. The method of claim 21, wherein the metal oxide semiconductor field effect transistor is a PMOS, NMOS, or CMOS transistor. 42. The method of claim 21, wherein the step of implanting the deep implant is performed before the etching window is defined. 43_ The method according to item 42 of the scope of patent application, wherein the concentration of the impurity in the deep implant is about 1 * 108 {16} / cm3. 44. The method according to item 21 of the patent application park, wherein the impurity concentration in the threshold adjustment planting area and the penetration adjustment area is between 1 * 10λ {17} / cm3 and "10Λ {18} / cm3" 45_ The method according to item 21 of the patent application, wherein the source region and the drain region are formed by implanting impurities after the step for removing at least a part of the dielectric stack, and the source electrode Both the region and the non-polar region have a steep junction surface leading to the channel, and the channel is located below the edges of the gate pillar and the gate oxide. 46. The method according to item 45 of the patent application scope, wherein the junction region of the source region and the channel region As well as the junctions of the non-polar region and the channel region are clearly defined. _______ -5- This paper is in line with the Chinese National Standard (CNS &gt; Α4 ·· (210X297 mm)-, --- ^ 1 ^^^ 1 --I «— ^ 1 '·· ^ (Please read the notes on the back before filling out this page) Printed by the Central Ministry of Economic Affairs of the Central Government Bureau of the Workers’ Cooperatives A8 Β8 C8 D8 409424 Patent scope 37. If applying for a patent Method according to item 35, wherein the thickness of the thin gate oxide is less than 5 nm a 38_ Please apply the method of the scope of the patent No. 21, in which the gate conductor contains polysilicon or 39. For the method of the scope of the patent application No. 21, the chemical mechanical polishing (CMP) process is used to remove some gate conductors, and these gates The conductor covers the portion of the dielectric stack surrounding the gate hole. 40'The method according to item 21 of the patent application 'and the transistor is a sub-0.1 micron device'and has a gate length L less than 0.1 micron. 41 · The method according to item 21 of the patent application, wherein the metal oxide semiconductor field effect transistor is a PMOS, NMOS, or CMOS transistor. 42. The method according to item 21 of the patent application, which is used for implantation The planting step is implemented before the etching window is defined. 43_ The method of applying for the scope of the patent No. 42 'wherein the impurity concentration for the deep planting is about 1 * 108 [16] / cubic centimeter. 44. If applied The method of the 21st item in the patent model garden, wherein the impurity concentration in the threshold adjustment planting area and the penetration adjustment area is between 1 * 10λ {17} / cm3 and "10Λ {18} / cm3". 45 _If the method of applying for the scope of patent No. 21, where the source The region and the drain region are formed by implanting impurities after the step for removing at least a part of the dielectric stack, and the source region and the non-electrode region have steep junctions leading to the channel, and the channel is located at Gates and gate oxides are below the edge. 46. The method of item 45 of the patent application, in which the junction area of the source region and the channel region and the junction surface of the non-polar region and the channel region are clearly defined. _______ -5 -This paper is not compatible with the Chinese national standard (CNS &gt; Α4 Listening · (210X297mm)-, ----- ^ 1 ^^^ 1--I «— ^ 1 '·· ^ (Please read the first Please fill out this page again) Printed by the Central Ministry of Economic Affairs of the Ministry of Economic Affairs of the shoulder work consumer cooperatives 409424 A8 BS C8 D8 'The slopes of the junctions between the source and channel regions and the junctions between the drain and channel regions are steep. 48. The method according to item 21 of the scope of patent application, wherein the effective gate length is defined by the length of the gate post. 49. The method of claim 21 in the scope of patent application, wherein: a sacrificial oxide layer is formed at the bottom of the gate hole, the sacrificial oxide layer is then etched away, and a metal oxide is deposited before a gate conductor is deposited The semiconductor field effect transistor is heated. 50. The method according to item 21 of the scope of patent application, wherein high-dose impurities are implanted through the interrogation hole so that the impurities can serve as the ground plane of the corresponding transistor. 51. A method for manufacturing a metal oxide semiconductor field-effect transistor (MOSFet) 2 'The method includes the following steps: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; by using activity Ion etching (RIE) process to transfer the etching window to the dielectric stack to define a gate hole in the dielectric stack; deposit a sidewall layer; remove the sidewall layer from the horizontal surface so that the sidewall spacers remain in the gate Within the hole, thereby reducing the lateral size of the gate hole; depositing a gate conductor so that the gate conductor fills the hole; removing the gate conductor outside the gate hole; removing at least a portion of the dielectric stack; and removing the sidewall spacers . jm ^ i ^^^ 1 n I n ^ i _nn n ^^^ 1 n ^ i In! * aJ (Please read Note 4 ^-on the back before filling this page) 409424 A8 BS C8 D8 Central Ministry of Economic Affairs Standard Bureau of Work Consumer Cooperatives printed the scope of patent application 47. For the method of applying for scope 45 of the patent application, 'the slope of the junction between the source region and the channel region and the junction between the drain region and the channel region are very steep. 48. The method according to item 21 of the scope of patent application, wherein the effective gate length is defined by the length of the gate post. 49. The method of claim 21 in the scope of patent application, wherein: a sacrificial oxide layer is formed at the bottom of the gate hole, the sacrificial oxide layer is then etched away, and a metal oxide is deposited before a gate conductor is deposited The semiconductor field effect transistor is heated. 50. The method according to item 21 of the scope of patent application, wherein high-dose impurities are implanted through the interrogation hole so that the impurities can serve as the ground plane of the corresponding transistor. 51. A method for manufacturing a metal oxide semiconductor field-effect transistor (MOSFet) 2 'The method includes the following steps: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; by using activity Ion etching (RIE) process to transfer the etching window to the dielectric stack to define a gate hole in the dielectric stack; deposit a sidewall layer; remove the sidewall layer from the horizontal surface so that the sidewall spacers remain in the gate Within the hole, thereby reducing the lateral size of the gate hole; depositing a gate conductor so that the gate conductor fills the hole; removing the gate conductor outside the gate hole; removing at least a portion of the dielectric stack; and removing the sidewall spacers . jm ^ i ^^^ 1 n I n ^ i _nn n ^^^ 1 n ^ i In! * one aJ (please read the note 4 ^-on the back before filling this page) 409424 patent application scope A8 B8 C8 D8 Printed by the Male Workers' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 52. If the method of applying for the scope of patent No. 51 is a nitride layer, and preferably a silicon nitride layer. 53. The method according to item 51 of the scope of patent application Tetraethyl Normal Silicate (TEOS) layer. 54. A method polymer as claimed in item 51 of the patent application. 55. If the method of the scope of the patent application No. 51-photoresist and a subsequent photolithography process to define 56. If the method of the patent scope of the patent application No. 5 i, the etching window is by using-sequence of active ions An etch (RIE) step to transfer to the dielectric stack. The method according to item 5 of the patent application range, wherein each step of the series of active ion etching (RIE) steps is optimized for the corresponding layer of the dielectric stack to be etched. 58. The method of claim 5, wherein the active ion engraving (RIE) step of the sequence is optimized to engrav a gate hole with vertical sidewalls passing through the dielectric stack. 59. The method of claim 57 in which the active ion last name (RIE) step of the sequence is at least 5: 1 in selectivity to oxides. 60. The method of claim 5 丨, wherein a thin oxide is formed on the bottom of the gate hole after the 'side wall layer is removed from the horizontal surface. 61. The method according to item 60 of the patent application ', wherein the thin gate oxide is constituted by heating. 62. For the method of applying for the scope of patent No. 60, wherein the thickness of the thin gate oxide is in which the dielectric stack includes a dielectric stack including the dielectric stack including the etching window by using (please read the precautions on the back before filling (This page) Binding-The size of the bound paper is subject to the Chinese National Standard (〇 阳) 6 4 specifications (210 &gt; &lt; 297 mm) 409424 Patent application scope A8 B8 C8 D8 Printed by the male workers' cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 52. If the method of applying for the scope of patent No. 51, nitride layer, and preferably silicon nitride Floor. 53. The method according to item 51 of the scope of patent application Tetraethyl Normal Silicate (TEOS) layer. 54. A method polymer as claimed in item 51 of the patent application. 55. If the method of the scope of the patent application No. 51-photoresist and a subsequent photolithography process to define 56. If the method of the patent scope of the patent No. 5 i, the etching window is by using-sequence of active ions An etch (RIE) step to transfer to the dielectric stack. The method according to item 5 of the patent application range, wherein each step of the series of active ion etching (RIE) steps is optimized for the corresponding layer of the dielectric stack to be etched. 58. The method of claim 5, wherein the active ion engraving (RIE) step of the sequence is optimized to engrav a gate hole with vertical sidewalls passing through the dielectric stack. 59. The method of claim 57 in which the last step of the active ion nicking (RIE) step of the sequence is at least 5: 1 for the oxide. 60. The method of claim 5 丨, wherein a thin oxide is formed on the bottom of the gate hole after the 'side wall layer is removed from the horizontal surface. 61. The method of claim 60, wherein the thin gate oxide is formed by heating. 62. For the method of applying for item 60 in the scope of patent application, where the thickness of the thin gate oxide is in which the dielectric stack includes a dielectric stack including the dielectric stack including an etching window by using (please read the precautions on the back before filling (This page) Binding-The size of the bound paper is subject to the Chinese National Standard (〇 阳) 6 4 specifications (210 &gt; &lt; 297 mm) 409424 A8 Βδ C8 D8 Printed by the Male Workers Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs. 6. The scope of patent application is less than 5 nm. 63. The method of claim 51, wherein the gate conductor comprises polysilicon or tungsten. 64. For example, the method of the 51st item in the patent application park, wherein the chemical mechanical polishing (CMp) process is used to remove some gate conductors, and the gate conductors cover the dielectric stacking portion surrounding the gate holes. 65. If the method of the scope of application for the item 51 of the patent is applied, the dielectric stack is removed. 66. The method according to item 65 of the scope of patent application The media stack is removed together. 67. The method according to item 51 of the scope of patent application has been removed separately. 68. Applicable to the method of patent application No. 5 丨 The device with a gate length (l) of 150 nm 69. Applicable to the method of the patent application No. 51 The device with a gate length (L). 70_ The method according to item 5 of the scope of patent application. The body field effect transistor is a PMOS, NMOS, or CMOS transistor. 71_ The method according to item 5 of the scope of patent application 'where the source region and the drain region are formed by implanting impurities', and the source region and the drain region both have a steep junction surface leading to the channel, and The channel is located below the edges of the gate post and gate oxide. 72. The method according to item 71 of the scope of patent application, wherein the joint surfaces of the source region and the channel region and the joint surfaces of the drain region and the channel region are clearly defined. Among them, after forming the gate post, all the sidewall spacers together with the dielectric sidewall spacers and the dielectric are formed, and the transistor is smaller than the transistor and has a secondary light in which the metal oxide semiconducting! II i III n. HI. IT (Please read the notes on the back before filling in this page) -8- The paper size is in Chinese National Standards (CNS) M Grid (2Ι〇 × 297 mm) 409424 A8 Βδ C8 D8 Printed by Bureau of Male Workers Consumer Cooperatives 6. The scope of patent application is below 5 nm. 63. The method of claim 51, wherein the gate conductor comprises polysilicon or tungsten. 64. For example, the method of the 51st item in the patent application park, wherein the chemical mechanical polishing (CMp) process is used to remove some gate conductors, and the gate conductors cover the dielectric stacking portion surrounding the gate holes. 65. If the method of the scope of application for the item 51 of the patent is applied, the dielectric stack is removed. 66. The method according to item 65 of the scope of patent application The media stack is removed together. 67. The method according to item 51 of the scope of patent application has been removed separately. 68. Applicable to the method of patent application No. 5 丨 The device with a gate length (l) of 150 nm 69. Applicable to the method of the patent application No. 51 The device with a gate length (L). 70_ The method according to item 5 of the scope of patent application. The body field effect transistor is a PMOS, NMOS, or CMOS transistor. 71_ The method according to item 5 of the scope of patent application 'where the source region and the drain region are formed by implanting impurities', and the source region and the drain region both have steep junctions leading to the channel, The channel is located below the edges of the gate post and gate oxide. 72. The method according to item 71 of the scope of patent application, wherein the joint surfaces of the source region and the channel region and the joint surfaces of the drain region and the channel region are clearly defined. Among them, after forming the gate post, all the sidewall spacers together with the dielectric sidewall spacers and the dielectric are formed, and the transistor is smaller than the transistor and has a secondary light in which the metal oxide semiconducting! II i III n. HI. IT (please read the precautions on the reverse side before filling out this page) -8- The size of the paper sheet uses China National Standards (CNS) M Grid (2Ι〇 × 297 mm) 409424 A8 B8 C8 D8 Patent Application Park 73 'If the method is called item 71 of the patent scope, the slopes of the junction between the source and channel regions and the junction between the drain and channel regions are very steep. 74 ’The method of item 51 in the scope of patent application, wherein the effective length is defined by the length of the brake (L). 75. The method of claim 51 in the scope of patent application, wherein a sacrificial oxide layer is formed at the bottom of the gate hole; the sacrificial oxide layer is then etched away, and the metal oxide semiconductor field effect transistor is heated. 76. The method of claim 51, wherein the pad oxide layer is formed on the semiconductor structure before the etched window defining the dielectric stack. 77. The method of claim 76, wherein the thickness of the pad oxide layer is between 5 nm and 20 nm. 78. The method of claim 76 of the patent application, wherein the pad oxide layer at the bottom of the mesopores is removed after defining the gate holes of the dielectric stack. 79. The method of claim 76, wherein the pad oxide layer at the bottom of the gate hole is removed by using a wet cut. 80. A metal oxide semiconductor field effect transistor (MOSFET), the transistor includes a drain region and a source region, and the drain region and the source region are adjacent to a channel region; A thin gate oxide above the channel region; a gate conductor above the gate oxide layer; the gate conductor has vertical sidewalls and the junction between the source region and the channel region and the junction between the drain region and the channel region Very steep. This paper size is suitable for middle and poor countries (CNS &gt; A4 size (2 丨 0 &gt; &lt; 25) 7 mm) (Please read the notes on the back before filling out this page] Ding printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 409424 A8 B8 C8 D8 Patent Application Park 73 ' The method of item 71, wherein the slopes of the junctions between the source region and the channel region and the junctions between the drain region and the channel region are very steep. 74 'As in the method of claim 51, the effective length is borrowed. Defined by the length (L) of the gate. 75. As in the method of claim 51 in the scope of patent application, a sacrificial oxide layer is formed at the bottom of the gate hole; the sacrificial oxide layer is then etched away, and the metal The oxide semiconductor field effect transistor is heated. 76. The method of item 51 in the scope of patent application, wherein the pad oxide layer is formed in the semiconductor structure before defining the etch window of the dielectric stack. 77. In the scope of patent application 76 Item, wherein the thickness of the pad oxide layer is between 5 nm and 20 nm. 78. For the method of claim 76 in the scope of patent application, the pad oxide layer at the bottom of the mesopore is in use The gate holes defining the dielectric stack are removed. 79. For example, the method in the scope of patent application No. 76, wherein the pad oxide layer at the bottom of the gate holes is removed by using a wet engraving. 80. A metal oxide semiconductor field MosFET, the transistor includes = a drain region and a source region, and the drain region and the source region are adjacent to a channel region; a thin gate oxide on the channel region A gate conductor above the gate oxide layer; the gate conductor has vertical sidewalls and the junction between the source region and the channel region and the junction between the drain region and the channel region are very steep. Trapped countries (CNS &gt; A4 specifications (2 丨 0 &gt; &lt; 25) 7 mm) (Please read the notes on the back before filling out this page] Ding Printing 8 888 ABCD Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives of the Ministry of Economic Affairs Scope of patent 81. For example, the transistor of the 80th scope of the patent application, wherein the gate oxide is a thermally grown gate oxide. 82. For the transistor of the 80th scope of the patent application, the gate conductor includes a polymer. 〇83. For example, the transistor of the patent application No. 80, wherein the gate conductor contains a town. 84. For the transistor of the patent application No. 80, and the transistor is a sub-zero micron device, and has Less than 0.1 micron gate length L. 85. For example, the transistor of the patent application No. 80, wherein the gate oxide has a thickness in the range of several nanometers. 86. For the transistor of the patent application No. 80, The MOSFET is a PMOS, NMOS, or CMOS transistor. 87. For example, the transistor in the scope of patent application No. 80, wherein the channel region contains silicon not doped with impurities. 88. If the transistor in the scope of patent application No. 80, Where the channel area contains There is boron, or marry, or any combination of boron and indium. 89. For example, the transistor of patent application No. 80, wherein the channel region contains phosphorus, or arsenic, or antimony, or phosphorus and kun and antimony. 90. If the transistor of patent application No. 80 is applied, the interface between the source region and the drain region and the interface between the Ϊ &amp; pole region and the channel region are clearly defined. 91. If applying for a patent For the transistor in the 80th range, the slope of the interface between the source region and the drain region and the interface between the non-polar region and the channel region is very steep. 92. For example, the transistor in the 80th range of the patent application is effective. The gate length is borrowed from -10- this paper size, using China National Standard (CNS) A4 (210X297 mm) ^^ 1 ml In HI n I — ^ 1 «In----.1 ^ In ^ aJ (Please read the note on the back of the page before filling in this page) 8 888 ABCD Printed patent application scope of the Male Workers Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs Oxidation is a thermally grown gate oxide. 82 · Electricity in the 80th scope of the patent application Body, wherein the gate conductor comprises a polycrystalline silicon. The transistor according to item 80 of the patent application range, wherein the gate conductor comprises a town. 84. As the transistor including the scope of patent application No. 80, and the transistor This is a 0 ”micron device and has a gate length L of less than 0.1 micron. 85. For example, the transistor of the patent application No. 80, wherein the gate oxide has a thickness in the range of several nanometers. 86. If applied The transistor of the scope of the patent No. 80, wherein the MOSFET is a PMOS, NMOS, or CMOS transistor. 87. The transistor of claim 80, wherein the channel region contains silicon not doped with impurities. 88. The transistor of claim 80, wherein the channel region comprises a chip doped with boron, or marry, or any combination of boron and indium. 89. The transistor of claim 80, wherein the channel region comprises silicon doped with phosphorus, or arsenic, or antimony, or any combination of phosphorus and antimony. 90. For the transistor with the scope of patent application No. 80, the interface between the source region and the drain region and the interface between the Ϊ &amp; polar region and the channel region are clearly defined. 91. For the transistor in the 80th area of the patent application, the slope of the interface between the source region and the drain region and the interface between the non-polar region and the channel region is very steep. 92. If the transistor of the 80th item of the patent application is applied, where the effective gate length is -10-, this paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) ^^ 1 ml In HI n I — ^ 1 «In----.1 ^ In ^ aJ (Please read the note on the back before filling in this page) 40942 ^ AS B8 C8 D8 Printed by the Central Laboratories of the Ministry of Economy The thickness of the oxide layer, in which the etching window is defined by the length of the gate conductor by using six, patent applications. &Gt; 93_ — a method for manufacturing a metal oxide semiconductor field effect transistor (MOSFET), the method The method comprises the following steps: forming a dielectric stack on a semiconductor structure, and the semiconductor structure includes at least an oxide layer; defining a engraved window on the dielectric stack, and the etching window has a lateral size and shape of a gate pillar to be formed; ; Defining a gate hole in the dielectric stack by using an active ion etching (RIE) process to transfer the etch window to the dielectric stack; depositing a gate conductor so that the gate conductor fills the inter-holes; removing the covering and surrounding The gate conductor of the semiconductor structure portion of the hole; removing at least part of the dielectric stack, so that a gate pillar with a vertical sidewall is released. 94. For example, the method of item 93 of the patent application scope, wherein the dielectric stack stack includes a nitride Layer 'and preferably a silicon nitride layer. 95. The method of claim 93, wherein the dielectric stack includes a tetraethylnormal silicic acid (TEOS) layer. 96_ If the method of applying for the item 93 of the patent scope is between 5 nm and 20 nm 97. For the method of applying for the item 93 of the patent scope 93 a photoresist and a subsequent lithography process to define 98. For example, the method of applying patent No. 93, wherein the etching window is transferred to the dielectric stack by using a sequence of reactive ion etching (RIE) steps. 99. The method of applying scope No. 98, wherein the sequence of Active ion-11-_ hemp t national standard I-: | I i .....------ II-II! I (Please read the precautions on the back before filling out this page) 40942 ^ AS B8 C8 D8 The thickness of the pad oxide layer is printed by the Central Working Group of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, where the etching window is defined by the length of the gate conductor by using the patent application scope. A method for manufacturing a metal oxide semiconductor field effect transistor (MOSFET), the method includes the following steps: forming a dielectric stack on a semiconductor structure, and the semiconductor structure includes at least a pad oxide layer; The dielectric stack, and the etch The window has the lateral size and shape of the gate pillar to be formed; a gate hole in the dielectric stack is defined by transferring the etched window to the dielectric stack using a reactive ion etching (RIE) process; and a gate conductor is deposited such that The gate conductor fills the gap; the gate conductor covering the semiconductor structure portion surrounding the gate hole is removed; at least part of the dielectric stack is removed so that a gate pillar with a vertical side wall is released. The method of 3, wherein the dielectric stack includes a nitride layer and preferably a silicon nitride layer. 95. The method of claim 93, wherein the dielectric stack includes a tetraethylnormal silicic acid (TEOS) layer. 96_ If the method of applying for the item 93 of the patent scope is between 5 nm and 20 nm 97. For the method of applying for the item 93 of the patent scope 93 a photoresist and a subsequent lithography process to define 98. For example, the method of applying patent No. 93, wherein the etching window is transferred to the dielectric stack by using a sequence of reactive ion etching (RIE) steps. 99. The method of applying scope No. 98, wherein the sequence of Active ion-11-_ hemp t national standard I-: | I i .....------ II-II! I (Please read the precautions on the back before filling this page) Economy Printed by 409424 5? C8 D8 in the patent application scope of the Ministry of Industry and Technology Bureau of Fengfeng Bureau. Each step of the etching (RIE) step is optimized for the corresponding layer of the dielectric stack ink to be etched. &amp; 100. The method of claim 98, wherein the active ion etch (RIE) step of the sequence is optimized to engrav a gate hole with vertical sidewalls passing through the dielectric stack. 101. If the method according to the scope of patent application is 98, wherein the last step of the sequence of the active ion etching (RIE) step is at least 5 for oxide selectivity. 102. If the method is within the scope of patent application 93, The pad oxide layer at the bottom of the gate hole is removed after the step used to define one gate hole of the dielectric stack. 103. The method according to the scope of patent application No. 102, wherein the hafnium oxide layer at the bottom of the gate hole is removed by using wet etching. 104. The method of claim 93, wherein a thin gate oxide is formed at the bottom of the gate hole. 105. The method according to item 104 of the scope of patent application, wherein the thin gate oxide is formed by heating. 106. The method of claim 104, wherein the thickness of the thin gate oxide is less than 5 nm. 107. The method of claim 93, wherein the gate conductor comprises polysilicon or a ballast. 108. The method of claim 93, wherein the chemical mechanical polishing (CMP) process is used to remove some gate conductors, and the gate conductors cover the dielectric stack portion surrounding the gate holes. -12 The size of this paper is free to use Chinese National Standard (CNS) Α4 size (210X297 mm) {Please read the precautions on the back before filling out this page) 11T Printed by the Central Bureau of Fengfeng, Ministry of Economic Affairs, Shellfish Consumer Cooperative, 409424 5? Each step of the C8 D8 patent application range etching (RIE) step is optimized for the corresponding layer of the dielectric stack ink to be etched. &amp; 100. The method of claim 98, wherein the active ion etch (RIE) step of the sequence is optimized to engrav a gate hole with vertical sidewalls passing through the dielectric stack. 101. If the method according to the scope of patent application is 98, wherein the last step of the sequence of the active ion etching (RIE) step is at least 5 for oxide selectivity. 102. If the method is within the scope of patent application 93, The pad oxide layer at the bottom of the gate hole is removed after the step used to define one gate hole of the dielectric stack. 103. The method according to the scope of patent application No. 102, wherein the hafnium oxide layer at the bottom of the gate hole is removed by using wet etching. 104. The method of claim 93, wherein a thin gate oxide is formed at the bottom of the gate hole. 105. The method according to item 104 of the scope of patent application, wherein the thin gate oxide is formed by heating. 106. The method of claim 104, wherein the thickness of the thin gate oxide is less than 5 nm. 107. The method of claim 93, wherein the gate conductor comprises polysilicon or a ballast. 108. The method of claim 93, wherein the chemical mechanical polishing (CMP) process is used to remove some gate conductors, and the gate conductors cover the dielectric stack portion surrounding the gate holes. -12 The scale of this paper is free to use Chinese National Standard (CNS) Α4 size (210X297 mm) {Please read the notes on the back before filling out this page) 11T 409424 ABCD Printed by the Bayer Consumer Cooperative of the Central Government of the Ministry of Economic Affairs «. 6. Patent application group 109. In the method of the scope of patent application (1), the entire dielectric stack is removed after forming the gate post. 110. The method according to item 93 of the patent application park, and the transistor is a sub-micrometer device 'and has a gate length L of less than 0.1 micron. 111. The method of claim M, wherein the metal oxide semiconductor field effect transistor is a PMOS, NMOS, or CMOS transistor. 112. A method as claimed in claim 104, wherein the thin gate oxide structure is irrelevant to the pad oxide layer. 113 'The method of claim 4 in which the thickness of the thin gate oxide is different from the thickness of the pad oxide layer. 114. The method according to item 93 of the patent application 'wherein the source region and the drain region are formed by implanting impurities, and the source region and the drain region both have a steep junction surface leading to the channel, and the channel Located below the edge of the gate. 115. The method according to item 114 of the scope of patent application, wherein the joint surfaces of the source region and the channel region and the joint surfaces of the non-polar region and the channel region are clearly defined. 116. If the method of applying for the item No. 114 of the scope of the patent application 'wherein the slope of the junction surface of the source region and the channel region and the junction surface of the pole region and the channel region are very Jl Xiao 4 Three methods, in which the effective gate length is defined by the length of the gate. 118. The method of claim 93, wherein a sacrificial oxide layer is formed on the bottom of the gate hole; the sacrificial oxide layer is then etched away, and the metal oxide semiconductor field effect transistor is heated. -13 · This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ mi II, (please read the precautions on the back before filling this page) 409424 ABCD Central Government Standards Bureau of the Ministry of Economic Affairs Industrial and consumer cooperative seal «. 6. Patent application group 109. For the method of applying for item (1) of the patent scope, in which all the dielectric stacks are removed after forming the gate post. 110. The method according to item 93 of the patent application park, and the transistor is a sub-micrometer device 'and has a gate length L of less than 0.1 micron. 111. The method of claim M, wherein the metal oxide semiconductor field effect transistor is a PMOS, NMOS, or CMOS transistor. 112. A method as claimed in claim 104, wherein the thin gate oxide structure is irrelevant to the pad oxide layer. 113 'The method of claim 4 in which the thickness of the thin gate oxide is different from the thickness of the pad oxide layer. 114. The method according to item 93 of the patent application 'wherein the source region and the drain region are formed by implanting impurities, and the source region and the drain region both have a steep junction surface leading to the channel, and the channel Located below the edge of the gate. 115. The method according to item 114 of the scope of patent application, wherein the joint surfaces of the source region and the channel region and the joint surfaces of the non-polar region and the channel region are clearly defined. 116. If the method of applying for the item No. 114 of the scope of the patent application 'wherein the slope of the junction surface of the source region and the channel region and the junction surface of the pole region and the channel region are very Jl Xiao 4 Three methods, in which the effective gate length is defined by the length of the gate. 118. The method of claim 93, wherein a sacrificial oxide layer is formed on the bottom of the gate hole; the sacrificial oxide layer is then etched away, and the metal oxide semiconductor field effect transistor is heated. -13 · The size of the paper method uses the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ m i ί I I, (please read the precautions on the back before filling this page)