TW498663B - Low distortion digital power amplification method and system therefor - Google Patents
Low distortion digital power amplification method and system therefor Download PDFInfo
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經濟部智慧財產局員工消費合作社印製 498663 A7 _ B7 五、發明說明(1 ) 本發明係有關於一種低失真之功率放大方法及其系統 ,特別疋指一種能消除訊號因相位偏移不對稱所產生之相 位雜訊及系統内部雜訊的低失真之數位功率放大方法及其 系統者。 按,一般數位功率放大器主要係以一功率切換電路放 大輸入訊號,而目前係存在有單邊(以“外^⑭幻切換電 路及雙邊(H-bridge)切換電路兩種功率切換電路,且其中 之切換動作係以電晶體作為主要開關元件。若假設一般電 晶體係為一理想元件時,則輸入該數位功率放大器之脈波 寬度調變(PWM)訊號經過其功率切換電路之開關元件切換 後’應該會被很真實地放大,然後經由一低通濾、波器濾除 高頻成分後,應可於該數位功率放大器之輸出端得到一完 整之低頻放大訊號。然而,在真實的電路中並不可能產生 這樣的完整訊號,這是因為一般數位功率放大器的供應電 源會產生漣波(ripple),而做為其開關元件之電晶體並非 理想元件,且當開關元件交替ON、0FF切換以進行訊號放 大時,其ON、OFF之切換時序並不能完全配合,以及負載 效應等種種因素’都會在數位功率放大器中產生許多雜訊 ,使得輸入PWM訊號經過數位功率放大器放大後並無法得 到一完整之放大訊號,而造成了輸出訊號的嚴重失真。 因此’為消除上述因素所造成之雜訊,習知一種脈波 邊緣延遲(pulse edge delay)技術被提出。請參照第一圖 所示,係為國際公告號碼W098/44626,國際申請案穿 PCT/DK/00133號所揭露之一種數位功率放大器的概要電路 第3頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) --------訂 I! I---. 498663 絰濟部智慧財產局員工消費合作社印製 頁 A7 五、發明說明(2 方塊圖,該數位功率放大1 . ^ , t 15 1主要包括一修正單元n、 ‘一功率切換單元12、及一誤#_ 一 為差處理早兀>13,其中該修正 單元1 1係分別與該功率切拖蒂― 千丨刀換早7G 12及誤差處理單元13 連接,且該修正單元11係供一时、士 # Η 于供脈波調變訊號Vi輸入,並 根據該誤差處理單元13提供夕 ^ v, 代供之一誤差訊號Ve,將脈波調 變訊號Vi之各脈波邊緣相對M^ • 豕相對延遲,以對應調整每一脈波 之寬度後’輸出一修正後的脈油,傲 无幻脈波調變訊號Vc至該功率切 β奐單元1 2,使經由功率切換單元〗 、平兀適當放大後,產生一 輸出訊號Vo’並由功率切換置弄 卞μ吳早兀丨2將輸出訊號V〇回授 至誤差處理导兀13中,缚出命认 左由與輸入訊號Vi進行比較處理 後,產生一新的誤差訊號Ve误5收X时- v e运至修正早元n中,以調整 下一輸入脈波調變訊號Vi之脈波寬度。 因此,習知數位功率放*哭,冰m〆 千双大裔1使用脈波邊緣延遲方法 ’根據回授之誤差訊號Ve,適冬,款私x 1b 過田調整輸入脈波調變訊號v i 之各脈波寬度,即可達到相對抑制釤你^^ ^ _ w玎仰制數位功率放大器内部雜 ^訊之目的,以得到一較完整之輸出訊號波形。 然而,上述習知雖具有消除螯价^安 负月除數位功率放大器所造成雜 訊之功效,但是其在消除該等雜訊的過程中,卻也產生了 、另一相位雜訊。 K 請參照第二圖所示,係為輸入數位功率放士时, 刀午敌大态1之脈 波調變訊號V i波形與經過修正單元n纲敕^ 1調整脈波寬度後輸 出之修正訊號Vc波形,由圖中可以看至彳, 孩修正訊號Vc 的每一脈波之中心位置與輸入訊號Vi的备 丄 旳母—相對脈波之 中心位置之間的距離(相位差△ 1、△ 2及△ 3 w )係各不相同 第 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) Μ--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 498663 A7Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498663 A7 _ B7 V. Description of the Invention (1) The present invention relates to a low-distortion power amplification method and system, and particularly to a method that can eliminate asymmetrical signals due to phase shift Low-distortion digital power amplification method of generated phase noise and internal noise of the system and a system thereof. According to the general, digital power amplifiers mainly use a power switching circuit to amplify the input signal. At present, there are two types of power switching circuits, which are unilateral (using "outside magic switching circuits and bilateral (H-bridge) switching circuits, and of which The switching action is based on the transistor as the main switching element. If it is assumed that the general transistor system is an ideal element, the pulse width modulation (PWM) signal of the digital power amplifier is input through the switching element of the power switching circuit. 'It should be amplified very realistically, and then through a low-pass filter and wave filter to remove high-frequency components, a complete low-frequency amplified signal should be obtained at the output of the digital power amplifier. However, in a real circuit It is not possible to generate such a complete signal, because the power supply of a general digital power amplifier generates ripples, and the transistor used as its switching element is not an ideal element, and when the switching element is turned ON alternately, 0FF is switched to When the signal is amplified, the switching timing of its ON and OFF cannot be fully matched, and various factors such as load effect will be in the A lot of noise is generated in the bit power amplifier, so that the input PWM signal cannot get a complete amplified signal after being amplified by the digital power amplifier, which causes serious distortion of the output signal. Therefore, in order to eliminate the noise caused by the above factors, Xi It is known that a pulse edge delay (pulse edge delay) technology is proposed. Please refer to the first figure, which is a digital power amplifier disclosed in International Publication No. W098 / 44626 and International Application No. PCT / DK / 00133. Outline Circuit Page 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -------- Order I! I- -. 498663 Printed page A7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2 Block diagram, the digital power amplification 1. ^, t 15 1 mainly includes a correction unit n, 'a power switching unit 12 、 和 一 ERROR # _ First is the difference processing early stage> 13, where the correction unit 11 is connected to the power cutting system ― Qian 丨 tool change early 7G 12 and the error processing unit 13 respectively, and the correction unit 11 is Temporary士 # 输入 is input to the pulse modulation signal Vi, and according to the error processing unit 13, ^ v, which is one of the error signals Ve, and the pulse wave modulation signal Vi is relative to each pulse edge M ^ •豕 The relative delay is to output a corrected pulse oil after adjusting the width of each pulse wave. The pulse signal Vc of the magic wave is adjusted to the power cut β 奂 unit 1 2 so that the power is passed through the power switching unit. After proper amplification, an output signal Vo ′ is generated and is switched by the power switch. Wu Wuwu 2 returns the output signal V0 to the error processing guide 13 and binds the input signal Vi to the input signal Vi. After the comparison process, a new error signal Ve is generated when the error is 5 and X is received -ve is transported to the modified early element n to adjust the pulse width of the next input pulse modulation signal Vi. Therefore, the conventional digital power amplifier * is crying. Bing m〆qian double generation 1 uses the pulse wave edge delay method 'according to the feedback error signal Ve, suitable for winter, models private x 1b crossing the field to adjust the input pulse wave modulation signal vi The width of each pulse wave can achieve the relative suppression of the internal noise of the digital power amplifier, so as to obtain a more complete output signal waveform. However, although the above-mentioned knowledge has the effect of eliminating the noise caused by the chelation value and the negative month of the digital power amplifier, in the process of eliminating such noise, it also generates another phase noise. K Please refer to the second figure, which is the correction of the pulse wave modulation signal V i waveform of the knife state 1 when the digital power is entered and the output is adjusted by the correction unit n outline 单元 ^ 1 The waveform of the signal Vc can be seen from the figure, and the distance between the center position of each pulse wave of the signal Vc and the center of the input signal Vi—the relative position of the pulse wave (phase difference △ 1, △ 2 and △ 3 w) are different. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). M -------- ^ --------- (Please read the precautions on the back before filling this page) 498663 A7
五、發明說明(3 ) 經濟部智慧財產局員工消費合作社印製 訊號Vc中 開後,會出 提供一種低 除相位雜訊 提供一種低 功率放大系 真放大訊號 率放大方法 根據該比較 生一控制訊 度調變訊號 切換級之修 置與輸入之 間具有一預 系統雜訊之 率放大系統 切換單元、 輸入訊號轉 :該處理單 修正單元連 換單元輸出 元中;該修 ,而此等不 訊,使得輸 諧波雜訊, 因此, 功率放大方 雜訊之功效 再者, 功率放大方 完整之放大 緣是, 括下列步驟 一功率切換 控制訊號, 之寬度及相 得該修正訊 變訊號的各 ,藉此,達 再者, 一調變單元 元,其中, 寬度調變訊 與上述調變 調變單元輸 號,產生一 相同之相位 出訊號 Vo 造成輸出訊 本發明之主 法及其系統 者。 本發明之另 法及其系統 訊號,以達 本發明低失 :提供一比 級輸出之回 對應調整輸 位,以產生 號的每一脈 相對脈波之 到消除相位 本發明低失 、一處理單 該調變單元 號,並產生 單元、功率 出之比較訊 控制訊號輸 差將於輸出 經由頻譜展 號失真。V. Explanation of the invention (3) After the printed signal Vc is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it will provide a low phase noise reduction method, a low power amplification system, true amplification signal rate amplification method, and a control method based on the comparison. There is a pre-system noise rate amplification system switching unit between the modification and input of the modulation signal switching level, and the input signal is transferred: the processing unit correction unit is connected to the output unit of the switching unit; the repair, but these are not Therefore, the noise of the power amplifying side is effective. The complete amplifying edge of the power amplifying side is as follows, including the following steps: the power switching control signal, the width of the signal and the phase of the modified signal. Each, by this means, a modulation unit element, in which the width modulation signal and the above-mentioned modulation modulation unit input signals generate a same phase output signal Vo and cause the output signal of the main method of the present invention and its system. . The other method of the present invention and the system signal thereof achieve the low loss of the present invention: providing a ratio of a level output correspondingly adjusting the input bit to generate a phase of each pulse relative to the pulse wave to eliminate the phase. The modulation unit number alone, and the comparison signal of the unit and power output control signal will be distorted by the spectrum display number.
以達到消 一目的乃在 ’使該數位 到輸出低失 真之數位功 較訊號,並 授訊號,產 入之脈波寬 一輸入功率 波之中心位 中心位置之 雜訊及抑制 真之數位功 元、一功率 ,係可將一 一比較訊號 切換單元及 號及功率切 入該修正單 第5頁 造成相位雜 現不必要的 失真之數位 及系統内部 失真之數位 統可輸出更 之功效者。 ’主要係包 訊戒及一由 號;根據該 的每一脈波 正訊號,使 脈波寬度調 期之相位差 功效者。 ’主要包括 及一修正單 換成一脈波 70 ’係分別 接,以根據 之一回授訊 正單元,係 II.--------r — MW--------訂---------線-#- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 498663 A7 B7 五、發明說明(4 ) 供上述調變單元之脈波寬度調變訊號輸入,並根據處理單 .元輸入之控制訊號,對應調整該脈波寬度調變訊號之每一 •脈波的寬度及相位,以產生一修正訊號輸入該功率切換單 元,使得該修正訊號之每一脈波的中心位置與脈波寬度調 變訊號之各相對脈波的中心位置之間具有一預期之相位差 ’藉以達到消除相位雜訊及系統雜訊之功效者。 為期對於本發明之目的、功效及構造特徵有更詳盡明 的瞭解’茲舉較佳實施例並配合圖式說明如后: 首先,請參閱第三圖及第十圖所示,係本發明一較佳 實施例低失真之數位功率放大方法的概要流程示意圖及數 位功率放大器中之一功率切換級3 3的内部電路示意圖。 且為消除上述習知因相位偏移不一致所造成之相位雜訊, 該方法係針對一脈波寬度調變訊號的每一脈波進行適當之 相位及寬度調整,使經由數位功率放大器之功率切換級3 3 進行放大後’可獲得一低失真之輸出訊號;請參閱第三圖 所示’該方法係包括下列步驟: ’ 首先,提供一比較訊號Vm,並根據該比較訊號Vm 及一由數位功率放大器之功率切換級33輸出之回授訊號 _Vf,產生一控制訊號Vc ; — 接著’根據該控制訊號Vc,對應調整輸入數位功率 放大器之脈波寬度調變訊號PWM的每一脈波之寬度及相 位’以產生一輸入該功率切換級3 3之修正訊號V e,使得 該修正訊號Ve的每一脈波之中心位置與輸入之脈波寬度 調變訊號PWM的各相對脈波之中心位置之間具有一預期 第6頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------I----I I · I I I---1 訂·! I!--線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 498663 A7 ____ B7 五、發明說明(5 ) 之相位差。 其中’在本實施例中,該脈波寬度調變訊號PWM係 分成CH —R及CH —L兩道訊號,且輸入該功率切換級33 之修正訊號Ve係分成R — U、R —d、L一 u及L —d四道訊號, 則由該功率切換級33輸出之回授訊號Vf,如第九圖所示 ’實際上係為該修正訊號V e經過功率切換級3 3放大之放 大訊號Vol、Vo2、ν〇3及Vo4相減,即Vo2與v〇4(或者 Vo 1與Vo 3)相減所得之差值,再除以一比例常數κ所得 出。而該比較訊號Vm,如第三圖所示,則根據系統設計 之不同需求,可為該脈波寬度調變訊號PWM之CH —R及 CH—L兩道訊號相減後所得之差值訊號,或者是修正訊號 Ve之R — U及L —u(或R —d及L_d)相減後所得之差值訊號。 則該控制訊號Vc可由該比較訊號vm與回授訊號vf相減 而獲得,但因為經過功率切換級33放大後之回授訊號Vf 内係含有複雜之雜訊,故由比較訊號Vm與回授訊號Vf 相減所得之差值訊號,實際上係為一内含許多雜訊之寬頻 類比訊號,因此,必須將該差值訊號經過一處理程序,使 經由低通濾波及取樣保持步驟後,可得到僅包含有低頻成 分之控制訊號Vc,且該控制訊號Vc可相對於輸入之脈波 寬度調變訊號PWM的每一脈波,產生一相對位移量 為脈波數1,2,3…)。此外,於本實施例中,係提供有—表 考訊號Vmax,其可產生一相對之參考位移量Amax,因此 ’本發明係根據該控制訊號Vc,將該脈波寬度調變訊號 PWM的每一脈波相對位移一 △ max- △ n/2距離(n:=脈波數 第7頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---r--------------------訂---------^ —Awl (請先閱讀背面之注意事項再填寫本頁} 498663 ¾齊即ϋ曰慧时轰笱員工消費合作杜印製 A7 五、發明說明(6 ) 1,2,3···) ’接著再將每一脈波對應調整一“如脈波數 1,2,3···)寬度,則會使得因此而產生之修正訊號的每一 脈波之中心位置與輸入之脈波寬度調變訊號pwM的每一相 對脈波之中心位置之間相差一預期之相位差,且該預期之 相位差在不受系統其他雜訊干擾及實現時之誤差的情況下 ,係為: • Δ max-Δ η/2 +Δ η/2=Δ max 所乂由上式可以知知,雖然輸入之脈波寬度調變訊 號酬的每-脈波所欲調整的△❿味以)值皆不相 同,但其每一脈波經過位移△贿七。及寬度調整“ 之後’則會使產生之修正訊號Ve相對於脈波寬度調變訊 號酬之相位差幾乎相同(即相當於Δπ^χ),而使得輸出 訊號Μ每-脈波相對於輸入訊號(脈波寬度調變訊號 PWM)的每一脈波係相差一相當於△ max之相位差,且此 I个〜響系統之SNR(訊號雜訊比),因此 龜不但於抑制數位功率放大器内部雜訊之同時,亦一併消 亀了可能產生之相位雜訊,使輸出訊號V。之失真降至最 此外在此值得/主思的是,本發明對於脈波寬度調變 ,號PWM的位移及寬度之調整順序是可以對調的,亦即 ,可以先對脈波寬度調變訊號pwM的每一脈波先做寬度 調整後,再調整其位移距離,或者相移及寬度調整同時進 行,所得到的相位雜訊之抑制效果和上述先調整位移,并 調整寬度之方法是相同的。 第8頁 表紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公楚) ---------------------1 訂*II-----I (請先閱讀背面之注意事項再填寫本頁) 498663 A7 ---—_ B7 五、發明說明(7 ) (請先閱讀背面之注意事項再填寫本頁) 另外’本實施例中所提供之參考訊號Vmax,係根據 系統所欲調整脈波的最大位移距離而設定,其可能是所調 整之脈波中的最大位移距離之相對訊號,或者是一可產生 大於該最大位移距離之參考距離的參考訊號。 接著,以下將針對實現上述方法之一低失真數位功率 放大系統做詳細描述。 首先,請參照第四圖所示,係本發明低失真數位功率 放大系統之一較佳實施例的電路方塊圖,且於本實施例中 ’係以H-bridge架構之低失真數位功率放大系統3做為 說明例子,其中系統3主要包括有一調變單元3 1、一修 正單元32、一功率切換單元33、及一處理單元34;其中 經濟部智慧財產局員工消費合作社印製 該調變單元31,係與上述修正單元32連接,用以將 一輸入訊號(可能是類比訊號或數位訊號)轉換成一脈波寬 度調變(PWM)訊號30後,輸入修正單元32中;且在本實 施例中,調變單元31係將該PWM訊號30分成CH —R及 CH—L兩道訊號輸出,而其調變方法如第五圖所示,係將 輸入訊號,例如一脈波編碼調變訊號PCM,分成PCM及 -PCM(即PCM乘以-1)兩道訊號,然後分別與一三角波比 車交調變後’即可得出CH一R及CH —L兩道不同的pwM調 變訊號分別輸入修正單元32中。 該處理單元34,係分別與上述調變單元31、功率切 換單元33及修正單元連接’其包括有兩個減法器341、342 、一低通濾、波器3 4 3、及一取樣保持電路3 4 4 ;其中,該 第9頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 498663 A7 B7 五、發明說明(8 ) 減法器341係取出調變單元31輸出之兩道脈波調變訊號 CH — R及CH — L輸入進行相減,以得出一比較訊號Vm, •該第二減法器342係供該比較訊號Vm及一由該功率切換 單元33輸出之一回授訊號Vf進行相減,以得出一誤差訊 號3 5,但因為該回授訊號V f係為經過功率切換單元3 3 放大後之差值訊號’其内含有複雜之雜訊,故由比較訊號 —Vm與回授訊號Vf相減所得之誤差訊號35,實際上係為 _ 一内含許多雜訊之寬頻類比訊號,因此需將該誤差訊號35 送入該低通遽波器343渡除高頻訊號後,再經過取樣保持 電路344產生對應之控制脈波,即可得到一具有低頻成分 之控制訊號Vc,並送入上述修正單元32中。 此外,在此值得一提的是,當此數位放大系統是針對 較低頻訊號進行放大,而須用到低頻訊號時,則該低通廣 波器343必須具有極低之截止頻率,以濾除高頻訊號,使 僅留下較低頻訊號(例如音頻,則需約22kHz左右),因為 若低通瀘、波器之頻寬很寬時,其取樣頻率就必須要很高, 則會有a 1 i a s (假像頻率)的產生,但是於實作上,具有乾、 低截止頻率之低通濾波器3 4 3的計設成本卻又偏高。因此 κ,為降低設計低通濾波器之成本,於本實施例中,該产理 -單元34之低通濾波器343及取樣保持電路344係可由一 具有較高截止頻率之低通濾波器343,串連一超取樣電路 345及一分樣器(decimator)346所取代,如第六圖所示 而形成一具有一極低截止頻率之等效低通濾波器電路,其 作法係將輸入低通濾波器343 ’之誤差訊號35濾除一部分 第10頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----I----------II--—訂-------I ·線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 498663 A7 B7 五、發明說明(9 ) 高頻成分後,送入超取樣電路345中,以例如,μ倍取樣 速度對誤差訊號35·進行取樣後’再經過一分樣器346以 1/Μ倍(Μ=1,2,3._·正整數)對誤差訊號35進行取樣,即可 得到該具有低頻成分之控制訊號V c,同時,因為該超取 樣電路 345 係為一離散訊號處理(discrete signal processing)器,其具有補償整體頻率響應之能力,故亦可 用來控制系統所欲之頻譜響應。 該修正單元32,請參照第四圖所示,係根據處理單 元34輸入之控制訊號Vc ’對應調整輸入之脈波寬度調變 訊號3 0的每一脈波之寬度及相位,以產生一修正訊號Ve 輸入該功率切換單元33中。請參照第七圖所示,係為修 正單元32之内部構造示意圖,該修正單元32主要包括有 兩個分別供脈波寬度調變訊號CH-R及CH_L輸入之相移 電路321、兩對應串接於該二相移電路321之後的脈波寬 度調整電路3 22、及一提供一參考訊號Vmax之參考訊號 產生器324,且該參考訊號Vmax可相對產生一參考修正 量△ max。其中,當前述控制訊號Vc輸入時,因其訊號 有正有負,故會先經過一比較電路323將控制訊號Vc轉 成正值後,乘以一與系統之修正係數K c相關之增益值(例 如3000),再與一基本量(2e·9)相乘後產生一適當放大之調 整訊號Vc’,且該調整訊號Vc’可相對於輸入之PWM訊 號30(CH-R及CH-L)的每一脈波產生一相對修正量△nCn。 脈波數1,2, 3· ·)。然後,該調整訊號Vc’分成兩路,一路 經由一乘法器325乘以1/2後,輸入一減法器326中與參 第11頁 本紙張尺度適用中國國寥標準(CNS)A4規格(210 X 297公釐) --1--------*----------訂---------線丨 (請先閱讀背面之注意事項再填寫本頁) 498663 ' A7 B7 五、發明說明(10) 考訊號Vmax進行相減,得到一相移控制訊號Vmax-l/2Vc ,以相對脈波調變訊號3 0之每一脈波產生一相對位移量 △ max-1/2 △ n(n =脈波數1,2, 3···),則如第八圖所示,會 使輸入修正單元32之脈波調變訊號30的每一脈波 (n=l,2, 3…)分別對應位移△ max-1/2 △ n(n = l,2, 3…)’而 得到如第八圖中所示之第二個波形;同時,調整訊號V c ’ -由另一路徑輸入該脈波寬度調整電路322中’使由相移電 路321輸出之PWM訊號30,的每一脈波(n = l, 2, 3··.)之寬度 被相對調整一修正量A n(n = l,2, 3…),則得到如第八圖中 所示之第三個波形(即修正訊號V e)。 而為更進一步詳細說明上述相移及寬度調整的動作原 理,請參照第九圖所示,假設圖(a)是在週期T s内輸入修 正單元32的一脈波寬度調變訊號,則如圖(b)所示,一斜 波產生器即會根據該脈波寬度調變訊號的上升緣及下降緣 ,分別產生角度大小相同的一上升斜波,藉此’如圖(b) 及圖(c)所示,當輸入修正單元32之控制訊號Vc為零時 鲁,則使上升斜波對應產生一 △ max相移量,使該脈波寬度 調變訊號僅向後移動一 △ max的位移量;而如圖(b)及圖(d) 、所示,當輸入修正單元32之控制訊號Vc為一正值時,則 J吏上升斜波對應產生一 △ 1相移量,而使該脈波寬度調變 訊號向後延遲△ max-△ 1相移量,並同時使其前後緣向外 拉開Δι的寬度;反之,如圖(b)及圖(e)所示,當輸入修正 單元3 2之控制訊號V c為一負值時,則使上升斜波對應產 生一 Δ2相移量,而使該脈波寬度調變訊號向後延遲△ max - 一 第12頁 本紙張尺度適中國國家標準(CNS)A4規格(210 X 297公釐) -------------裝-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 498663 A7 B7 五、發明說明(11 ) △ 2相移量,並同時使其前後緣向内縮入△ 2的寬度,如此 ’即完成了脈波寬度調變訊號的位移及寬度調整動作。 所以,由第八圖中可以看出,輸入之脈波調變訊號3 〇 經過修正單元32.之相移電路321及寬度調整電路322, 根據控制訊號V c適當調整其脈波之相位及寬度後,在不 受到系統其他雜訊干擾的情況之下,所產生之修正訊號Ve 的每一脈波之中心位置與該PWM訊號30的每一相對脈波 之中心位置之間具有一相當於△ max的預期之相位差,且 該預期之相位差(△ max)在不考慮系統即時修正之因素時 並不會影響系統之SNR(訊號雜訊比)。 而該功率切換單元3 3,係對上述修正訊號Ve進行放 大,以產生一輸出訊號Vo推動負載,並產生輸入處理單 元34之回授訊號Vf。請參照第十圖所示,係為該功率切 換單元3 3之内部電路示意圖,其中在本實施例中,由修 正單元32輸出之修正訊號Ve係分成R —u、R_d、L —u及 L_d四道訊號分別輸入功率切換單元33,而分別經由切換 元件332、333、3 34、3 35適當放大後,分別輸出一放大 訊號(Vol、Vol、Vo3及Vo4),並經由兩組差動電路336 、3 37配合一低通濾波器338進行差動低通濾波後,產生 一輸出訊號Vo推動一負載331,而該回授訊號vf則為該 放大訊號Vo2與Vo4相減後,除以一比例常數K(適當降 低放大訊號之電壓值)所得到之差值訊號。 故,藉由將該回授訊號Vf輸入處理單元34中’使與 輸入端之比較訊號Vm相減並產生一控制訊號Vc回授至 第13頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公ίΤ (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 498663 A7 B7 五、發明說明(12) 修正單元32中,調整輸入之PWM訊號30之脈波相位及 寬度,使得產生之修正訊號Ve輸入功率切換單元33進行 訊號放大後’可使輸出訊號Vo之失真降至最低。因此, 經由上述脈波相位及寬度調整動作,確實可消除輸入訊號 3 0因相移所可能產生之相位雜訊及系統内部所產生之雜 訊,使數位功率放大系統3能夠輸出高傳真之放大訊號。 - 因此,根據上述低失真數位功率大系統3,係可得到 •如第十一圖所示之一低頻等效線性模組,其中: X係為輸入系統3之修正單元32的PWM訊號之低頻 成分訊號; nl係為數位功率放大系統3之内部元件不匹配 (mismatch)、非理想、近似假設及相位不對稱等因素所產 生之雜訊; n2係為數位功率放大系統3之功率切換單元33為非 線性、非理想、負載效應、以及供應電源上之漣波等因素 等所造成之雜訊; _ y係為該功率切換單元33輸出之放大訊號; 且令 x,=xe-jwA /2 s Kc,= Kc e-jwA /2 . 又 Kp x,+ {H(w)Kcx,-[yH(w)Kc,]/K}Kp + z = y 其中 z=nlKp+n2 則由該等效模組可以求得 STF=y/x | w=0=[Kp+H(w)KcKp]e(-jWA /2) / [l+H(w)Kc,Kp/K] NTF = y/w| x = 0=i/[i+H(w)Kc5Kp/K] 第14頁 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公釐) ------------I -------1 訂 --- -----I (請先閱讀背面之注意事項再填寫本頁) 498663 A7 B7 五、發明說明(13) 其中, (請先閲讀背面之注意事項再填寫本頁) △ /2是每一 Ts週期内修正訊號之中心位置和輪入脈 波寬度調變訊號的中心位置之時間差。In order to achieve the purpose of eliminating the noise, the digital power output signal with low distortion is output and the signal is given. The pulse width produced is the center noise of the center position of the input power wave and the true digital power is suppressed. A power is a digital one that can compare the signal switching unit and the signal and power into page 5 of the correction sheet, causing the digital distortion of the phase miscellaneous and the digital distortion of the system's internal distortion can output more effective. ’Mainly include a signal ring and a signal; according to the positive signal of each pulse, the phase difference effect of the pulse width is adjusted. 'Mainly includes and a correction unit is replaced by a pulse 70' are connected separately to feedback the positive unit according to one, which is II .-------- r — MW -------- Order --------- Line-#-(Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 498663 A7 B7 5 4. Description of the invention (4) For the pulse width modulation signal input of the aforementioned modulation unit, and according to the control signal of the processing unit, the corresponding adjustment of each pulse width modulation signal • the width and phase of the pulse wave To generate a correction signal to input the power switching unit, so that there is an expected phase difference between the center position of each pulse wave of the correction signal and the center position of each relative pulse wave of the pulse width modulation signal, thereby achieving The effect of eliminating phase noise and system noise. In order to have a more detailed and clear understanding of the purpose, effects and structural features of the present invention, the preferred embodiment is described below in conjunction with the drawings. First, please refer to the third and tenth drawings, which are the first embodiment of the present invention. The schematic flow chart of the low-distortion digital power amplification method of the preferred embodiment and the schematic diagram of the internal circuit of one of the power switching stages 33 in the digital power amplifier. And in order to eliminate the phase noise caused by the inconsistent phase offset mentioned above, the method is to adjust the phase and width of each pulse of a pulse width modulation signal appropriately, so that the power through the digital power amplifier is switched. Level 3 3 After amplification, 'a low-distortion output signal can be obtained; please refer to the third figure' This method includes the following steps: 'First, a comparison signal Vm is provided, and the comparison signal Vm and a digital The feedback signal _Vf output from the power switching stage 33 of the power amplifier generates a control signal Vc; — Then, according to the control signal Vc, each pulse of the pulse width modulation signal PWM of the input digital power amplifier is adjusted correspondingly. Width and Phase 'to generate a modified signal Ve input to the power switching stage 3 3 such that the center position of each pulse wave of the modified signal Ve and the center of each relative pulse wave of the input pulse width modulation signal PWM There is an expectation between the positions on page 6. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ I ---- II · II I --- 1 Order ·! I!-Line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498663 A7 ____ B7 V. Phase difference of the invention description (5). Among them, in this embodiment, the pulse width modulation signal PWM is divided into two signals CH-R and CH-L, and the correction signal Ve inputted into the power switching stage 33 is divided into R-U, R-d, L a u and L — d four signals, then the feedback signal Vf output by the power switching stage 33, as shown in the ninth figure, 'is actually the correction signal V e amplified by the power switching stage 3 3 The signals Vol, Vo2, Vo3, and Vo4 are subtracted, that is, the difference between Vo2 and Vo4 (or Vo 1 and Vo 3) is subtracted, and then divided by a proportionality constant κ. The comparison signal Vm, as shown in the third figure, can be the difference signal obtained by subtracting the two signals of CH — R and CH — L of the pulse width modulation signal PWM according to different requirements of the system design. , Or the difference signal obtained by subtracting the R — U and L — u (or R — d and L_d) of the correction signal Ve. Then the control signal Vc can be obtained by subtracting the comparison signal vm from the feedback signal vf, but because the feedback signal Vf amplified by the power switching stage 33 contains complex noise, the comparison signal Vm and the feedback The difference signal obtained by subtracting the signal Vf is actually a wideband analog signal containing a lot of noise. Therefore, the difference signal must be processed through a low-pass filtering and sample-and-hold step. A control signal Vc containing only low-frequency components is obtained, and the control signal Vc can generate a relative displacement amount for each pulse wave of the input pulse width modulation signal PWM as a pulse wave number of 1, 2, 3, etc.) . In addition, in this embodiment, a table test signal Vmax is provided, which can generate a relative reference displacement Amax. Therefore, the present invention is based on the control signal Vc, each time the pulse width modulation signal PWM is adjusted. The relative displacement of a pulse wave is △ max- △ n / 2 distance (n: = pulse wave number. Page 7 This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- r --- ----------------- Order --------- ^ --Awl (Please read the notes on the back before filling in this page} 498663 Shi Hongzheng Employees ’Consumer Cooperation Du printed A7 V. Description of the Invention (6) 1,2,3 ···) 'Then adjust each pulse wave correspondingly, such as the pulse wave number 1,2,3 ··· ) Width, the center position of each pulse wave of the resulting modified signal and the center position of each relative pulse wave of the input pulse width modulation signal pwM differ by an expected phase difference, and the The expected phase difference is not affected by other noise in the system and the error during implementation, as follows: • Δ max-Δ η / 2 + Δ η / 2 = Δ max The above equation can be known, although Enter it The value of △ ❿ to be adjusted for each pulse of the wave width modulation signal is different, but each pulse is shifted by △ 7. And the width adjustment “after” will cause the correction signal to be generated. The phase difference of Ve relative to the pulse width modulation signal is almost the same (that is, equivalent to Δπ ^ χ), so that the output signal M per pulse is relative to each pulse of the input signal (pulse width modulation signal PWM). The phase difference of the wave system is equivalent to the phase difference of △ max, and the SNR (signal-to-noise ratio) of this I ~ system, so the turtle not only suppresses the internal noise of the digital power amplifier, but also eliminates the possibility of The phase noise makes the output signal V. The distortion is reduced to the maximum. In addition, it is worthwhile / thinking that, for the pulse width modulation, the present invention can adjust the displacement and width of the PWM signal in the order of adjustment, that is, the pulse width modulation signal can be adjusted first. After adjusting the width of each pulse wave of pwM, then adjust its displacement distance, or phase shift and width adjustment are performed at the same time. The suppression effect of the phase noise obtained is the same as the method of adjusting the displacement and adjusting the width described above. . The paper size on page 8 applies to China National Standard (CNS) A4 (210 X 297 cm) --------------------- 1 Order * II --- --I (Please read the notes on the back before filling this page) 498663 A7 -----_ B7 V. Description of the invention (7) (Please read the notes on the back before filling this page) In addition 'In this embodiment The provided reference signal Vmax is set according to the maximum displacement distance of the pulse wave to be adjusted by the system, which may be a relative signal of the maximum displacement distance in the adjusted pulse wave, or a signal that can generate a value greater than the maximum displacement distance. Reference signal for reference distance. Next, a detailed description of a low-distortion digital power amplifier system implementing one of the above methods will be described below. First, please refer to the fourth figure, which is a circuit block diagram of a preferred embodiment of the low distortion digital power amplifier system of the present invention, and in this embodiment, 'is a low distortion digital power amplifier system based on H-bridge architecture. 3 as an illustrative example, where the system 3 mainly includes a modulation unit 3 1, a correction unit 32, a power switching unit 33, and a processing unit 34; among them, the employee co-operative cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the modulation unit 31, which is connected to the above-mentioned correction unit 32, and is used to convert an input signal (may be an analog signal or a digital signal) into a pulse width modulation (PWM) signal 30, and then input the correction unit 32; and in this embodiment In the modulation unit 31, the PWM signal 30 is divided into two signals CH-R and CH-L, and the modulation method is shown in the fifth figure. The modulation signal is an input signal, such as a pulse-coded modulation signal. PCM, divided into PCM and -PCM (that is, PCM multiplied by -1) two signals, and then after intermodulation with a triangle wave ratio car, you can get two different pwM modulation signals: CH-R and CH-L. These are respectively input into the correction unit 32. The processing unit 34 is connected to the modulation unit 31, the power switching unit 33 and the correction unit, respectively. It includes two subtractors 341, 342, a low-pass filter, a wave filter 3 4 3, and a sample-and-hold circuit. 3 4 4; Of which, the paper size on page 9 applies to the Chinese National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 498663 A7 B7 5. Explanation of the invention (8) Subtraction The subtracter 341 takes two pulse wave modulation signals CH — R and CH — L input from the modulation unit 31 and subtracts them to obtain a comparison signal Vm. • The second subtractor 342 is used for the comparison signal Vm. And a subtraction of a feedback signal Vf output by the power switching unit 33 to obtain an error signal 35, but because the feedback signal Vf is a difference signal amplified by the power switching unit 3 3 'It contains complex noise, so the error signal 35 obtained by subtracting the comparison signal—Vm and the feedback signal Vf—is actually _ A wideband analog signal that contains a lot of noise, so the error signal needs to be 35 into the low-pass chirped wave filter 343 After the signal, and then through the corresponding sample and hold circuit 344 generates the control pulse, to obtain a low frequency component of a control signal Vc of, and fed to the correction unit 32. In addition, it is worth mentioning here that when this digital amplification system is designed to amplify lower frequency signals and low frequency signals are required, the low-pass wideband filter 343 must have a very low cut-off frequency to filter In addition to high-frequency signals, only lower-frequency signals are left (for example, audio, it needs about 22kHz), because if the low-pass signal and the bandwidth of the waveband are very wide, the sampling frequency must be very high. There is a 1 ias (artificial frequency), but in practice, the design cost of the low-pass filter 3 4 3 with dry and low cut-off frequency is relatively high. Therefore, in order to reduce the cost of designing a low-pass filter, in this embodiment, the low-pass filter 343 and the sample-and-hold circuit 344 of the production unit 34 can be a low-pass filter 343 with a higher cut-off frequency. Replaced in series by a supersampling circuit 345 and a decimator 346, as shown in the sixth figure, to form an equivalent low-pass filter circuit with a very low cut-off frequency. The method is to input low Pass filter 343 'The error signal 35 filters out a part of page 10 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----- I ---------- II --- Order ------- I · Line (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498663 A7 B7 V. Invention Description (9) High Frequency After the components, they are sent to the oversampling circuit 345, and the error signal 35 · is sampled at, for example, μ times the sampling speed ', and then passed through a decimator 346 at 1 / M times (M = 1, 2, 3._ · Positive integer) by sampling the error signal 35, the control signal Vc with a low frequency component can be obtained, and because the oversampling Path 345 is a discrete-time signal processing system (discrete signal processing) device, which has the ability to compensate for the overall frequency response, it is also desired to control the spectral response of the system. The correction unit 32, as shown in the fourth figure, adjusts the width and phase of each pulse wave of the input pulse width modulation signal 30 according to the control signal Vc ′ input by the processing unit 34 to generate a correction. The signal Ve is input to the power switching unit 33. Please refer to the seventh figure, which is a schematic diagram of the internal structure of the correction unit 32. The correction unit 32 mainly includes two phase shift circuits 321 and two corresponding strings for the input of the pulse width modulation signals CH-R and CH_L, respectively. The pulse width adjustment circuit 322 after the two phase shift circuits 321 and a reference signal generator 324 providing a reference signal Vmax, and the reference signal Vmax can relatively generate a reference correction amount Δmax. Among them, when the aforementioned control signal Vc is input, because its signal is positive or negative, it will first pass a comparison circuit 323 to convert the control signal Vc to a positive value, and then multiply it by a gain value related to the system's correction coefficient K c (Such as 3000), and then multiply it with a basic quantity (2e · 9) to generate an appropriately amplified adjustment signal Vc ', and the adjustment signal Vc' can be relative to the input PWM signal 30 (CH-R and CH-L Each pulse wave of) generates a relative correction amount ΔnCn. Pulse number 1, 2, 3 · ·). Then, the adjustment signal Vc 'is divided into two paths, one is multiplied by 1/2 by a multiplier 325, and then inputted into a subtractor 326 and referenced on page 11. This paper standard applies the China National Standard (CNS) A4 specification (210 X 297 mm) --1 -------- * ---------- Order --------- line 丨 (Please read the notes on the back before filling in this Page) 498663 'A7 B7 V. Description of the invention (10) Subtract the Vmax signal from the test signal to obtain a phase shift control signal Vmax-l / 2Vc. Each pulse wave with relative pulse wave modulation signal 30 generates a relative displacement. △ max-1 / 2 △ n (n = pulse wave number 1, 2, 3, ···), as shown in the eighth figure, each pulse of the pulse wave modulation signal 30 of the input correction unit 32 will be changed. Waves (n = 1, 2, 3 ...) correspond to displacements △ max-1 / 2 △ n (n = 1, 2, 3 ...) 'respectively to obtain the second waveform as shown in the eighth figure; at the same time, The adjustment signal V c '-is input to the pulse wave width adjustment circuit 322 from another path to cause each pulse wave (n = 1, 2, 3 ...) of the PWM signal 30, output by the phase shift circuit 321. The width is relatively adjusted by a correction amount A n (n = 1, 2, 3 ...), and the result is as shown in the eighth figure. Three waveform (i.e., the correction signal V e). To further explain the operation principle of the above-mentioned phase shift and width adjustment, please refer to the ninth figure. Assume that (a) is a pulse width modulation signal input to the correction unit 32 within the period T s. As shown in figure (b), a ramp wave generator will modulate the rising edge and falling edge of the signal according to the pulse width to generate a rising ramp wave with the same angle respectively, thereby 'as shown in (b) and Figure (C), when the control signal Vc of the input correction unit 32 is zero, the rising ramp wave correspondingly generates a △ max phase shift amount, so that the pulse width modulation signal moves backward by a △ max displacement. As shown in Figures (b) and (d), when the control signal Vc of the input correction unit 32 is a positive value, the rising ramp wave of J1 will generate a △ 1 phase shift amount, so that The pulse width modulation signal is delayed backwards by △ max- △ 1 phase shift amount, and at the same time the front and rear edges are pulled outward by the width of Δι; otherwise, as shown in (b) and (e), when the input correction unit When the control signal V c of 3 2 is a negative value, a rising ramp wave correspondingly generates a Δ2 phase shift amount, and The pulse width modulation signal is delayed backwards △ max-one page 12 The paper size is suitable for China National Standard (CNS) A4 (210 X 297 mm) ------------- installation- ------ Order --------- Line (Please read the precautions on the back before filling this page) 498663 A7 B7 V. Description of the invention (11) △ 2 phase shift amount, and make it at the same time The leading and trailing edges are retracted inwardly by a width of Δ2, so that the displacement and width adjustment of the pulse width modulation signal are completed. Therefore, it can be seen from the eighth figure that the input pulse wave modulation signal 3 passes through the phase shift circuit 321 and the width adjustment circuit 322 of the correction unit 32. The phase and width of the pulse wave are appropriately adjusted according to the control signal V c Then, without being disturbed by other noise of the system, there is an equivalent △ between the center position of each pulse wave of the correction signal Ve generated and the center position of each relative pulse wave of the PWM signal 30. The expected phase difference of max, and the expected phase difference (Δmax) does not affect the system's SNR (signal-to-noise ratio) when the factors of the system's immediate correction are not considered. The power switching unit 3 3 amplifies the above-mentioned correction signal Ve to generate an output signal Vo to drive the load, and generates a feedback signal Vf of the input processing unit 34. Please refer to the tenth figure, which is a schematic diagram of the internal circuit of the power switching unit 33. In this embodiment, the correction signal Ve output by the correction unit 32 is divided into R-u, R_d, L-u, and L_d. The four signals are respectively input to the power switching unit 33, and after being appropriately amplified through the switching elements 332, 333, 3 34, and 3 35, respectively, an amplified signal (Vol, Vol, Vo3, and Vo4) is output, and the two sets of differential circuits are passed through 336, 3 37 and a low-pass filter 338 perform differential low-pass filtering to generate an output signal Vo to drive a load 331, and the feedback signal vf is the amplified signal Vo2 and Vo4 are subtracted and divided by one The difference signal obtained by the proportionality constant K (appropriately reducing the voltage value of the amplified signal). Therefore, by inputting the feedback signal Vf into the processing unit 34, the comparison signal Vm is subtracted from the input terminal and a control signal Vc is generated to be returned to page 13. This paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297) (Please read the notes on the back before filling out this page) Order --------- Line · Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 498663 A7 B7 V. Invention Description (12 ) In the correction unit 32, the pulse phase and width of the input PWM signal 30 are adjusted so that the generated correction signal Ve input power switching unit 33 performs signal amplification to minimize the distortion of the output signal Vo. Therefore, through the above, The pulse wave phase and width adjustment action can indeed eliminate the phase noise and internal noise generated by the input signal 30 due to phase shift, so that the digital power amplifier system 3 can output the high-fax amplified signal.-Therefore According to the above-mentioned low-distortion digital power large system 3, one can obtain a low-frequency equivalent linear module as shown in the eleventh figure, where: X is the low level of the PWM signal of the correction unit 32 of the input system 3. Component signal; nl is noise generated by mismatch, non-ideal, approximate assumption and phase asymmetry of internal components of digital power amplifier system 3; n2 is power switching unit 33 of digital power amplifier system 3 Noise caused by factors such as non-linearity, non-idealities, load effects, and ripples on the power supply; _ y is the amplified signal output by the power switching unit 33; and let x, = xe-jwA / 2 s Kc, = Kc e-jwA / 2. And Kp x, + {H (w) Kcx,-[yH (w) Kc,] / K} Kp + z = y where z = nlKp + n2 is determined by The effect module can find STF = y / x | w = 0 = [Kp + H (w) KcKp] e (-jWA / 2) / [l + H (w) Kc, Kp / K] NTF = y / w | x = 0 = i / [i + H (w) Kc5Kp / K] Page 14 This paper size is applicable to China National Standard (CNS) A4 (21〇χ 297 mm) -------- ---- I ------- 1 Order --- ----- I (Please read the notes on the back before filling this page) 498663 A7 B7 V. Description of the invention (13) Among them, (Please (Read the precautions on the back before filling in this page) △ / 2 is the center position of the correction signal and the turn-in pulse width modulation signal in each Ts period The time difference.
Kc係為系統3藉以調整脈波寬度調變訊號之脈波寬 度時的一重要參考係數,其係修正訊號Ve減脈波寬度調 變訊號PWM,再除以控制訊號Vc後所得到之一修正係數 ’而Kc值之推導則如第十二圖所示之例子,其中,假設 圖(a)係經過處理單元34以每秒取樣一次後輸出之控制訊 號Vc ’且若僅考慮其低頻成分(例如音頻約22kHz),則該 控制訊號Vc可等效於圖(b)所繪之波形,並可求得該波形 之複利葉表示式為: [a· eJ“ + a· e”01]ri· [sir^TTfrO / 7rf7:i] =?(2a)r ! · [sin(7r fr x) / π fr x]....................(1) 而修正訊號Ve減經過△ /2位移後之脈波寬度調變訊 號PWM之結果,例如圖(c)所示之波形,則可由該波形求 得其複利葉表示式為: 4C · r 2[sin(7r fr 2) / 7Γ fz* 2]............................(2) 則可由上式(1)(2)求得 經濟部智慧財產局員工消費合作社印製Kc is an important reference coefficient when system 3 adjusts the pulse width of the pulse width modulation signal. It is a correction obtained by modifying the signal Ve to reduce the pulse width modulation signal PWM and dividing it by the control signal Vc. The coefficient 'and the derivation of the Kc value are as shown in the example in Fig. 12, where it is assumed that the graph (a) is the control signal Vc' output after the processing unit 34 samples once per second and if only its low frequency components are considered ( For example, the audio frequency is about 22kHz), the control signal Vc can be equivalent to the waveform drawn in Figure (b), and the compound's expression of the waveform can be obtained as: [a · eJ “+ a · e” 01] ri · [Sir ^ TTfrO / 7rf7: i] =? (2a) r! [Sin (7r fr x) / π fr x] ........ (1) The result of the pulse width modulation signal PWM after the correction signal Ve is subtracted from the △ / 2 shift, such as the waveform shown in Figure (c), can be obtained from the waveform. Its compound-leaf expression is: 4C · r 2 [sin (7r fr 2) / 7Γ fz * 2] ............ (2) can be expressed by the above formula (1) (2) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Kc={4C*r2[sin(7rfr2)/^fr2]}/{(a + b) [siiUTrfrJ / TrfrJ}(因 1*2正比於 a,且當 f 屬於低頻時,Kc為一常數值。)Kc = {4C * r2 [sin (7rfr2) / ^ fr2]} / {(a + b) [siiUTrfrJ / TrfrJ} (because 1 * 2 is proportional to a, and when f is a low frequency, Kc is a constant value. )
Kp為功率切換單元33之放大增益;及 Κ為功率切換單元33中之一比例(scale)常數; 該STF為訊號轉換函數,STF越高,表示數位功率放 第15頁 本紙張尺度適用中§國家標準(CNS)A4規格(21〇 X 297公釐) 498663 A7Kp is the amplification gain of the power switching unit 33; and K is a scale constant in the power switching unit 33; The STF is a signal conversion function. The higher the STF, the digital power is put on page 15. This paper is applicable to the paper scale. § National Standard (CNS) A4 Specification (21 × 297 mm) 498663 A7
大 放 加 )斤 •著 率 包 及 構 與 修 之 得 、十 系統3輸出之玫大訊號則越大; 該NTF為雜訊轉換函數,NTF越低, ,〇α 、 不數位功率 大裔抑制雜訊能力越佳; 該H(w)係處理單元之總體轉換函數; 因此’由上面STF及NTF式子可以得4d , 士 / ’當K值增(Large amplifier plus) • The rate of coverage and construction and repair, and the large signal of the output of the 10 system 3 are larger; the NTF is a noise conversion function, the lower the NTF, 〇α, non-digit power generation to suppress noise The better the communication ability; the H (w) is the overall conversion function of the processing unit; therefore '4d can be obtained from the above STF and NTF formulas, + / when the K value increases
時’系統之STF跟著增大,但是NTF也會F 思之增加, 以要降低系統之NTF可從增加H(w)Kc,Kp之枯斗攸 或降低nl 手。 繼而,請參照第十三圖所示,係本發明低失真數位功 放大系統之另一較佳實施例,該數位功率放大系統4係 括一調變單元4ί、一修正單元42、一功率切換單元43 一處理單元44 ;且該等單元間之連接關係與内部電路 造係與上述實施例相同,故於此不再贅述。而本實施例 上述實施例不同之處主要係在於該比較訊號係由該 正單元42所產生,且在本實施例中,修正單元42輸出 修正訊號Ve亦分成R一u、R—d、L —u及L — d四道訊號, 該比較訊號Vm係由R_u與L 一u(或者)R—d與L—d相減所 ;因此,由此一數位功率放大系統4,亦可以得到如第 四圖所示之另一等效低頻線性模組,其中, y = n2+ β Κρ 又 # =nl+x e,jwA/2+[// -y/K]H(w)Kc e.jwA/2 且令 x ’ =x e··*w △ /2At the same time, the STF of the system will increase, but the NTF will also increase. In order to reduce the NTF of the system, you can increase the H (w) Kc, Kp or reduce the number of nl hands. Then, please refer to the thirteenth figure, which is another preferred embodiment of the low-distortion digital power amplification system of the present invention. The digital power amplification system 4 includes a modulation unit 4, a correction unit 42, and a power switch. The unit 43 is a processing unit 44; and the connection relationship between these units and the internal circuit structure are the same as those in the above embodiment, so they will not be repeated here. The difference between the above embodiments of this embodiment is mainly that the comparison signal is generated by the positive unit 42, and in this embodiment, the correction signal Ve output by the correction unit 42 is also divided into R_u, R_d, and L. —U and L — d four signals, the comparison signal Vm is obtained by subtracting R_u and L-u (or) R-d and L-d; therefore, a digital power amplification system 4 can also be obtained as Another equivalent low-frequency linear module shown in the fourth figure, where y = n2 + β Κρ and # = nl + xe, jwA / 2 + [// -y / K] H (w) Kc e.jwA / 2 Let x '= xe · * w △ / 2
Kc^Kc e--*wA /2 則可求得該模組之 第16頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---I!------- 裝 i ----I 1 訂· II--II--線 (請先閱讀背面之注意事項再填寫本頁) 498663 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(15) STF=y/x’|nl h2=0=Kp/[l- H(w)Kc,+Kp H(w)Kc,/K] N2TF=y/n2|x’及 nl=0=[l- H(w)Kc,]/[ 1- H(w)Kc,+KpH(w)Kc,/K] NJF=y/nl|x’及 n2=0=Kp/[l- H(w)Kc,+Kp H(w) Kc,/K] 其中,Kc、Kp、K、STF及NTF之定義係與上述模 組相同,而欲進一步加以說明的是,上述兩種回授模式, 其K值之設定係和Kp值有關,所以大略估算Kp值是需 要的,其一般可藉由估算供應電源之直流電壓值而得出Kp 之大略值。 另外,值得注意的一點是,由於修正單元32或42之 相移電路321及寬度延遲電路322中,係以控制訊號Vc 控制一延遲電路使產生時間延遲線(d e 1 a y 1 i n e),再以該延 遲線去對脈波做相移及寬度調整;但因該延遲電路一般會 受溫度變化之影響,使得其對應控制訊號Vc所產生之延 遲線的延遲時間會隨著溫度變化而漂移,使延遲時間不穩 定而造成了系統輸出失真,並且影響到系統之Kc值。因 此’為改善此一問題,可以在修正單元32或42中設置一 /m度變化補償電路’其係使用一極高振蘯頻率之振盪器對 控制訊號Vc在不同溫度下所對應產生之延遲線的延遲 (delay)值所產生之脈波(如第七圖中之脈波寬度調整電路 3 22的AND閘之輸出)進行取樣,以測得此一脈波寬度, 並經D/A轉換後,得到控制訊號Vc在不同溫度下之延遲 線斜率及本質延遲值C(即控制訊號Vc為0時之初始延遲 值)’例如第十五圖所示,分別輸入A、B兩控制訊號, 則可從延遲線之寬度測量並經D/A轉換後,得到對應之 第17頁 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) II---------—#--------訂---------線· <請先閱讀背面之注意事項再填寫本頁) 498663 A7 B7 五、發明說明(16) 見度值dl及d2,即可算出其延遲線斜率及c值,然後再 -以不同溫度下求得之延遲線斜率及本質延遲值C與系統 -内4认疋之一參考斜率及c值比較辱所得之差值去補償 延遲線之變化,即可使延遲線受溫度影響之程度降低。又 一2延遲線實現之方法中,其C值可為零或者不為零, 而當其C值不為零時,則須做相對之補償。 一再者,在此需提出討論的一點是,請參照第十六圖所 •示,s控制訊號Vc與脈波調變訊號之時脈(PWM clock)同 步時,若脈波調變訊號之前一脈波pl受控制訊號Ve之 控制脈波a調整,使得該位移後之脈波寬度超出其週期Ts fe圍而延伸至下一脈波p2之週期ts内時,就會受到下一 控制脈波b之調整,而產生了錯誤的修正訊號。因此為解 决此一不理想情況,可使脈波調變訊號之時脈稍微向右延 遲’使控制訊號之脈波相對向右延遲,如第十七圖所示, 則可使受控制訊號Vc調整後之修正訊號Ve的每一脈波 ^位於其週期Ts範圍内,並增加可修正之範圍,且控制 I號Vc可向右延遲之最大距離係為該脈波寬度調變訊號 之調變係數(modulation index)的二分之一,例如,第十七 圖中之例子,脈波p 1之調變係數為1/2,表示其脈波寬度 J占整個週期TS的1/2,則控制訊號Vc可向右延遲的最大 距離即為週期Ts的1/4,即圖中之3值,如此則可保證經 控制訊號V c調整後之修正訊號Ve的每一脈波皆位於其 週期Ts範圍内。因此,當上述控制訊號vc往右延遲5距 離時’如第^--及十四圖中所示之線性模組中的Kc.e-jwA /2 ^ 第18頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ^ · I I-----t---I-----線 (請先閱讀背面之注意事項再填寫本頁) 498663 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(17) 項,因為Kc A設為常數,因此須對應改成Kc w 一] ’則相當於使控制訊號Vc往右位移一 δ距離。 而且,在此值得一提的是,本發明不但可以應用在上 述較佳實施例以H-bridge為架構之數位功率放大系统中 ’其亦可適用於以―ge為架構之單邊數位功率放 系統中’而其肖H-bridge不同的地方主要在於其調變單 元所調變輸出之PWM訊號係為單道(即不分成ch_r及 — L兩道訊號故其修正單元僅需要一相移電路及一脈 波寬度調整轉’而修正單元產生之修正訊號則僅分成兩 道訊號輸入其功率切換單元中,故其功率切換單元之開關 (切換)元件亦僅需設單邊即可。而且前述兩種線性模組亦 可適用於此half_bddge架構之數位功率放,且其Kc 值亦可由前述說明同理推得。 综上所述,本發明低失真之數位功率放大方法及低失 真之數位功率放大系統,藉由回授至修正單元32之控制 訊號Vc,適當調整輸入之脈波寬度調變訊號的各脈波之 相位及寬《,可確實達到抑制系統雜訊及消除因相位移不 平均所產生之相位雜訊等功效者。 惟’以上所述者’僅係本發明之較佳實施例而已,故 舉凡應用本發明說明書及申請專利範圍所為之等效結構變 化,理應包含在本發明之專利範圍内。 圖式之簡單說明: 第圖係I知一種數位功率放大器之概要電路方塊圖 第19頁 本紙張尺度適用中國國—家標準規格(21G x 297公楚) ----------------------訂---------線 ^1^· (請先閱讀背面之注意事項再填寫本頁) 498663 A7 B7 五、發明說明(18) 放比 率形 功波 位的 數號 知訊 習波 由脈 經之 與出 號輸 訊後 波整 ^ 周 用 言 入術 輸技 示遲 顯延 1 緣 係邊 圖波 二脈 第以 器 大 圖 較 流 要 簡 的 法 方 大 放 率 功 位 數 之 真 失 低 明 發 本 係 圖 〇 三圖 第意 示 程 佳 較 1 的 統 系 大 放 率 功 位 數 之 真。 失圖 低塊 明方 發路 本電 係要 圖主 四之 第例 施 實 波 脈 生 產 元 單 變 調 之 中 fill 塊 方。 路圖 電意 的示 圖 程 四過 第的 係號 圖訊 五變 第調 度 寬 效 等 一 的 元 單 S 處 之 中 圖 塊 方 路 電 的 圖 四 第 係 〇 圖圖 六塊 第方 路 ^¾ r^Jr 電 Λ 口 内 的 元 單 正 修 之 中 圖 塊 方 路 |^& 的 圖 四 第 係 圖 〇 七圖 第意 示 路 波 脈 C 行圖 進意 元示 單形 正波 修的 之號 中訊 圖變 塊調 方度 路寬 電波 的脈 圖 之 四時 第整 係調 圖位 八相 第及 度 寬 的 訊 變 罔 度 寬 波 脈 整 同 2 3 元 單 〇 正理 修原 示作 繪動 係之 圖度 九寬 第及 位 目 鹦 ---I----------. I I (請先閱讀背面之注意事項再填寫本頁> 訂: •線· 痤齊Sri曰i讨轰苟員!.消費合阼汪印製 内 的 元 單 換 切 率 功 之 中 圖 塊 方 路 電 的 圖 四 第 〇 係圖 圖意 十示 第路 τρβτ 部 等 I 之 出 得 而 圖 塊 方 路 T^nr 之 中 圖 四 第 應 對。 係組 圖模 一性 十線 第頻 低 效 另 的 統 系 大 放 率 功 位 數 之。 K 真圖 導失塊 推低方 一 明路 示發電 顯本要 係係主 圖圖之 二三例 十十施 第第實 佳 較 圖 形 波 的 中 子 例 之 值 頁 20 第 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) H-youuj 五、發明說明(19) 第十四圖係對應第十= 一圖中之電路方塊圖而得出 一等效低頻線性模組。 吩刀尼 于出之另 第十五圖係本發明低生# a低失真之數位功放大系統 請 先 閱 背 之 注 意 事 項 再 填 寫 本 頁 度變化補償電路之舉例說明圖示。 皿 第十六圖係顯示當控制 田役制訊唬Vc與脈波調變訊號之時 脈(PWM clock)同步時所產生之不理想情況。 第十七圖係顯示當控制訊號之脈波相對向右延遲 圖式中之參照編號: 當距離時,即可解決第+丄圓* 丁_ 听伏乐十/、圖之不理想情況。 3, 4 數位功率放大系統 31,41 調變單元 32, 42 修正單元 33, 43 功率切換(級)單元 34, 44 處理單元 35 誤差訊號 30, PWM訊號 321 相移電路 322 脈波寬度調整電路 323 比較電路 324 參考訊號產生器 325, 326乘法器 331 負載 3 3 2〜3 3 5切換元件 336, 337差動電路 338 低通滤波器 341,342減法器 343, 343’低通濾波器 344 取樣保持電路 345 超取樣電路 346 分樣器 Vm 比較訊號 Vf 回授訊號 Vc 控制訊號 PWM 脈波寬度調變訊號 Ve 修正訊號 CH—R,CH _L PWM訊號 經濟部智慧財產局員工消費合作社印製 第21頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 498663 A7 B7 五、發明說明(20) R—u,R_d, L_u,L_d Vol, Vo2,Vo3,Vo4 A,B 控制訊號 p 1,p 2 脈波 Ts 脈波週期 修正訊號 放大訊號 dl,d2 寬度值 a, b 控制脈波 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經齊邹智慧財產局員工消費合作社印製 第22頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)Kc ^ Kc e-* wA / 2 can be found on page 16 of this module. The paper size of this module applies to China National Standard (CNS) A4 (210 X 297 mm) --- I! ----- -Install i ---- I 1 order II--II--line (please read the precautions on the back before filling this page) 498663 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( 15) STF = y / x '| nl h2 = 0 = Kp / [l- H (w) Kc, + Kp H (w) Kc, / K] N2TF = y / n2 | x' and nl = 0 = [ l- H (w) Kc,] / [1- H (w) Kc, + KpH (w) Kc, / K] NJF = y / nl | x 'and n2 = 0 = Kp / [l- H (w ) Kc, + Kp H (w) Kc, / K] Among them, the definition of Kc, Kp, K, STF and NTF is the same as the above module, and to further explain, the above two feedback modes, which The setting of the K value is related to the Kp value, so a rough estimate of the Kp value is needed. Generally, the approximate value of Kp can be obtained by estimating the DC voltage value of the power supply. In addition, it is worth noting that, since the phase shift circuit 321 and the width delay circuit 322 of the correction unit 32 or 42 use a control signal Vc to control a delay circuit to generate a time delay line (de 1 ay 1 ine), and then The delay line is used to phase-shift and adjust the width of the pulse wave; but because the delay circuit is generally affected by temperature changes, the delay time of the delay line corresponding to the control signal Vc will drift with temperature change, so that The unstable delay time causes distortion of the system output and affects the Kc value of the system. Therefore, 'to improve this problem, a compensation circuit of one degree / m degree can be set in the correction unit 32 or 42', which uses a very high oscillation frequency oscillator to control the delay line corresponding to the control signal Vc at different temperatures. The pulse generated by the delay value (such as the output of the AND gate of the pulse width adjustment circuit 3 22 in the seventh figure) is sampled to measure this pulse width, and after D / A conversion, Obtain the delay line slope and intrinsic delay value C of the control signal Vc at different temperatures (that is, the initial delay value when the control signal Vc is 0). For example, as shown in the fifteenth figure, input the two control signals A and B respectively. Measured from the width of the delay line and converted by D / A, the corresponding page 17 of this paper is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) II --------- — # -------- Order --------- line · < Please read the notes on the back before filling this page) 498663 A7 B7 V. Description of the invention (16) See the value dl And d2, you can calculate the delay line slope and c value, and then-the delay line slope and the essential delay value C and EC - comparing the difference obtained from one of the insult recognize Cloth 4 c and the reference value to compensate for slope changes in the delay line, the delay line can be reduced by the degree of influence of temperature. In another implementation method of the 2 delay line, the C value may be zero or non-zero, and when the C value is not zero, relative compensation must be made. Again and again, one point that needs to be discussed here is, please refer to the illustration in Figure 16. When the s control signal Vc is synchronized with the pulse clock of the PWM signal (PWM clock), if the pulse modulation signal is The pulse wave pl is adjusted by the control pulse wave a of the control signal Ve, so that the pulse width after the displacement exceeds the period Ts fe and extends to the period ts of the next pulse wave p2, it will receive the next control pulse wave. The adjustment of b resulted in a false correction signal. Therefore, in order to solve this unsatisfactory situation, the clock of the pulse modulation signal can be slightly delayed to the right, so that the pulse of the control signal is delayed to the right, as shown in the seventeenth figure, the controlled signal Vc can be controlled. Each pulse ^ of the adjusted modified signal Ve is within the range of its period Ts, and the range that can be corrected is increased, and the maximum distance that can be delayed to the right by No. I Vc is the modulation of the pulse width modulation signal One half of the modulation index. For example, in the example in Figure 17, the modulation coefficient of the pulse wave p 1 is 1/2, which means that the pulse width J occupies 1/2 of the entire period TS, then The maximum distance that the control signal Vc can be delayed to the right is 1/4 of the period Ts, which is the three values in the figure. This ensures that each pulse of the modified signal Ve adjusted after the control signal V c is located in its period Ts range. Therefore, when the above-mentioned control signal vc is delayed by 5 distances to the right, 'Kc.e-jwA / 2 ^ in the linear module shown in Figures ^-and 14] Page 18 This paper applies Chinese national standards (CNS) A4 specification (210 X 297 mm) ^ · I I ----- t --- I ----- line (Please read the precautions on the back before filling this page) 498663 A7 B7 Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative printed item 5. Item (17) of the invention description, because Kc A is set to a constant, so it must be changed to Kc w a] ', which is equivalent to shifting the control signal Vc to the right by a δ distance. Moreover, it is worth mentioning here that the present invention can not only be applied to the above-mentioned preferred embodiment of the digital power amplifier system based on H-bridge, it can also be applied to a unilateral digital power amplifier based on ge The main difference between the system and its H-bridge is that the PWM signal modulated by its modulation unit is a single channel (that is, it is not divided into two signals of ch_r and-L, so its correction unit only needs a phase shift circuit. And a pulse width adjustment switch, and the correction signal generated by the correction unit is only divided into two signals input to its power switching unit, so the switching (switching) element of its power switching unit only needs to be provided on one side. And the aforementioned The two linear modules can also be applied to the digital power amplifier of the half_bddge architecture, and its Kc value can also be derived from the same explanation as above. In summary, the low distortion digital power amplification method and low distortion digital power of the present invention The amplification system, through feedback of the control signal Vc to the correction unit 32, appropriately adjusts the phase and width of each pulse wave of the input pulse width modulation signal, which can surely achieve suppression of system noise and In addition to the effects of phase noise caused by uneven phase shift, etc., but the 'mentioned one' is only a preferred embodiment of the present invention, so the equivalent structural changes for the application of the present specification and the scope of patent applications It should be included in the patent scope of the present invention. Brief description of the drawing: The figure is a schematic circuit block diagram of a digital power amplifier. Page 19 This paper is applicable to China's standard specifications (21G x 297 cm) ) ---------------------- Order --------- line ^ 1 ^ · (Please read the notes on the back before filling this page ) 498663 A7 B7 V. Description of the invention (18) The digital signal of the proportional wave power wave is learned from the meridian and the output signal, and the wave is integrated. The figure of the second pulse of the pulse wave is larger than the streamlined method of the French method. The true power loss is low. This figure is shown in the figure. Missing picture, low block, bright side, and the first line of the main line of the electric system. Fill the squares in the metatonic tone. Road maps are shown in Figure 4 of the series. Figure 5th in the 5th schedule and the schedule wide effect is in Yuandan S at the middle of the squares. 〇 Figure six block square road ^ ¾ r ^ Jr Yuan Λ in the mouth of Yuandan is repairing the square block square road | ^ & The elementary signal of the positive wave repair is shown in Figure 4. The block diagram of the square wave width of the radio wave pulse pattern is four o'clock and the whole system is the eighth phase. 3 yuan 〇 Zhengli Xiu originally showed the figure of the 9th wide and the first parrot of the movement system --- I ----------. II (Please read the precautions on the back before filling this page > Order: • Line · Sri Qi, I ’m talking about the members !. Figure 4 of the square circuit diagram of the block diagram of the power consumption in the yuan conversion and cutting rate power consumption within the printing unit. The first path τρβτ part and other I come out, and the square path T ^ nr in the block square response. The system's graphic mode has the same ten-line frequency and low efficiency. The other system has a large power rate. K True picture guide block is pushed down. Yiming Road shows that the power generation display is mainly the second and third examples of the main map. The value of the neutron example of the tenth best figure is better than the figure. Page 20 The Chinese standard is applicable to this paper size. (CNS) A4 specification (210 X 297 mm) H-youuj V. Description of the invention (19) The fourteenth figure corresponds to the circuit block diagram of the tenth = one figure and an equivalent low-frequency linear module is obtained. The fifteenth figure is the digital power amplifier system of the low-generation # a low-distortion digital power amplifier system of the present invention. Please read the notes on the back first and then fill out this page to illustrate the example of the compensation circuit for degree change. The sixteenth figure shows the unsatisfactory situation that occurs when controlling the field service signal Vc to synchronize with the pulse clock (PWM clock). The seventeenth figure shows that when the pulse of the control signal is delayed to the right, the reference number in the figure: When the distance is reached, you can solve the unsatisfactory situation of the + 丄 circle * 丁 _ listen to Fu Le X /. 3, 4 Digital power amplifier system 31, 41 Modulation unit 32, 42 Correction unit 33, 43 Power switching (stage) unit 34, 44 Processing unit 35 Error signal 30, PWM signal 321 Phase shift circuit 322 Pulse width adjustment circuit 323 Comparison circuit 324 Reference signal generator 325, 326 Multiplier 331 Load 3 3 2 ~ 3 3 5 Switching element 336, 337 Differential circuit 338 Low-pass filter 341, 342 Subtractor 343, 343 'Low-pass filter 344 Sample and hold Circuit 345 Oversampling circuit 346 Divider Vm Comparison signal Vf Feedback signal Vc Control signal PWM Pulse width modulation signal Ve Correction signal CH—R, CH _L PWM signal Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Page 21 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 498663 A7 B7 V. Description of the invention (20) R—u, R_d, L_u, L_d Vol, Vo2, Vo3, Vo4 A, B control signals p 1, p 2 pulse wave Ts pulse wave period correction signal amplification signal dl, d2 width value a, b control pulse wave ------------- install -------- order- -------- Line (Please read the notes on the back before filling this page) Qi Zou Zhihui Property Office employees consumer cooperatives printed on page 22 Paper scale applicable to Chinese National Standard (CNS) A4 size (210 X 297 mm)
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TW90105959A TW498663B (en) | 2001-03-14 | 2001-03-14 | Low distortion digital power amplification method and system therefor |
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TW90105959A TW498663B (en) | 2001-03-14 | 2001-03-14 | Low distortion digital power amplification method and system therefor |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI396440B (en) * | 2008-08-22 | 2013-05-11 | Aten Int Co Ltd | Signal compensation apparatus, signal compensation method and multi-computer switch system |
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2001
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI396440B (en) * | 2008-08-22 | 2013-05-11 | Aten Int Co Ltd | Signal compensation apparatus, signal compensation method and multi-computer switch system |
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