經濟部智慧財產局員工消費合作社印製 498619 A7 B7____ 五、發明說明（l ) 發明領域 本發明係有關於一種數位電路設計，特別是有關於一 種具有相位校正電路（phase alignment circuit )之數位電路設 計。 發明背景 引證參考資料 美國專利文件： 美國專利號6,060,928 ; 美國專利號6，144,713 ; 美國專利號6，166,572 ;以及 美國專利號6，125，157。 延遲鎖相迴路（delayed locked loop )通常使用於高速相 位校正電路，例如雙資料速率同步動態隨機存取記憶體 (DDRSDRAM )中。在使用DDRSDRAM作爲記憶儲存裝置 的系統中，需要一資料脈衝相位控制（data strobe phase control )以鎖定（latch )被DDRSDRAM (以下稱爲 DDR ) 送回的讀取資料。DDR在每個時脈邊緣送出資料脈衝與資 料，因此稱爲「邊緣校準」（edgealigned);而當DDR在每 個時脈中央執行寫入資料脈衝與資料，因此稱爲「中央校 準」（center-aligned )。此種分別針對讀取與寫入以不同時 脈位置觸發的方法，是爲了在DDR製造中簡化設計與得到 更佳的良率。因此，當DDR執行寫入週期時，系統必須產 生一準確的四分之一延遲以用於中央校準脈衝與資料。 4SIS200101TW: 89P76 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裳—— (請先閱讀背面之注意事項寫本頁) 訂： 線· 498619 A7 ______B7 五、發明說明（> ) 圖1顯示一典型的DLL電路。相位檢測器130比較 ext_clk信號與由T/4延遲線路115所產生的delay_clk信號。 延遲線路監控器H0因應來自相位檢測器13〇的 increment_or-decrement 彳目號，輸出 deiay_contr〇i_numi3er 信號至延遲 線路115及116以調整延遲量。最後系統收斂並且獲得 T/4延遲時脈（delay clock ) 150。然而，來自相位檢測器 130的結果可能因溫度的變化而漂移，導致延遲線路監控 器140提供不適當的資訊至T/4延遲線路115以及116。 而且，製程改變也可能影響來自相位檢測器130的結果。 因此，本發明提出一具有雙鎖定機制以及動態延遲控制的 數位延遲鎖相迴路電路以解決上述之問題。應注意的是， 本發明可產生任何希望的延遲信號。所以本發明可以使用 在任何使用DLL機構的電路中。 發明槪述 本發明提供一使用雙軌式數位延遲鎖相迴路（DLL ) 之準確的時間延遲產生器。此雙軌式數位DLL包括一第一 延遲線路、一第二延遲線路、一延遲單元、一第一相位檢 測器、一第二相位檢測器、〜延遲線路監控器、一數位對 時間轉換器（DTC )延遲單元。 第一延遲線路接收一外部時脈信號以及一第一延遲控 制信號，以產生一第一延遲信號。並且第二延遲線路接收 一第二延遲控制信號以及外部時脈信號，以產生一第二延 遲信號。延遲單元使用外部時脈信號、第一延遲信號以及 4SIS200101TW; 89P76 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复） (請先閱讀背面之注意事項寫 π本頁) 經濟部智慧財產局員工消費合作社印製 498619 A7 B7 五、發明說明（3 弟一延遲號’以產生一內部延遲信號。第一相位檢測器 接收內部延遲信號以及第一延遲信號，以產生一第一控制 信號；而第二相位檢測器使用內部延遲信號以及第二延遲 信號，以產生一第二控制信號。延遲線路監控器因應第一 以及第二控制信號，而產生第一延遲控制信號以及第二延 遲控制信號。延遲信號係由DTC延遲單元所產生，其中 DTC延遲單元的輸入爲外部時脈信號以及第一延遲控制信 號。 本發明提供一雙軌式延遲鎖相迴路，以產生希望的延 遲信號。在此所介紹的雙軌式DLL設計根據電壓及溫度的 變化而動態地改變DTC延遲單元的延遲。在此提供之電路 可應用於任何高速相位校正系統中，並且延遲量可以藉引 入N個DTC延遲單元至延遲線路，而被擴展爲1/N週期的 時間。 (請先閱讀背面之注意事項再本頁) 裝 訂 經濟部智慧財產局員工消費合作社印製 圖示簡單說明 圖1以圖表顯示一習知的DLL電路’可產生一 T/4延 遲時脈。 圖2以圖表顯示一根據本發明設計的雙軌式DLL電 路，可產生一 T/N延遲時脈。 圖3以圖表顯示如圖2中一 DTC延遲單元的具體實施 例。 圖4以圖表顯示一根據本發明設計的雙軌式DLL電 路，可產生一 T/4延遲時脈。 4SIS200101TW; 89P76 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 線 A7Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 498619 A7 B7____ V. Description of the Invention (1) Field of the Invention The present invention relates to a digital circuit design, and in particular to a digital circuit design with a phase alignment circuit . BACKGROUND OF THE INVENTION Citation references US patent documents: US Patent No. 6,060,928; US Patent No. 6,144,713; US Patent No. 6,166,572; and US Patent No. 6,125,157. A delayed locked loop is usually used in a high-speed phase correction circuit, such as a dual data rate synchronous dynamic random access memory (DDRSDRAM). In a system using DDRSDRAM as a memory storage device, a data strobe phase control is required to latch the read data sent back by DDRSDRAM (hereinafter referred to as DDR). DDR sends data pulses and data at the edge of each clock, so it is called "edgealigned"; and when DDR writes data pulses and data at the center of each clock, it is called "center calibration" (center -aligned). This method for reading and writing with different clock positions is to simplify the design and get better yield in DDR manufacturing. Therefore, when the DDR performs a write cycle, the system must generate an accurate quarter delay for the central calibration pulse and data. 4SIS200101TW: 89P76 1 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -------------- Shang—— (Please read the notes on the back first to write this Page) Order: Line · 498619 A7 ______B7 V. Description of the invention (>) Figure 1 shows a typical DLL circuit. The phase detector 130 compares the ext_clk signal with the delay_clk signal generated by the T / 4 delay line 115. The delay line monitor H0 outputs the deiay_controi_numi3er signal to the delay lines 115 and 116 in response to the increment_or-decrement number from the phase detector 13 to adjust the delay amount. Finally, the system converges and obtains a T / 4 delay clock (delay clock) 150. However, the results from the phase detector 130 may drift due to temperature changes, causing the delay line monitor 140 to provide inappropriate information to the T / 4 delay lines 115 and 116. Moreover, process changes may also affect results from the phase detector 130. Therefore, the present invention proposes a digital delay phase locked loop circuit with a double lock mechanism and dynamic delay control to solve the above problems. It should be noted that the present invention can produce any desired delayed signal. Therefore, the present invention can be used in any circuit using a DLL mechanism. SUMMARY OF THE INVENTION The present invention provides an accurate time delay generator using a dual-track digital delay phase locked loop (DLL). The dual-track digital DLL includes a first delay line, a second delay line, a delay unit, a first phase detector, a second phase detector, a delay line monitor, and a digital-to-time converter (DTC). ) Delay unit. The first delay line receives an external clock signal and a first delay control signal to generate a first delay signal. And the second delay line receives a second delay control signal and an external clock signal to generate a second delay signal. The delay unit uses the external clock signal, the first delay signal and 4SIS200101TW; 89P76 9 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public copy) (Please read the precautions on the back first and write π page) Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 498619 A7 B7 V. Description of the invention (3, a delay number 'to generate an internal delay signal. The first phase detector receives the internal delay signal and the first delay signal to generate a first A control signal; and the second phase detector uses an internal delay signal and a second delay signal to generate a second control signal. The delay line monitor generates a first delay control signal and a second response signal in response to the first and second control signals. Delay control signal. The delay signal is generated by the DTC delay unit. The input of the DTC delay unit is an external clock signal and a first delay control signal. The present invention provides a dual-track delay phase locked loop to generate a desired delay signal. The dual-rail DLL design introduced here dynamically changes the DTC delay based on changes in voltage and temperature. Unit delay. The circuit provided here can be applied to any high-speed phase correction system, and the amount of delay can be extended to 1 / N cycle time by introducing N DTC delay units to the delay line. (Please read the back first (Notes on this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Binding, a simple illustration. Figure 1 shows a conventional DLL circuit in a graph 'can produce a T / 4 delay clock. Figure 2 shows a graph with a The dual-track DLL circuit designed according to the present invention can generate a T / N delay clock. Fig. 3 shows a specific embodiment of a DTC delay unit as shown in Fig. 2. Fig. 4 shows a dual track designed according to the present invention. DLL circuit can generate a T / 4 delay clock. 4SIS200101TW; 89P76 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) line A7
五、發明說明（今） 圖5顯不雙軌式DLL電路的鎖住實例。 圖6顯不雙軌式dll電路的領先實例。 (請先閱讀背面之注意事項再^^本頁) 圖7顯示雙軌式DLL電路的落後實例。 圖8顯示一 DTC延遲單元因製程變化所產生的非線性 知* 性（non-linear characteristics ) ° 圖9顯示一具有4DTC延遲單元的延遲線路，因製程 變化所產生的非線性特性。 發明詳細說明 請參閱圖2，其以圖表顯示一根據本發明設計的雙軌 式DLL電路，可產生一 τ/Ν延遲時脈，其中T是一時脈週 期時間（clock cycle time )以及N是一預定的數目。本發明 之雙軌式DLL電路包括：一第一延遲線路200、一第二延 遲線路220、一延遲單元，較佳者爲一半解析度 (half-resolution )延遲單元235、一第一相位檢測器245、 一第二相位檢測器255、一延遲線路監控器265以及一 DTC延遲單元270。 經濟部智慧財產局員工消費合作社印製 第一延遲線路200，因應一外部時脈信號（extjlk ) 以及一第一延遲控制信號210，而產生一第一延遲信號 215。第二延遲線路因應一第二延遲控制信號225以及 ext_dk220，而產生一第二延遲信號230。較佳者爲第一延 遲線路200以及第二延遲線路220分別具有N個DTC延遲 單元，其中N是一預定的數目。半解析度延遲單元235因 應ext_dk，而產生一內部延遲信號240。較佳者爲半解析 4SIS200101TW; 89P76 4 適用中國國家標準（CNS)A4規格（210 X 297公f ) 498619 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（5) 度延遲單元235進一步因應第一延遲信號215以及第二延 遲信號230。第一相位檢測器245比較內部延遲信號240 與第一延遲信號215，以產生一第一控制信號250。 第二相位檢測器255比較內部延遲信號240與第二延 遲信號230，以產生一第二控制信號260。延遲線路監控 器265因應第一以及第二控制信號（250及260 )，產生 第一延遲控制信號210以及第二延遲控制信號225。關於 延遲線路監控器265的進一步功能之說明，請參考關於圖 4之說明。DTC延遲單元270因應ext_clk以及第一延遲控 制信號210，產生延遲信號275。 圖3顯示DTC延遲單元如何轉化4位元延遲控制數位 輸入305爲延遲信號輸出310。DTC延遲單元包括一數位 延遲數目編碼器320。數位延遲數目編碼器320接收4位 元延遲控制數位輸入305並且產生DO、D1…至D15信 號，在DTC延遲單元中總共有16延遲刻度（Tscale)，當D (η ) =1，表示一對應的延遲存在。因此，DTC延遲單元 根據4位元延遲控制數位輸入305接收一輸入信號315以 及輸出延遲信號輸出310。 請參考圖4。在本發明之一較佳實施例中，在第一延 遲線路400以及第二延遲線路420中的DTC延遲單元的數 目分別等於4。亦即Ν = 4。第一延遲線路400因應具有k 値之第一延遲控制信號（delay_contrOl_coiint )以及ext_clk信 號，而產生第一延遲信號delay_clk ( k )，其至少爲k的函 數。第二延遲線路420因應具有k+Ι値之第二延遲控制信 4SIS200101TW; 89P76 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝—— (請先閱讀背面之注意事項再5^本頁) · 498619 A7 B7_____ 五、發明說明（t ) 號（delay_control _count_l )以及 ext_clk 信號，而產生第二延 遲信號（delay_clk ( k+Ι ))，其至少爲（k+1 )之函數。 delay_clk ( k )以及delay_clk ( k+Ι )之時間差定義爲一最小 的解析度Tres，其亦是第一延遲線路400以及第二延遲線 路420之最小解析度。所以delay_clk ( k )比delay_clk (k+1 )超前一 Tres。 再者，由半解析度延遲單元435所產生的內部延遲信 號（int_clk )比ext__clk延遲一 l/2Tres。第一相位檢測器 445比較int_clk與delay_clk ( k )，並且輸出第一控制信號 (decrement );第二相位檢測器 455 比較 int_clk 與delay_clk (k+1 )，並且輸出第二控制信號（increment )。在較佳 的實施例中，第一相位檢測器445以及第二相位檢測器 455分別爲D正反器（D-flip-flop )。 爲了使第一相位檢測器445以及第二相位檢測器455 正確地鎖定delay_clk ( k )以及delay_clk ( k+1 )，int_clk 應 落在delay_clk ( k )以及delay_clk ( k+1 )之間。有必要提供 足夠的設置時間（Tsetup )至第一相位檢測器445，以及 足夠的維持時間（Thold)至第二相位檢測器455。因此， Tres應該比Tsetup及Thold之總和爲大。亦即，Tres — (Tsetup + Thold )。然而，已知在大多數的實例中，Tsetup 比Thold大。所以，在較佳實施例中，設定：V. Description of the Invention (Today) Figure 5 shows a locking example of a dual-track DLL circuit. Figure 6 shows a leading example of a dual-track dll circuit. (Please read the precautions on the back before ^^ this page) Figure 7 shows a backward example of a dual-rail DLL circuit. Figure 8 shows the non-linear characteristics of a DTC delay unit due to process changes. Figure 9 shows the non-linear characteristics of a delay line with 4 DTC delay units due to process changes. For a detailed description of the invention, please refer to FIG. 2, which shows a diagram of a dual-rail DLL circuit designed according to the present invention, which can generate a τ / N delay clock, where T is a clock cycle time and N is a predetermined time. Number of. The dual-track DLL circuit of the present invention includes: a first delay line 200, a second delay line 220, a delay unit, preferably a half-resolution delay unit 235, and a first phase detector 245 A second phase detector 255, a delay line monitor 265, and a DTC delay unit 270. The first delay line 200 is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and a first delay signal 215 is generated in response to an external clock signal (extjlk) and a first delay control signal 210. The second delay line generates a second delay signal 230 according to a second delay control signal 225 and ext_dk220. Preferably, the first delay line 200 and the second delay line 220 each have N DTC delay units, where N is a predetermined number. The half-resolution delay unit 235 generates an internal delay signal 240 in response to ext_dk. The better one is semi-analytical 4SIS200101TW; 89P76 4 Applicable to China National Standard (CNS) A4 specification (210 X 297 male f) 498619 Printed by A7 B7, Employee Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (5) Degree delay unit 235 It further corresponds to the first delay signal 215 and the second delay signal 230. The first phase detector 245 compares the internal delay signal 240 with the first delay signal 215 to generate a first control signal 250. The second phase detector 255 compares the internal delay signal 240 with the second delay signal 230 to generate a second control signal 260. The delay line monitor 265 generates a first delay control signal 210 and a second delay control signal 225 in response to the first and second control signals (250 and 260). For a description of further functions of the delay line monitor 265, please refer to the description about FIG. The DTC delay unit 270 generates a delay signal 275 in response to ext_clk and the first delay control signal 210. Figure 3 shows how the DTC delay unit translates a 4-bit delay control digital input 305 into a delay signal output 310. The DTC delay unit includes a digital delay number encoder 320. Digital delay number encoder 320 receives 4-bit delay control digital input 305 and generates DO, D1 ... to D15 signals. There are a total of 16 delay scales (Tscale) in the DTC delay unit. When D (η) = 1, it indicates a correspondence The delay exists. Therefore, the DTC delay unit controls the digital input 305 to receive an input signal 315 and the output delay signal output 310 according to the 4-bit delay control. Please refer to Figure 4. In a preferred embodiment of the present invention, the number of DTC delay units in the first delay line 400 and the second delay line 420 is equal to four, respectively. That is, N = 4. The first delay line 400 responds to the first delay control signal (delay_contrOl_coiint) and the ext_clk signal with k 値 to generate a first delay signal delay_clk (k), which is at least a function of k. The second delay line 420 corresponds to the second delay control letter 4SIS200101TW; 89P76 with k + 1 値 5 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---------- ---- Install—— (Please read the precautions on the back and then 5 ^ this page) · 498619 A7 B7_____ V. Invention Description (t) number (delay_control _count_l) and ext_clk signal to generate a second delay signal (delay_clk ( k + 1)), which is at least a function of (k + 1). The time difference between delay_clk (k) and delay_clk (k + 1) is defined as a minimum resolution Tres, which is also the minimum resolution of the first delay line 400 and the second delay line 420. So delay_clk (k) is one Tres ahead of delay_clk (k + 1). Moreover, the internal delay signal (int_clk) generated by the half-resolution delay unit 435 is delayed by ½_Tres compared to ext__clk. The first phase detector 445 compares int_clk and delay_clk (k) and outputs a first control signal (decrement); the second phase detector 455 compares int_clk and delay_clk (k + 1) and outputs a second control signal (increment). In a preferred embodiment, the first phase detector 445 and the second phase detector 455 are D-flip-flops, respectively. In order for the first phase detector 445 and the second phase detector 455 to lock the delay_clk (k) and delay_clk (k + 1) correctly, int_clk should fall between delay_clk (k) and delay_clk (k + 1). It is necessary to provide sufficient setup time (Tsetup) to the first phase detector 445, and sufficient hold time (Thold) to the second phase detector 455. Therefore, Tres should be larger than the sum of Tsetup and Thold. That is, Tres — (Tsetup + Thold). However, Tsetup is known to be larger than Thold in most instances. Therefore, in the preferred embodiment, set:
Tres ^ 2*Tsetup------方程式（1)。 在本發明之一較佳實施例中，所有在第一延遲線路 400以及第二延遲線路420中的DTC延遲單元都是一樣 4SIS200101TW; 89P76 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —------------裝--- (請先閱讀背面之注意1*自1||^^—" 訂· 線· 經濟部智慧財產局員工消費合作社印製 498619 經濟部智慧財產局員工消費合作社印製 A7 ___B7____五、發明說明（勹） 的。DTC延遲單元之最小的解析度Tres由上述D正反器的 兩倍Tsetup所定義。若D正反器之Tsetup爲0.2ns，則可選 擇Tres爲0.5ns，其大於2*Tsetup，並且由半解析度延遲單兀 所產生的延遲是0.25ns。 請參考圖5。當delay_clk ( k )與ext_clk校準，即符合 鎖住的情況。delay_clk ( k )正好比ext_clk晚一個時脈週 期，以及delay__clk ( k+Ι )比ext_clk晚一個時脈週期加上 Tres。在鎖住的情況中，第一相位檢測器445設定減少量 信號爲0，而且第二相位檢測器455設定增加量信號爲 0。則延遲線路監控器465不會改變delay_cc)ntrd_count以及 delay一control 一count一 1 之値。 DTC 延遲單元 470 因應 ext_clk 以及 delay_control_count， 產生延遲信號475。因此，在N = 4之範例中，一四分之一* 週期延遲時脈信號475可從DTC延遲單元470中獲得。 如圖6所不之領先實例中，delay_clk ( k )領先ext_clk 少於一個時脈週期的量。在領先的實例中，第一相位檢測 器445設定減少量信號爲0，以及第二相位檢測器455設 定增加量信號爲1。則延遲線路監控器465以1爲增量， 分別增加 delay_control—count 以及 delay__contr〇Lcount_l 之値。第 一延遲線路 400 因應 ext_clk 以及 delay_control_count，產生 delay_clk ( k )。第二延遲線路420因應ext_clk以及 delay_control_count_l ，產生delay—elk ( k+1 )。因此第一延遲 線路400以及第二延遲線路420的延遲增加。若delay_clk (k )仍然領先ext_clk少於一個時脈週期的量，則雙軌式 4SIS200101TW; 89P76 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項 本頁) 裝 --線- 498619 A7 B7 五、發明說明（2) dll電路繼續上述之步驟’直到達到如圖5所示的鎖住實 例爲止。 對於如圖7所示落後實例，delay_clk ( k )落後ext一elk 少於一個時脈週期的量。在落後的實例中’第一相位檢測 器445設定減少量信號爲1 ’並且第二相位檢測器455設 定增加量信號爲〇。則延遲線路監控描1 465以1爲減量， 減少 delay_contr〇LcQimt 以及 delay_CQntrd_cQimU 之値。第一延 遲線路 400 因應 ext一elk 以及 delay_control一count，產生delay_clk (k )。第二延遲線路420因應ext—clk以及 delay_control_counLl ’產生delay—elk ( k+1 )。因此，第一延 遲線路400以及第二延遲線路420的延遲減少。若delay__clk (k )仍然落後ext_clk少於一個時脈週期的量，則雙軌式 DLL電路繼續上述之步驟，直到達到如圖5所示的鎖住實 例爲止。 此外，若在DTC延遲單元的電路片段中有非線性特 性，並不會影響系統的收斂。因爲兩延遲線路400及420 是對稱電路結構，兩者隨著製程、溫度、及供應電壓的變 動而以同樣的方式以及百分比變化。圖8顯示一發生在延 遲控制數位輸入305之8 (即1000 )至9 (即1001 )範圍 的單一 DTC單元之延遲刻度（Tscale)的非線性特性。Tscale 之値從0.125ns改變至〇.25ns ，導致一非線性情況。據此， 如圖9所示第一延遲線路400以及第二延遲線路420的最 小解析度（即Tres )從0.5ns變化至Ins。Int—elk相對於 ext_clk 有一 0.25ns 的漂移。因此 int_clk 仍然落在delay_clk 4SIS200101TW; 89P76 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事項^¾^寫本頁) · 線· 經濟部智慧財產局員工消費合作社印製 498619 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（q) (k )以及delay_clk ( k+1 )之間’並且雙軌式DLL電路可 以容忍PVT (製程、電壓、溫度）變化。 此外，雙軌式數位DLL設計可以輕易地產生T/N時間 延遲’其中N分別是在弟一'延遲線路400以及弟一^延遲線 路420中DTC延遲單元的數目，而T是時脈週期時間。參 考圖3的實施例，假設在本發明的單一 DTC延遲單元不是 具有16延遲刻度，而是具有L個Tscales。則以下所推得之 方程式滿足鎖住之情況，如方程式（2 )所示。 T = Tscale * L * N--------方程式（2)。 貝[J，Tres = delay一elk ( K+l ) - delay—elk ( K ) = Tscale* (K+l ) *N - Tscale*L*N = Tscale*N---方程式（3 )。 從上述之方程式（1 )、（ 2 )以及（3 ) ’當鎖住 情況發生時，T = L*Tres g 2L*Tsetup--方程式（4 )。 從方程式（2 )，Tscale ^ ( 2/N ) *Tsetup ----方程式（5) ° 在一較佳實施例中，假設Tsetup = 0.2ns，則從方程式 (1 )中可選擇Tres爲0.5ns，如果目標週期時間（τ )爲 7.5ns (意即時脈頻率133MHz )，從方程式（4 )中可以選 擇 L=15。 在另一較佳實施例中，假設在方程式（5 )中N=4 ’ 如果選擇 Tsetup 爲 a2ns，則 Tscale - 0.5*Tsetup = 〇.lns ° 因 此Tscale應大於0.1ns以容忍PVT變化。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此項技術者，在不脫離本發明之精神和 4SIS200101TW; 89P76 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意I*自^ 訂： 線· 498619 A7 B7___ 五、發明說明（\〇) 範圍內，當可做些許之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項本頁) 訂 經濟部智慧財產局員工消費合作社印制衣 4SIS200101TW; 89P76 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Tres ^ 2 * Tsetup ------ Equation (1). In a preferred embodiment of the present invention, all the DTC delay units in the first delay line 400 and the second delay line 420 are the same. 4SIS200101TW; 89P76 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —------------ Installing --- (Please read the note on the back 1 * from 1 || ^^ — " Order · Line · Intellectual Property Bureau Staff of the Ministry of Economic Affairs Printed by the Consumer Cooperative 498619 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7____ V. Invention Description (勹). The minimum resolution Tres of the DTC delay unit is defined by Tsetup which is twice the D flip-flop. For D flip-flop with Tsetup of 0.2ns, you can choose Tres to be 0.5ns, which is greater than 2 * Tsetup, and the delay caused by the half-resolution delay unit is 0.25ns. Please refer to Figure 5. When delay_clk (k) Calibration with ext_clk is consistent with the locked condition. Delay_clk (k) is exactly one clock cycle later than ext_clk, and delay__clk (k + 1) is one clock cycle later than ext_clk plus Tres. In the locked case, the A phase detector 445 sets the reduction signal to 0, and the second phase The bit detector 455 sets the increase signal to 0. Then the delay line monitor 465 does not change delay_cc) ntrd_count and delay_control_count_1. The DTC delay unit 470 generates a delay signal 475 according to ext_clk and delay_control_count. Therefore, in the example of N = 4, a quarter * period delay clock signal 475 can be obtained from the DTC delay unit 470. As shown in the leading example shown in Fig. 6, delay_clk (k) leads ext_clk by less than one clock cycle. In the leading example, the first phase detector 445 sets the decrement signal to 0, and the second phase detector 455 sets the decrement signal to 1. The delay line monitor 465 increments delay_control_count and delay__contr0Lcount_l in increments of 1, respectively. The first delay line 400 generates delay_clk (k) in response to ext_clk and delay_control_count. The second delay line 420 generates delay_elk (k + 1) in response to ext_clk and delay_control_count_l. Therefore, the delays of the first delay line 400 and the second delay line 420 increase. If delay_clk (k) is still ahead of ext_clk by less than one clock cycle, the dual-track type 4SIS200101TW; 89P76 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first Matters on this page) Installation-Line-498619 A7 B7 V. Description of the invention (2) The DLL circuit continues the above steps' until it reaches the locked instance shown in Figure 5. For the lagging example shown in Figure 7, delay_clk (k) lags ext-elk by less than one clock period. In the backward example, 'the first phase detector 445 sets the decrease signal to 1' and the second phase detector 455 sets the increase signal to zero. Then the delay line monitoring trace 1 465 takes 1 as the decrement, reducing delay_contr0LcQimt and delay_CQntrd_cQimU. The first delay line 400 generates delay_clk (k) in response to ext_elk and delay_control_count. The second delay line 420 generates delay_elk (k + 1) in response to ext_clk and delay_control_counLl '. Therefore, the delays of the first delay line 400 and the second delay line 420 are reduced. If delay__clk (k) is still behind ext_clk by less than one clock cycle, the dual-rail DLL circuit continues the above steps until it reaches the lockout example shown in FIG. 5. In addition, if there are nonlinear characteristics in the circuit segments of the DTC delay unit, it will not affect the convergence of the system. Because the two delay lines 400 and 420 are symmetrical circuit structures, they both change in the same manner and percentage as the process, temperature, and supply voltage change. Figure 8 shows the non-linear characteristics of the delay scale (Tscale) of a single DTC unit occurring in the delay control digital input 305 from 8 (ie 1000) to 9 (ie 1001). The scale of Tscale changed from 0.125ns to 0.25ns, resulting in a non-linear situation. Accordingly, as shown in FIG. 9, the minimum resolution (ie, Tres) of the first delay line 400 and the second delay line 420 changes from 0.5 ns to Ins. Int_elk has a drift of 0.25ns relative to ext_clk. Therefore, int_clk still falls on delay_clk 4SIS200101TW; 89P76 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------- install --- (please first Read the notes on the back ^ ¾ ^ Write this page) · Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 498619 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (q) (k) and delay_clk (k + 1) between 'and dual-rail DLL circuit can tolerate PVT (process, voltage, temperature) changes. In addition, the dual-track digital DLL design can easily generate T / N time delay ', where N is the number of DTC delay units in the D' delay line 400 and D 'delay line 420, respectively, and T is the clock cycle time. Referring to the embodiment of FIG. 3, it is assumed that a single DTC delay unit in the present invention does not have a delay scale of 16 but has L Tscales. Then the equation obtained below satisfies the locked condition, as shown in equation (2). T = Tscale * L * N -------- equation (2). [J, Tres = delay-elk (K + l)-delay—elk (K) = Tscale * (K + l) * N-Tscale * L * N = Tscale * N --- Equation (3). From the above-mentioned equations (1), (2), and (3) 'when the locking condition occurs, T = L * Tres g 2L * Tsetup--Equation (4). From equation (2), Tscale ^ (2 / N) * Tsetup ---- equation (5) ° In a preferred embodiment, assuming Tsetup = 0.2ns, then from equation (1), Tres can be selected as 0.5 ns, if the target cycle time (τ) is 7.5ns (meaning the clock frequency is 133MHz), L = 15 can be selected from the equation (4). In another preferred embodiment, it is assumed that N = 4 ′ in equation (5). If Tsetup is selected as a2ns, then Tscale-0.5 * Tsetup = 0.1ns. Therefore, Tscale should be greater than 0.1ns to tolerate PVT changes. Although the present invention is disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art will not deviate from the spirit of the present invention and 4SIS200101TW; 89P76 9 This paper standard is applicable to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -------------- install --- (Please read the note on the back I * Custom ^ Order: line · 498619 A7 B7___ V. Description of the invention (\ 〇) Within the scope, some modifications and retouching can be done, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the note on the back page first) Order the intellectual property of the Ministry of Economic Affairs Bureau's Consumer Cooperatives Printed Clothes 4SIS200101TW; 89P76 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)