498529 A7 533twf.doc/009 五、發明說明（/ ) 本發明是有關於一種覆晶構裝及其製程，且特別是 有關於一種不需在晶片上形成重配置線路層之覆晶構裝及 其所對應的製程。 在現今資訊爆炸的社會，電子產品遍佈於日常生活 中，無論在食衣住行育樂方面，都會用到積體電路元件所 組細產品。隨著電子科技不斷地演進，功能性更複雜、 ，人性化的產品推陳出新，就電子產品外_言，也朝向 '、薄七二小的麵_+，因此在半雜封裝技術上， 開發出許多高密度半導___式。而觀覆晶封裝 (Fhp Chlp)技術可以翻上述的目的，由於覆晶晶片的封 裝係形成多個凸塊於晶片的焊墊上，而透過凸塊直接與基 板（Substrate)電性連接，相鲛於打線一以b〇ndmg)及軟片 =動貼合（TAB)方式’覆晶的電路路徑較短，具有甚佳的 每性品質；而覆晶晶片亦岢以設計成晶背裸露的形式，可 以提筒晶片散熱性。基於上述原因，覆晶晶片構裝普遍地 應用於半導體封裝產業中。 一請參照第1圖’其繪示習知迷你球格陣列構裝之剖 面不意圖。就製程上而言，首先提供一基板（未繪示），基 板具有多個基板單元110,在第丨圖中僅繪示出其中的一 個，並且基板單元110具有一第一基板表面120及—第二 基板表面uo，在第一基板袠面12〇上具有一晶片座124 及多個接合塾l22(m〇untlng pad)，而在第二基板表面ι3〇 上具有多個焊球帛132(baUpad)。並且提供多個晶片14〇， 在第1圖中僅繪不出其中的—個，晶片14〇具有—主動表 本紙張尺料fflTa m (cns)a4 (210 ---------------------訂—I------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 公釐）498529 A7 533twf.doc / 009 V. Description of the Invention (/) The present invention relates to a flip-chip package and its manufacturing process, and in particular to a flip-chip package and the like, without the need to form a reconfiguration circuit layer on a wafer and Its corresponding process. In today's information exploding society, electronic products are everywhere in daily life. No matter in food, clothing, living, and entertainment, fine products of integrated circuit components are used. With the continuous evolution of electronic technology, the functionality is more complex and humane products are being introduced. As far as electronic products are concerned, they are also oriented towards ', thin, small, and small faces' +. Therefore, in semi-hybrid packaging technology, we have developed Many high density semiconducting ___ types. The Fhp Chlp technology can achieve the above purpose. As the flip chip package system forms a plurality of bumps on the pads of the wafer, the bumps are directly and electrically connected to the substrate through the bumps. In the first wire bonding process, the chip-on-chip circuit path is short and has excellent persex quality; and the chip-on-chip is also designed to have a bare back. Can improve the heat dissipation of the tube wafer. For these reasons, flip-chip wafer fabrication is commonly used in the semiconductor packaging industry. Firstly, please refer to FIG. 1 ', which shows the cross-section of the conventional mini ball grid array structure. In terms of manufacturing process, a substrate (not shown) is first provided. The substrate has a plurality of substrate units 110. Only one of them is shown in the figure. The substrate unit 110 has a first substrate surface 120 and- The second substrate surface uo has a wafer holder 124 and a plurality of bonding pads 122 on the first substrate surface 120, and a plurality of solder balls 132 on the second substrate surface 1230. baUpad). And a plurality of wafers 14 are provided. Only one of them can not be drawn in the first figure. The wafer 14 has an active surface paper rule fflTa m (cns) a4 (210 --------- ------------ Order—I ------ line (please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
經濟部智慧財產局員工消費合作社印製 五、發明說明（]/) 面142及對應之一背面144，逝且在晶片14〇之主動表面 142還具有多個焊墊146。接下來進行一貼附之製程，將 每一晶片140以其背面144貼附對應之基板單元丨〗〇之晶 片座124上。然後進行一打線製程，打上多個導線15〇 = 焊墊146與接合墊122電性連接。接下來進行一封膠製程 (encapsulating)，一封裝材料160包覆晶片14〇、導線〗5〇、 基板110之第一表面120。然後進行一植入焊塊之製程， 將多個焊球植接於焊球墊132上。然後還要進行一單 ，（singUlating)之製程，將每—基板單元n〇及其對應之 紂裝材料丨60相互分離，使其形成獨立之構裝體1〇〇。 在上述的迷你球格陣列構裝中，由於晶片14〇之焊 土 146係藉由導線1 %與基板11 〇之接合墊I〗]電性連接。 如此訊號傳導的過程甚長，會有訊號衰減或延遲的發生， =其對於應用在高頻電路上，更會有嚴重的影響，而降低 晶片140之效能。 爲解決上述電性品質不良的問題，一種覆晶構裝及 其製程便硏發出來，如第2圖所示，其繪示習知覆晶構裝 之剖面承意圖。就製程上而言，首先提供一晶片210，晶 片210具有一主動表面212，而在晶片210之主動表面212 表層具有多個焊墊214。然後還要提供一基板220,基板22〇 具有〜基板表面222，而在基板表面222的表層還具有多 個f接點224)接下來會進行一製作重配置線路層之製程， 衣作·‘蔞配置線路層230(re-distribution layer)於晶片2 1 〇 Z主動袠面2〗2上，其中重配置線路層23〇係由一金屬結 本紙張尺度適用 (210 X 297 公釐） (請先閱讀背面之注咅？事項再填寫本頁) -I an aaBi n Λ§β «ϋ ϋ 一 1_ mamM MMmMm 線 經濟部智慧財產局員工消費合作社印製 498529 五、發明說明（、） ; 構體232及一絕緣體234所組合而成，而金屬結構體232' 交錯於絕緣體234之中，並且重配置線路層230還具有多 個凸塊墊236(bump pad)，透過金屬結構體232可以使焊‘ 墊214與凸塊墊236電性連接。然後再進行一製作凸塊的 製程，可以製作出多個凸塊240(bump)於凸塊墊236上。 .接下來，再進行一覆晶之製程，藉由迴焊的方法，會將重 配置線路層230上之凸塊240與基板220焊合，因而可以 使晶片210與基板220相互間固定並與其電性連接。接下 來，會進行一塡入塡充材料之製程’，將一塡充材料 25〇(underfill)塡入於重配置錄路層23〇與基板22〇間的細 縫中，並且塡充材料250會包覆凸塊240。然後進行一植 入焊球之製程，將多個焊球260植接於基板220之接點226 上。最後，再進行一單切製程，可以切割出多個獨立的封 裝體。 . 在上述的覆晶構裝中，雖然可以縮短晶片210之焊 墊214與基板220之接點224間的距離，而降低訊號衰減 或延遲的發生_率；但是由於上述凸塊240的作法，其形 成的體積會非常大，因而在焊合時，相鄰凸塊之間距(Pitch) 必須保持在200微米以上，才能確保相鄰的凸塊間不會短 路，故不能直接形成在晶片210之焊墊214上（其間距約 爲50微米）。因此一般的做法，會透過重配置線路層130 使凸塊墊236的配置能符合凸塊240的要求。故在上述的 覆晶製程中，還必須製作重配置線路曆230才能將晶片210 與基板220顺利地電性連接，其覆晶構裝製程甚爲繁雜且 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公楚） -------------------·丨訂--I--丨！ · 丨丨 (請先閱讀背面之注意事項再填寫本頁) •T * 經濟部智慧財產局員工消費合作社印製 498529 五、發明說明（AO ' 不具效率性。 … ’ 因此本發明的目的之一就是在提供一種覆晶構裝及 其製程，透過特殊的凸塊及基板的設計，可以將晶片直接 與印刷電路基板電性連接，而不再需藉由重配置線路層才 能達成，大幅提高覆晶封裝製程的效率。 本發明的目的之二就是在提供一種覆晶構裝及其製 程，透過特殊的凸塊設計，而縮減相鄰凸塊間的距離，可 以直接形成於晶片的焊墊上。 本發明的目的之三就是在提供一種覆晶構裝及其製 程，由於不需重配置線路層，而透過特殊的凸塊設計，可 以使晶片直接與基板電性連接，如此更縮短晶片與基板間 的距離，使訊號傳導路徑變爲更短，而更提高晶片與基板 間的電性品質。 爲達成本發明之上述和其他目的，提出一種覆晶構 裝’至少包括· 一^晶片’具有一^主動表面’在主動表面之 表層具有多個焊墊。一基板，具有一基板表面，基板表面 還具有一焊罩層及多個接點，而焊罩層具有至少一開口， 接點位於焊罩層之開口的區域，並且基板還具有一晶片置 放區域，晶片置放於基板之晶片置放區域上，而開口位於 晶片置放區域內。多個凸塊，固定於晶片之焊墊與基板之 接點間，每一凸塊具有一金屬柱及一焊塊，其中每一金屬 柱分別與每一焊塊電性接合，而金屬柱係位於靠近晶片的 一端，焊塊係位於靠近基板的-端。以及一塡充材料，位 於晶片與基板間，並11包覆凸塊。 本紙張尺度適用中國國家標準（CNS)A〗規格（210 X 297公爱） --------------裝--------訂--------·線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 498529 五、發明說明（g) 依照本發明的一較佳實施例，其中金屬柱與焊塊間 還具有一過渡體，而過渡體的截面積大於金屬柱的截面 積，並且過渡體的材質包括鎳’且過渡體在靠近金屬柱之 表面的邊緣暴露出具有一氧化鎳層。另外，覆晶構裝還包 括至少一支撐構件，位於晶片與基板之間，係用以支撐晶 片於基板上，而支撐構件的形狀係爲球狀。 本發明的特徵在於透過特殊的凸塊及基板，可以使 晶片上不需製作重配置線路層’即可以與基板電性連接。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： ， 圖式之簡單說明： ’ 第1圖繪示繪示習知迷你球格陣列構裝之剖面示意 圖。 第2圖繪示習知覆晶構裝之剖面示意圖。 、 第3圖至第9圖繪示依照本發明一較佳實施例的一 種覆晶晶片製程對應於凸塊部份之剖面放大示意圖° 第10圖繪示依照本發明一較佳實施例的基板俯視 示意圖。 第10A圖繪示對應於第10圖中基板之剖面線1 1 之剖面示意圖。 第10B圖繪示晶片上支撐構件之剖面示意圖。 第11圖至第13圖繪示依照本發明其他較佳實施例 之開U位置不意圖。 7 本紙張尺度適用中國國家標準（CNS)Al規格（21〇 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) -衣-------^•丨訂---------線| 498529 ^533twf.doc/〇〇9 77 A7 B7 發明說明（\〇 ) 第1 4圖繪示依照本發明覆晶構裝之剖面示意圖。 第〗5圖繪不依照本發明另一較佳實施例之一種半 導體晶片構裝。 第1 6圖繪示依照本發明再一較佳實施例之一種半 導體晶片構裝。 圖式之標示說明： 200、800 :封裝體 220、400、500、600、700 ' 820、920 ' 1020 ··基 板 410 :底層 420 :圖案線路層 430、530、630、730、840 :焊罩層 432、532a、532b、632、732a、732b、832 :開口 440、540、640、740 :晶片置放區域 450、550、650、750 :支撐構件 222 :基板表面 224 、 422 、 522a 、 522b 、 622 、 722a 、 722b 、 830 : 經濟部智慧財產局員工消費合作社印製 接點 110 :基板單元 120 :第一基板表靣 122 :接合墊 124 :晶片座 130 :第二基板表面 8 本紙張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印刹衣 498529 五、發明說明（>c\ ) 132 :焊球墊 140、210、310、810、910、1010 :晶片 142、212、312 :主動表面. 146、214、316、812 :焊墊 M4 :保護層 144 :背面 > 320 :阻障層 322 :阻障體 3 2 6 :種子層 328 :種子體 330 :光阻 332 :貫孔’ 340、874 :金屬柱 3 4 2 :周圍表面 350 :過渡體 352 :下表面 354 :上表面 356 :側邊 240、370、870、970 :凸塊 230 :重配置線路層 232 :金屬結構體 234 :絕緣體 236 :凸塊墊 150 :導線 ------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 498529 7533twf.doc/009 __B7__ 五、發明說明（幺） 160、980、1080 :封裝材料 300 ' 872 :焊塊 170 :焊球 250、880、1082 :塡充材料 d:距離 實施例 請參照第3圖至第9圖，其繪示依照本發明一較佳 實施例的一種覆晶晶片製程對應於凸塊部份之剖面放大示 意圖。請先參照第3圖，首先提供一晶片310，晶片310 具有一主動表面312，而晶片310之主動表面312具有一 保護層314及多個焊墊316(僅繪示出其中的一個），並且 保護層314暴露出焊墊316，晶片310可以透過焊墊316 與外界電路（未繪示）電性連接。 請參照第4圖，接下來進行一製作阻障層製程，以 濺鏟的方式將一阻障層320形成於晶片310之主動表面312 上，而阻障層320會覆蓋焊墊316及保護層314，阻障層 的材質可以是鎢化鈦（TiW)、鈦（Ti)或鉻（C〇等金屬，其厚 度約爲1000埃左右。然後再進行一製作種子層製程，以 濺鍍的方式，形成一種子層326(seed layer)於阻障層320 上，而種子層326·的材質係爲銅。接下來進行一微影製程， 首先將一光阻330形成於種子層326上，然後透過曝光.、 顯影等步驟，將一圖案（未繪示）轉移至光阻330，使得光 阻330形成多個貫孔332(僅繪示出其中的一個），而貫孔332 10 本紙張尺/ΐ適用中國國家標準（CNS)A4規格（2】0 X 297公釐) ' ------------裝--------訂----丨丨—丨-線_ (請先閱讀背面之注意事項再填寫本頁) 7533twf.doc/009 A7 7533twf.doc/009 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（cp r 的位置對應於焊墊316的區域。 請參照第5圖，接下來進行一製作金屬柱製程，可 . 、 ’ 藉由電鍍的方式，製作多個金屬柱340(僅繪示出其中的一 個‘)於貫孔332內，使金屬柱340分別配置於對應之焊墊316 上。金屬柱340·的高度約介於1〇微米至100微米之間， 而其材質可以是銅。然後進行一製作過渡體製程，可透過 電鍍的方式製作多個過渡體350(僅繪示出其中的一個）於 金屬柱340上，而過渡體350的高度約介於1微米至1〇 微米之間，其材質可以是鎳。然後進行一製作焊塊之製程’ 可以藉由電鍍的方式，製作多個焊塊360(僅繪示出其中的 一個）於過渡體350上，而焊塊360的材質可以是錫鉛合 金。 請參照第5圖、第6圖，接下來進行一除去光阻製 程，將光阻330從種子層326上剝除。 請參照第7圖，然後進行一去除部份金屬柱製程’ 透過濕蝕刻的方式，從金屬柱340之側邊進行蝕刻，使金 屬柱340的截面積小於過渡體350的截面積，也使得過渡 體350的下表面352邊緣暴露於外。而距離d係爲過渡體 邊緣至金屬柱邊緣的最短距離，此距離最好大於0.2微米。 如此暴露於外的過渡體350與金屬柱340，會與空氣進行 氧化，其中過渡體350的側邊356及其下表面352邊緣會 形成一鎳氣化物層，.而金屬柱340的周圍表面342會形成 -銅氧化物層。若是再進行一熱氧化（Thermal Oxidation) 製程，可以使過渡體350及金屬柱340暴露於外的區域氧 ----— II----#裝·;!------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 498529 7 5 3 3 twf . doc/ 009 經濟部智慧財產局員工消費合作社印製 A7 _____—^______— 發明說明（v° ) 化更完全。或者亦可以將金屬柱340及過渡體350浸於氧 化_中，以達到氧化的目的，其中氧化劑可以是雙氣水。 請參照第7圖、第8圖.，接下來進行一蝕刻表面製 程，比如藉由反應性離子餓刻（Reactive IolV Etch ’ 方式，將種子層326及阻障層320在未對應於金屬柱340 的區域去除，而分別形成獨立分開的種子體328及阻障體 322 〇 請參照第9圖，最後進行一迴焊製程，利用加熱的 方式使焊塊360軟化而成類似球體之形·狀’如此凸塊370 的製作即完成，凸塊37()係由阻障體,322、種子體328、 金屬柱340、過渡體350、焊塊360所組成，而晶片310 可以透過凸塊370與基板（未繪示）電性連接。然而就鎳與 錫鉛合金的金屬特性而言，鎳與錫鉛合金相互間的表面張 力甚小，因此錫鉛合金會在鎳金屬的表面上快速擴散流 動；然而鎳的氧化物與錫鉛合金相互間的表面張力甚大’ 因此錫鉛合金不易在鎳氧化物的表面上快速擴散流動’而 聚集在一起。在進行此迴焊製程時，由於過渡體350的側 邊356及下表面352的邊緣暴露於外，並且過渡體350的 材質係爲鎳，而鎳會與氧作用而形成鎳的氧化物’因此加 熱軟化時的焊塊360不會流至過渡體350的側邊356及其 下表面352，而黏附在過渡體350的上表面354。同時焊 塊360與過渡體3 50間的互溶速度不能太快，否則焊塊360 也容易從金屬柱340上崩潰下來，因此過渡體350必須要 有足夠的厚度以承受焊塊360在迴焊時與過渡體350產生 本紙張尺度適用中國國家標準（C^S)A4規ίΓ(2】0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 498529 五、發明說明（Λ) ' 的互溶效果。 而過渡體350的材質並非只限於鎳.，亦可以是複合 材料，由多層金屬所疊合而成，·只要是位於上表面、354的 金屬能夠與焊塊360互溶’而位於下表面352的金屬是不 易與焊塊360互溶的金屬即可。 然而在上述製程中，即使過渡體及金屬柱暴露於外 的表面沒有氧化的情形發生’在進行迴焊的時候，焊塊就 可以順利地形成在過渡體上。但是一般而言，過渡體及金 屬柱均會在凸塊製作過程中氧化，如此更可以確保在迴焊 時焊塊不會從金屬柱上崩潰下來。然而若是再進行一道熱 氧化製捏，使過渡體及金屬柱暴露於外的區域氧化更完 全’如此更可以進一步確保其在迴焊時，焊塊不會滑落到 過渡體邊緣及其下表面。 ’ &上述製程中在阻障層與金屬柱之間係具有一種子 ® ’由於金屬柱與種子層的材質均爲銅，因此金屬柱與種 子層的接合性甚佳；然而亦可以不需製作此種子層，將金 屬柱直接形成於阻障層上，只是金屬柱與阻障層的接合性 會較差。 然而爲了能夠藉由上述的凸塊，晶片能順利地與基 板電性連接，因此在基板的設計上，必須做一些調整，如 第10圖及第10Α圖，其中第10圖繪示依照本發明一較佳 實施例的基板俯視示意圖，而第10Α圖繪示對應於第1〇 圖中基板之剖面線〖I之剖面示意圖。一基板400包括一 底層410、一圖案線路層420及一焊罩層430，其中圖案 本紙張尺度適財國⑽χ 297公爱） ------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 498529 五、發明說明（γν) (請先閱讀背面之注意事項再填寫本頁) 線路層420位於底層410上，而圖案線路層420包括多個 接點422 ;另外，焊罩層430具有一開口 432，暴露出多 個接點422。此外，基板400具有一晶片置放區域440， 而晶片置放區域440定義爲晶片（未繪示）與基板400焊合 後，晶片垂直投影至基板400上的區域；而開口 432位於 晶片置放區域440內中間的位置。 經濟部智慧財產局員工消費合作社印製 請參照第1〇圖及第i〇B圖，其中第10Β圖繪示晶 片上支撐構件之剖面示意圖。在晶片310與基板400進行 焊合之前，還可以製作多個支撐構件450於晶片310之主 動表面312上，其製作過程係與在製作凸塊時同步並且與 其製作過程是相同的’亦即在製作完成凸塊的同時亦製作 完成支撐構件450,如此凸塊的高度會大致等於支撐構件 450的高度，而支撐構件450之結構亦與凸塊之結構雷同， 由上而下分別是焊塊451、過渡體452、金屬柱453、種子 體454、阻障體455，而阻障體455係形成在晶片310之 保護層314上。當晶片310焊合於基板400上之後，透過 支撐構件450可以支撐晶片310於基板400上，而支撐構 件450除了支撐晶片310的功能之外，還具有提高晶片310 散熱效率的功能。其中第10圖之虛線區域係爲晶片310 與基板400焊合後，支撐構件450所在的位置。 在前述的實施例中，開口僅只有一個，並且位於基 板之晶片置放區域的中間位置。然而，本發明之開口形式 及位置並非侷限於上述的方式，亦可以是其他方式。請參 見第11圖至第13圖，其繪示依照本發明其他較佳實施例 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 498529 五、發明說明（\、） 之開口位置示意圖。如第11圖所示，焊罩層530具有二 開口 532a、532b，雙排排列於晶片置放區域540中間的位 置，並且分別暴露出多個接點522a、522b，而其中一開口 532a內的接點522a與另一開口 532b內的接點522b之相 互間排列關係係爲交錯排列的關係；再者’圖中之虛線區 域550係爲晶片與基板500焊合後，支撐構件所在的位置， 支撐構件係配置在靠近晶片之主動表面周圍區域的位置。 另外，如第12圖所示，焊罩層630具有一開口 632，其係 爲環型的樣式，位於晶片置放區域640的邊緣位置，並且 暴露出多個接點622，而接點622亦爲環型的排列；此外， 圖中之虛線區域650係爲晶片與基板600焊合後，支撐構 件所在的位置，支撐構件係配置於晶片之主動表面中間位 置。再者，如第13圖所示，焊罩層730具有二開口 732&、 732b，分別暴露出多個接點722a、722b，而二開口 732a、 732b分別位於晶片置放區域740對應之兩側的邊緣位置； 另外，圖中之虛線區域750係爲晶片與基板7〇〇焊合後’ 支撐構件所在的位置，而支撐構件750係配置於晶片之主 動表面中間位置。 請參照第14圖，其繪示依照本發明覆晶構裝之剖 面示意圖。當晶片81 0植上凸塊870後，便可以與基板820 進行焊合的製程，其中基板820的形式如前所述’在接點 83〇附近的區域並未有焊罩層840，在進行焊合製私之後’ 焊塊872會與接點83〇焊合。接下來，便進行一媳入填充 祠料之製程’而1¾¾充材料880包覆凸塊87〇及按>1 本紙張尺度適用中國國家標準（CNS)A4規格（2l〇x 297公t ) 7丨裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 498529 i、發明說明（νΛ〇 周圍。然後進行一植入焊球之製程，將多個焊球890植接 於基板820之接點826上。最後，再進行一單切製程，可 以切割出多個獨立的封裝體800。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 請參照第14圖，在上述的製程中，由於凸塊870 係由焊塊872、過渡體（未繪示）及金屬柱874所組成，因 此可以大幅地減少凸塊870的體積，同時可以縮短相鄰凸 塊870間的距離，而趨近於晶片810上相鄰焊墊812間所 允許的間距，如此可以直接將凸塊870形成於焊墊上，並 且直接透過凸塊870與基板820電性接合，而不再需製作 重配置線路層，可大幅增進製程效率。由於上述的覆晶構 裝，可以完全不需製作重配置線路層，只需透過凸塊870 即可完成晶片810與基板820間的電性連接，如此更縮短 晶片810與基板820間訊號傳導的路徑，更提高晶片810 與基板820間的電性品質。此外，由於本發明可以透過金 屬柱874將晶片810與基板820間的距離墊得更高，並且 金屬柱874的線徑甚細微，再者，金屬柱874所使用的材 質爲銅，銅的延展性甚佳，如此凸塊870可以容忍晶片810 與基板820間因熱而產生之較大的變形，提高晶片810與 基板820接合的可靠度。並且由於本發明將位於接點830 附近的焊罩層840去除，而形成開口 832，如此晶片810 與基板820間的間距會增加，因而在進行覆晶製程時，可 以較容易且迅速地塡入一塡充材料880於晶片810與基板 間。而藉由金屬柱874墊高後的晶片810，當晶片810與 基板820迴焊焊合後，淸洗液也較容易流入到晶片810與 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 498529 7533twf.d〇c/〇〇9 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（\$) 基板82〇間的縫隙，如此可以將迴焊製程後所殘留的助焊 劑（flux)淸除得較乾淨。 ㈣本發明的封裝方式亦可以是其_的形式，如第 b圖所示，其繪示依照本發明另〜較佳實施例之〜種半道 體晶片構裝。在晶片9H)與基板92〇電性接合之後，^ 以進行一封膠之製程，使一封裝材料MO包覆晶片91〇 凸塊970。另外，如第16圖所示，其繪示依照本發明再一 較佳實施例之一種半導體晶片構裝。當塡充材料1〇82墳 充於晶片1010與基板1020之間後，還可以利用〜封裝^ 料1080將晶片1010及塡充材料log〗包覆住。 綜上所述，本發明至少具有下列優點： 1. 本發明之覆晶構裝，由於凸塊係由焊塊、過渡鸺 及金屬柱所組成，因此可以大幅地減少凸塊的體積，同時 可以縮短相鄰凸塊間的距離，而趨近於晶片相鄰焊塾_# 允許的間距，如此可以直接將凸塊形成於焊塾上，並I胃 接透過凸塊與基板電性接合，而不再需製作重配置，線足各 層，可大幅增進製程效率。 2. 本發明之覆晶構裝，由於可以完全不需製作重配 置線路層，只需透過凸塊即可完成晶片與基板間的電丨生_ 接，如此更縮短晶片與基板間訊號傳導的路寧，更提 片與基板間的電性品質。. 3. 本發明之覆晶構裝，由於本發明可以透過金屬柱 將晶片與基板間的距離墊得更高，並且金.屬柱的線徑甚糸田 -，再者，金屬柱所使用的材質爲銅，銅的延展性甚佳， 17 本紙張尺度適用中國國家標準（CNSW1規格（21〇χ 297公餐） (請先閱讀背面之注意事項再填寫本頁} I裝 ----訂---------線* 498529 A7 B7 S33twf.doc/009 五、發明說明（\>) 如此凸塊可以容忍晶片與基板間因熱而產生之較大的變 形，提高晶片與基板接合的可靠度。 4. 本發明之覆晶構裝，由於將位於接點附近的焊罩 層去除，而形成開口，如此晶片與基板間的間距會增加， 因而在進行覆晶製程時，可以較容易且迅速地塡入一塡充 材料於晶片與基板間。 5. 本發明之覆晶構裝，由於藉由金屬柱墊高後的晶 片，當晶片與基板迴焊焊合後，淸洗液也較容易流入到晶 片與基板間的縫隙，如此可以將迴焊製程後所殘留的助焊 劑淸除得較乾淨。 雖然本發明已以一較佳實施例揭露如上，然 其並非用以限定本發明，任何熟習此技藝者，在不脫離本 發明之精神和範圍內，當可作些許之更動與潤飾，医|此本 發明之保護軔圍當視後附之申請專利範圍所界定者胃、准。 ------------裝--------訂--------•線. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 張 紙 S) N (C 準 標Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention [] /) A surface 142 and a corresponding one of the back surface 144, and the active surface 142 on the chip 140 also has a plurality of pads 146. Next, an attaching process is performed, and each wafer 140 is attached to the corresponding wafer unit 124 of the substrate unit 丨 〇 0 with its back surface 144. Then, a wire process is performed, and a plurality of wires 15 are applied. The solder pad 146 is electrically connected to the bonding pad 122. Next, an encapsulating process is performed. An encapsulating material 160 covers the wafer 14, the wires 50, and the first surface 120 of the substrate 110. Then, a solder implantation process is performed, and a plurality of solder balls are implanted on the solder ball pad 132. Then, a single (SingUlating) process is performed to separate each substrate unit n0 and its corresponding mounting material 60 from each other to form an independent structure 100. In the above-mentioned mini ball grid array configuration, the solder 146 of the wafer 14 is electrically connected to the bonding pad I of the substrate 110 through a wire 1%]. In this way, the process of signal transmission is very long, and signal attenuation or delay will occur, which will have a serious impact on the application in high-frequency circuits, and reduce the performance of the chip 140. In order to solve the above-mentioned problem of poor electrical quality, a flip-chip structure and its manufacturing process have been developed. As shown in FIG. 2, it shows the cross-section bearing intention of the conventional flip-chip structure. In terms of manufacturing process, a wafer 210 is first provided. The wafer 210 has an active surface 212, and a plurality of bonding pads 214 are provided on the surface of the active surface 212 of the wafer 210. Then, a substrate 220 is provided. The substrate 22 has a substrate surface 222, and the surface layer of the substrate surface 222 also has a plurality of f contacts 224.) Next, a process for making a reconfigured circuit layer will be performed.蒌 Configure a circuit layer 230 (re-distribution layer) on the chip 2 1 〇Z active surface 2 〖2, of which the reconfiguration circuit layer 23 is a metal paper size (210 X 297 mm) (Please First read the note on the back? Matters and then fill out this page) -I an aaBi n Λ§β «ϋ 1 1_ mamM MMmMm Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498529 5. Invention Description (,); Structure 232 and an insulator 234 are combined, and the metal structure 232 'is staggered in the insulator 234, and the reconfiguration circuit layer 230 also has a plurality of bump pads. The metal structure 232 can be used for soldering. The pad 214 is electrically connected to the bump pad 236. Then, a bump manufacturing process is performed, and a plurality of bumps 240 (bumps) can be manufactured on the bump pad 236. Next, a flip-chip process is performed, and the bump 240 on the reconfiguration circuit layer 230 is soldered to the substrate 220 by a reflow method, so that the wafer 210 and the substrate 220 can be fixed to each other and connected to it. Electrical connection. Next, a process of filling a filling material will be performed. A filling material 25 ° (underfill) is inserted into the fine gap between the reconfiguration recording layer 23 and the substrate 22, and the filling material 250 is filled. Will cover the bump 240. Then, a solder ball implantation process is performed, and a plurality of solder balls 260 are implanted on the contacts 226 of the substrate 220. Finally, a single cutting process can be performed to cut multiple independent packages. In the above flip-chip structure, although the distance between the pads 214 of the wafer 210 and the contacts 224 of the substrate 220 can be shortened, and the occurrence rate of signal attenuation or delay is reduced; however, due to the method of the bump 240 described above, The volume formed by it will be very large. Therefore, the pitch between adjacent bumps must be kept above 200 microns during welding, so as to ensure that there is no short circuit between adjacent bumps, so it cannot be directly formed on the wafer 210. On pads 214 (with a pitch of about 50 microns). Therefore, in general, the configuration of the bump pads 236 can meet the requirements of the bumps 240 by reconfiguring the circuit layer 130. Therefore, in the above-mentioned flip-chip manufacturing process, a reconfiguration circuit calendar 230 must also be made to successfully electrically connect the chip 210 and the substrate 220. The flip-chip structure manufacturing process is very complicated and this paper standard applies to the Chinese National Standard (CNS) A4 size (210 x 297 cm) ------------------- · 丨 Order--I-- 丨! · 丨 丨 (Please read the notes on the back before filling out this page) • T * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 498529 V. Description of the invention (AO 'Not efficient.…' Therefore, one of the objects of the present invention It is to provide a flip-chip structure and its process. Through the design of special bumps and substrates, the chip can be electrically connected directly to the printed circuit board without the need to reconfigure the circuit layer to achieve a significant increase in coverage. The efficiency of the chip packaging process. Another object of the present invention is to provide a flip-chip structure and its process. Through the special bump design, the distance between adjacent bumps can be reduced, which can be directly formed on the bonding pads of the wafer. The third object of the present invention is to provide a flip-chip structure and a manufacturing process thereof. Since the circuit layer is not required to be reconfigured, the special bump design allows the chip to be electrically connected directly to the substrate, thus shortening the chip and the substrate even more. The distance between them makes the signal conduction path shorter, and improves the electrical quality between the chip and the substrate. To achieve the above and other objectives of the invention, A flip-chip structure including at least a wafer having an active surface has a plurality of pads on the surface of the active surface. A substrate has a substrate surface, and the substrate surface also has a solder mask layer and a plurality of Contact, and the solder mask layer has at least one opening, the contact is located in the region of the opening of the solder mask layer, and the substrate also has a wafer placement area, the wafer is placed on the wafer placement area of the substrate, and the opening is located on the wafer placement area A plurality of bumps are fixed between the pads of the wafer and the contacts of the substrate. Each bump has a metal pillar and a solder bump, wherein each metal pillar is electrically connected to each solder bump. The metal pillars are located at one end near the wafer, and the solder bumps are located at the-end near the substrate. And a filling material is located between the wafer and the substrate, and 11 is covered with bumps. This paper size applies to Chinese National Standard (CNS) A 〖Specifications (210 X 297 public love) -------------- install -------- order -------- · line (please read the note on the back first) Please fill in this page for further information.) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. g) According to a preferred embodiment of the present invention, a transition body is further provided between the metal pillar and the solder bump, and the cross-sectional area of the transition body is greater than the cross-sectional area of the metal pillar, and the material of the transition body includes nickel and the transition body is A nickel oxide layer is exposed near the edge of the surface of the metal pillar. In addition, the flip-chip structure further includes at least one supporting member located between the wafer and the substrate for supporting the wafer on the substrate, and the shape of the supporting member is It is spherical. The present invention is characterized in that through special bumps and the substrate, the wafer can be electrically connected to the substrate without the need to make a reconfiguration circuit layer on the wafer. In order to make the above and other objects, features, and The advantages are more obvious and easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings. The simple description of the drawings is as follows: 'Figure 1 shows a conventional mini ball grid array structure. Schematic cross-section of the device. FIG. 2 is a schematic cross-sectional view of a conventional flip chip structure. Figures 3 to 9 are enlarged schematic cross-sectional views corresponding to bumps of a flip-chip wafer process according to a preferred embodiment of the present invention. Figure 10 shows a substrate according to a preferred embodiment of the present invention. Top view schematic. FIG. 10A is a schematic cross-sectional view corresponding to the section line 1 1 of the substrate in FIG. 10. FIG. 10B is a schematic cross-sectional view of a supporting member on a wafer. Figures 11 to 13 illustrate the open U position according to other preferred embodiments of the present invention. 7 This paper size applies the Chinese National Standard (CNS) Al specification (21〇X 297) (Please read the precautions on the back before filling this page) -Clothing ------- ^ • 丨 Order --- ------ line | 498529 ^ 533twf.doc / 〇〇9 77 A7 B7 Description of the invention (\ 〇) Figure 14 shows a schematic cross-sectional view of a flip-chip structure according to the present invention. FIG. 5 shows a semiconductor wafer structure not according to another preferred embodiment of the present invention. Figure 16 shows a semiconductor wafer structure according to yet another preferred embodiment of the present invention. Description of the drawing labels: 200, 800: Packages 220, 400, 500, 600, 700 '820, 920' 1020 ... · Substrate 410: Bottom layer 420: Patterned circuit layer 430, 530, 630, 730, 840: Solder cover Layers 432, 532a, 532b, 632, 732a, 732b, 832: openings 440, 540, 640, 740: wafer placement areas 450, 550, 650, 750: support members 222: substrate surfaces 224, 422, 522a, 522b, 622, 722a, 722b, 830: Contacts printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 110: Substrate unit 120: First substrate table 靣 122: Bonding pad 124: Wafer holder 130: Second substrate surface 8 This paper size applies China National Standard (CNS) Al specification (210 X 297 mm) Printed clothing for consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economy 498529 V. Description of the invention (&c;) 132: Solder ball pad 140, 210, 310, 810, 910, 1010: Wafer 142, 212, 312: Active surface. 146, 214, 316, 812: Pad M4: Protective layer 144: Back side> 320: Barrier layer 322: Barrier body 3 2 6: Seed layer 328 : Seed body 330: Photoresist 332: Through hole '340, 874: Metal post 3 4 2: Surrounding surface 350 : Transition body 352: Lower surface 354: Upper surface 356: Side 240, 370, 870, 970: Bump 230: Reconfigured wiring layer 232: Metal structure 234: Insulator 236: Bump pad 150: Wire --- --------- Installation -------- Order --------- Line (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards ( CNS) A4 size (210 x 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 498529 7533twf.doc / 009 __B7__ V. Description of the invention (幺) 160, 980, 1080: Packaging material 300 '872: Solder block 170 : Solder ball 250, 880, 1082: filling material d: distance embodiment Please refer to FIG. 3 to FIG. 9, which shows a flip-chip wafer manufacturing process corresponding to a bump portion according to a preferred embodiment of the present invention The enlarged schematic diagram of the section. Please refer to FIG. 3 first, a wafer 310 is provided, the wafer 310 has an active surface 312, and the active surface 312 of the wafer 310 has a protective layer 314 and a plurality of pads 316 (only one of which is shown), and The protective layer 314 exposes the bonding pad 316, and the chip 310 can be electrically connected to an external circuit (not shown) through the bonding pad 316. Please refer to FIG. 4. Next, a barrier layer manufacturing process is performed. A barrier layer 320 is formed on the active surface 312 of the wafer 310 by a shovel, and the barrier layer 320 will cover the pad 316 and the protective layer. 314. The material of the barrier layer may be titanium tungsten (TiW), titanium (Ti), or chromium (C0), and the thickness is about 1000 angstroms. Then, a seed layer manufacturing process is performed, and a sputtering method is used. A seed layer 326 is formed on the barrier layer 320, and the material of the seed layer 326 · is copper. Next, a lithography process is performed, and a photoresist 330 is first formed on the seed layer 326, and then Through the steps of exposure, development, etc., a pattern (not shown) is transferred to the photoresist 330, so that the photoresist 330 forms a plurality of through holes 332 (only one of which is shown), and the through holes 332 10 paper rule / ΐApplicable to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) '------------ Installation -------- Order ---- 丨 丨 —丨 -line_ (Please read the notes on the back before filling out this page) 7533twf.doc / 009 A7 7533twf.doc / 009 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 Explanation (The position of cp r corresponds to the area of the solder pad 316. Please refer to Figure 5, and then proceed to a process of making metal pillars. You can make multiple metal pillars 340 by electroplating (only shown) One of them is') arranged in the through hole 332 so that the metal pillars 340 are respectively arranged on the corresponding pads 316. The height of the metal pillars 340 · is between about 10 micrometers and 100 micrometers, and the material can be copper. Then, a transition process is performed. A plurality of transition bodies 350 (only one of which is shown) can be fabricated on the metal pillars 340 by electroplating. The height of the transition bodies 350 is about 1 μm to 10 μm. In the meantime, the material can be nickel. Then, a process for making solder bumps can be performed by electroplating, and a plurality of solder bumps 360 (only one of which is shown) is formed on the transition body 350, and the solder bumps 360 The material can be tin-lead alloy. Please refer to Figure 5 and Figure 6, and then perform a photoresist removal process to strip the photoresist 330 from the seed layer 326. Please refer to Figure 7 and then perform a removal Metal pillar process' through wet etching, from The side of the metal pillar 340 is etched so that the cross-sectional area of the metal pillar 340 is smaller than that of the transition body 350, and the edge of the lower surface 352 of the transition body 350 is exposed. The distance d is from the edge of the transition body to the edge of the metal pillar. The shortest distance is preferably greater than 0.2 micrometers. The transition body 350 and the metal pillars 340 thus exposed to the outside will be oxidized with air, and the side 356 of the transition body 350 and the edge of the lower surface 352 will form a nickel gas. A copper oxide layer is formed on the surrounding surface 342 of the metal pillar 340. If a thermal oxidation process is performed again, the transition body 350 and the metal pillar 340 can be exposed to oxygen outside the area .-------- II ---- # 装 ·;! ------ Order- -------- Line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) 498529 7 5 3 3 twf .doc / 009 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _____— ^ ______— The description of the invention (v °) is more complete. Alternatively, the metal pillars 340 and the transition body 350 can also be immersed in oxidation to achieve the purpose of oxidation, wherein the oxidant can be double gas water. Please refer to FIG. 7 and FIG. 8. Next, an etching surface process is performed. For example, by using a reactive ion etching (Reactive IolV Etch 'method), the seed layer 326 and the barrier layer 320 are not corresponding to the metal pillar 340. The area is removed, and the seed body 328 and the barrier body 322 are formed separately. Please refer to FIG. 9. Finally, a reflow process is performed, and the soldering block 360 is softened into a ball-like shape and shape by heating. The production of the bump 370 is completed. The bump 37 () is composed of a barrier body, 322, a seed body 328, a metal pillar 340, a transition body 350, and a solder bump 360. The wafer 310 can pass through the bump 370 and the substrate. (Not shown) Electrical connection. However, as far as the metal properties of nickel and tin-lead alloy are concerned, the surface tension between nickel and tin-lead alloy is very small, so the tin-lead alloy will quickly diffuse and flow on the surface of nickel metal; However, the surface tension between the nickel oxide and the tin-lead alloy is very large, so the tin-lead alloy does not easily diffuse and flow on the surface of the nickel oxide, and gathers together. During this reflow process, due to the transition body 350's Side The edges of 356 and the lower surface 352 are exposed to the outside, and the material of the transition body 350 is nickel, and nickel will interact with oxygen to form nickel oxides. Therefore, the solder bump 360 during heating and softening will not flow to the transition body 350. The side 356 and its lower surface 352 adhere to the upper surface 354 of the transition body 350. At the same time, the mutual dissolution rate between the solder bump 360 and the transition body 350 cannot be too fast, otherwise the solder bump 360 will easily collapse from the metal pillar 340 Therefore, the transition body 350 must have sufficient thickness to withstand the soldering block 360 produced with the transition body 350 during re-soldering. The paper size is applicable to the Chinese National Standard (C ^ S) A4 rule. Γ (2) 0 X 297 mm) ( Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 498529 V. Description of the invention (Λ) 'The miscibility effect. The material of the transition body 350 is not limited to nickel. It can also be The composite material is made of multiple layers of metal. As long as the metal on the upper surface, 354 can be miscible with the solder bump 360, and the metal on the lower surface 352 is a metal that is not easily miscible with the solder bump 360. However, in the In the above process, The surface of the transition body and the metal pillar is not oxidized. 'When the reflow is performed, the solder bump can be smoothly formed on the transition body. However, generally, the transition body and the metal pillar are convex. The block is oxidized during the production process, so that it can ensure that the block does not collapse from the metal pillar during reflow. However, if a thermal oxidation process is performed, the transition body and the exposed area of the metal pillar will be more fully oxidized. This can further ensure that during reflow, the solder bump will not slip to the edge of the transition body and its lower surface. '&Amp; In the above process, there is a kind of sub-layer between the barrier layer and the metal pillar. The material of the seed layer is copper, so the bonding between the metal pillar and the seed layer is very good; however, it is not necessary to make the seed layer, and the metal pillar can be directly formed on the barrier layer, but the junction of the metal pillar and the barrier layer Sex will be poor. However, in order to be able to electrically connect the wafer to the substrate smoothly through the above-mentioned bumps, some adjustments must be made in the design of the substrate, such as FIG. 10 and FIG. 10A, where FIG. 10 illustrates the method according to the present invention. A schematic plan view of a substrate according to a preferred embodiment, and FIG. 10A is a schematic cross-sectional view corresponding to a cross-sectional line I of the substrate in FIG. 10. A substrate 400 includes a bottom layer 410, a patterned circuit layer 420, and a solder mask layer 430, wherein the patterned paper size is suitable for financial countries (⑽297). ---- Order --------- line (please read the precautions on the back before filling this page) 498529 5. Description of the invention (γν) (please read the precautions on the back before filling this page) The layer 420 is located on the bottom layer 410, and the pattern circuit layer 420 includes a plurality of contacts 422. In addition, the solder mask layer 430 has an opening 432, and the plurality of contacts 422 are exposed. In addition, the substrate 400 has a wafer placement area 440, and the wafer placement area 440 is defined as a region where the wafer (not shown) is welded to the substrate 400 and the wafer is vertically projected onto the substrate 400; and the opening 432 is located on the wafer placement The middle position in the area 440. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 10 and Figure 10B. Figure 10B shows a schematic cross-sectional view of the supporting members on the wafer. Before the wafer 310 and the substrate 400 are welded, a plurality of supporting members 450 can also be fabricated on the active surface 312 of the wafer 310. The manufacturing process is synchronized with and is the same as the manufacturing process of the bumps. The supporting member 450 is also manufactured at the same time as the bumps are manufactured, so that the height of the bumps will be approximately equal to the height of the supporting members 450, and the structure of the supporting members 450 is the same as the structure of the bumps, and the soldering blocks 451 from top to bottom , The transition body 452, the metal pillar 453, the seed body 454, and the barrier body 455, and the barrier body 455 is formed on the protective layer 314 of the wafer 310. After the wafer 310 is welded on the substrate 400, the wafer 310 can be supported on the substrate 400 through the supporting member 450. In addition to the function of supporting the wafer 310, the supporting member 450 can also improve the heat dissipation efficiency of the wafer 310. The dotted area in FIG. 10 is the position where the supporting member 450 is located after the wafer 310 and the substrate 400 are welded. In the foregoing embodiment, there is only one opening, and it is located in the middle of the wafer placement area of the substrate. However, the form and position of the opening of the present invention are not limited to the above-mentioned methods, and may be other methods. Please refer to FIG. 11 to FIG. 13, which show that according to other preferred embodiments of the present invention. 14 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). System 498529 V. Schematic diagram of the opening position of the invention description (\,). As shown in FIG. 11, the solder mask layer 530 has two openings 532 a and 532 b, and two rows are arranged in the middle of the wafer placement area 540, and a plurality of contacts 522 a and 522 b are respectively exposed. The arrangement relationship between the contact point 522a and the contact point 522b in the other opening 532b is a staggered relationship; Moreover, the dotted line area 550 in the figure is the position where the support member is located after the wafer and the substrate 500 are welded. The support member is disposed near the area around the active surface of the wafer. In addition, as shown in FIG. 12, the solder mask layer 630 has an opening 632, which is a ring-shaped pattern, which is located at the edge of the wafer placement area 640, and exposes a plurality of contacts 622, and the contacts 622 are also It is a ring-shaped arrangement. In addition, the dotted area 650 in the figure is the position where the support member is located after the wafer and the substrate 600 are welded, and the support member is arranged at the middle position of the active surface of the wafer. Furthermore, as shown in FIG. 13, the solder mask layer 730 has two openings 732 & 732b, respectively, a plurality of contacts 722a and 722b are exposed, and the two openings 732a and 732b are respectively located on two sides corresponding to the wafer placement area 740. In addition, the dashed area 750 in the figure is the position where the support member is located after the wafer and the substrate are welded, and the support member 750 is disposed at the middle position of the active surface of the wafer. Please refer to FIG. 14, which is a schematic cross-sectional view of a flip-chip assembly according to the present invention. After the wafer 810 is implanted with the bump 870, the bonding process with the substrate 820 can be performed. The form of the substrate 820 is as described above. 'There is no solder mask layer 840 in the area near the contact point 83. After welding, the solder joint 872 will be welded with the contact 83. Next, a process of filling the ancestral material is carried out, and 1¾¾ filling material 880 covers the bumps 87 °, and according to the> 1 paper size, the Chinese National Standard (CNS) A4 specification (2l0x 297 g t) is applied. 7 丨 Install -------- Order --------- line (please read the notes on the back before filling this page) 498529 i. Description of the invention (around νΛ〇. Then perform an implant In the process of solder ball, a plurality of solder balls 890 are planted on the contacts 826 of the substrate 820. Finally, a single cutting process is performed to cut multiple independent packages 800. (Please read the precautions on the back first (Fill in this page again.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics. Please refer to Figure 14. In the above process, the bump 870 is composed of a solder bump 872, a transition body (not shown), and a metal post 874. Therefore, the volume of the bumps 870 can be greatly reduced, and the distance between adjacent bumps 870 can be shortened at the same time, and closer to the allowable distance between the adjacent pads 812 on the wafer 810, so that the bumps 870 can be directly formed On the bonding pad, and is electrically connected to the substrate 820 directly through the bump 870, without the need for fabrication The configuration of the circuit layer can greatly improve the process efficiency. Because of the flip-chip structure described above, it is not necessary to make a reconfiguration circuit layer, and the electrical connection between the chip 810 and the substrate 820 can be completed only through the bump 870. Shorten the signal transmission path between the wafer 810 and the substrate 820, and further improve the electrical quality between the wafer 810 and the substrate 820. In addition, the present invention can pad the distance between the wafer 810 and the substrate 820 through the metal pillar 874, and The diameter of the metal pillar 874 is very small. Furthermore, the material used for the metal pillar 874 is copper, and the ductility of copper is very good. In this way, the bump 870 can tolerate the large deformation between the wafer 810 and the substrate 820 due to heat. To improve the reliability of the bonding between the wafer 810 and the substrate 820. In addition, the present invention removes the solder mask layer 840 located near the contact point 830 to form an opening 832, so that the distance between the wafer 810 and the substrate 820 will increase, so it is being covered. During the crystal manufacturing process, a filling material 880 can be easily and quickly inserted between the wafer 810 and the substrate. The wafer 810 which is raised by the metal post 874 is used to return the wafer 810 and the substrate 820 back. After welding, the cleaning solution also flows into the wafers 810 and 16 more easily. This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 498529 7533twf.d〇c / 〇〇9 A7 Intellectual Property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of the People's Republic of China 5. The gap between the substrates of the invention (82), so that the flux remaining after the reflow process can be removed cleanly. The packaging method of the present invention can also be It is a form of _, as shown in FIG. B, which shows a kind of half-body wafer structure according to another ~ preferred embodiment of the present invention. After the wafer 9H) is electrically bonded to the substrate 92 °, an adhesive process is performed to cover a wafer 91 ° bump 970 with a packaging material MO. In addition, as shown in FIG. 16, it shows a semiconductor wafer structure according to still another preferred embodiment of the present invention. After the filling material 1082 is filled between the wafer 1010 and the substrate 1020, the wafer 1010 and the filling material log can also be covered with ~ packaging material 1080. To sum up, the present invention has at least the following advantages: 1. The flip-chip structure of the present invention, since the bumps are composed of solder bumps, transition ridges and metal pillars, the volume of the bumps can be greatly reduced, and at the same time, Shorten the distance between adjacent bumps, and approach the allowable distance between the adjacent solder pads of the wafer, so that the bumps can be directly formed on the solder pads, and the stomach is electrically connected to the substrate through the bumps, and No longer need to make reconfiguration, the line foot of each layer can greatly improve the process efficiency. 2. The flip-chip structure of the present invention can completely eliminate the need to make a reconfiguration circuit layer, and the electrical connection between the wafer and the substrate can be completed only through the bump, so that the signal transmission between the wafer and the substrate can be shortened even more. Lu Ning also mentions the electrical quality between the wafer and the substrate. 3. The flip-chip structure of the present invention, because the present invention can pad the distance between the wafer and the substrate higher through the metal pillars, and the diameter of the metal pillars is very small. Moreover, the metal pillars are used for metal pillars. The material is copper, and the ductility of copper is very good. 17 This paper size applies to the Chinese national standard (CNSW1 specification (21〇χ 297 meals) (Please read the precautions on the back before filling out this page) --------- Line * 498529 A7 B7 S33twf.doc / 009 V. Description of the invention (\ >) Such a bump can tolerate large deformation between the wafer and the substrate due to heat, which improves the wafer and the Reliability of substrate bonding 4. The flip-chip structure of the present invention removes the solder mask layer located near the contact to form an opening, so that the distance between the wafer and the substrate will increase, so during the flip-chip process, It is relatively easy and quick to insert a filling material between the wafer and the substrate. 5. The flip-chip structure of the present invention, because the wafer is raised by metal pillars, when the wafer and the substrate are re-welded, The cleaning solution also easily flows into the gap between the wafer and the substrate, so that the reflow can be performed. The flux remaining after the process is removed relatively cleanly. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Inside, when you can make a few changes and retouching, the protection of the present invention is limited by the scope of the patent application attached to Dangshi. ------ Order -------- • Line. (Please read the notes on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives printed sheets S) N (C Standard