TW497216B - Dual damascene process of applying compound mask layer - Google Patents

Abstract

There is disclosed a method for manufacturing dual damascene structure, which comprises: first, sequentially depositing a first dielectric layer, an etching stop layer, a second dielectric layer, and a mask layer on a semiconductor substrate, and defining a contact tube on the surface of the semiconductor substrate by a photolithography and etching procedure; next, depositing a polymer dielectric layer on the upper surface of the mask layer and filling the same in the contact tube, and depositing silicon-based film on the surface of the polymer dielectric layer, such that a compound barrier mask formed by the polymer dielectric layer and silicon-based film can effectively prevent the photoresist in the contact tube from qualitative change in the next step of photolithography process for the trench; then, using the compound mask as an etching mask to perform an etching procedure on the second dielectric layer, thereby defining a trench opening pattern therein; and after removing the polymer dielectric layer and silicon-based film remained on the semiconductor substrate, filling metal in the trench opening and contact tube to form a dual damascene structure.

Description

497216 V. Description of the invention α) Field of the invention: The present invention relates to a dual damascene process in the semiconductor industry, especially a stack using a polymer dielectric and a Si-based film. It is used as a composite mask power layer to prevent the occurrence of via poisoning defects, and to further improve the method of absolute dimension (CD) of the double post-mounting process. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULS I), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. And due to the continuous shrinking of components, the related semiconductor process often encounters unprecedented difficulties, and the complexity of the process is also increasing. In general, integrated circuits include countless components and electronic connection structures used to connect these components in order to perform the specific functions required. Therefore, in addition to the performance of integrated circuits, the performance of integrated circuits requires countless precise and fine metal interconnections in order to effectively transfer electronic signals between components. However, in the related process of multi-metal interconnection, due to the limitation of the lithographic resolution, the error of the exposure focus (Focus), the resolution of the image transmission (Resolution), and the reduction of the available space, the mosaic process is caused. (Damascenepr 〇cess) related technologies have been widely developed

497216 V. Description of invention (2) and application. In addition, by using single damascene or dual damascene technology, multiple metal interconnects (mu 1 ΐ ip 1 einter-c ο η necti〇ns) can be manufactured more precisely. ). Among them, the dual damascene technology can simultaneously form trench connections and conductive plugs connected to a semiconductor substrate. Therefore,-in addition to improving the accuracy of the defined pattern, it can also improve the integrated circuit yield and yield, and reduce the cost of process time. ^ Please refer to the first figure, which shows the steps for making a dual-inlay structure in the prior art. Among them, the system of forming the contact culvert (via_first) Ϊ :: ΐ ΐ has considerable advantages ’and has been widely used. Typical Γ2: = half substrate 10 is sequentially formed to form the barrier layer 12, 20: fabrication: such as the stop layer 16, the second dielectric layer 18, and the cover layer 丄 ^ c V 1 a) ZZ stops with the above-mentioned membrane layer. Next, a photoresist layer 22 is coated on the masking layer 12 and the upper surface of the barrier layer 12 is because the photoresist layer 22 has fluidity, so that the upper surface of the layer 20 is: At the same time, "X" is filled in the contact culvert. Then, as shown in the second figure, borrow

The photoresist layer 22 may be subjected to photolithography, development, cleaning, and other procedures. At the same time, the opening pattern 24 of the trench is on the photoresist layer 22 of the covering part, and can be continued, the bottom of the contact culvert will still be protected in the etching step in 18, the protection level = the meaning of the trench opening in the second Dielectrics are protected from the effects of ion etching. If you touch the barrier layer 1 2 at the bottom of the culvert, you are using a photoresist layer 2 2

4y / 厶 丄 υ 5. Description of the invention (3) The dielectric layer 18 is subjected to an etching process. For the etch mask power, the flex-Γ-I pair of the masking layer 20 and the first layer can be opened in σ. However, it is worthy to inject the soil. It is usually made of osmium. It is composed of the material of the first dielectric layer and the first dielectric layer 14 along the material of the second electrical coefficient (丨 ow —K), so when the photoresistance = In the case of filling in the battalion, Mu and a large number of non-dielectric materials in the low-dielectric material 26, as shown in the reaction of the 3% basis, and the formation of hard 22 in contact with the opening of the culvert. In addition, these hard blocks 26 cannot be effectively removed after the above photoresist layer is used in the development process. In such a step,: = the photoresist layer 22 is used to define a trench opening in the second dielectric layer 18. The hard block 26 which is in contact with the opening of the culvert will make the etching process difficult. In addition, as the connection ratio in the film layer is adjusted. In other words, the organic layer, such as an emission layer, shows the shape of the deposited light. For semi-conducting contact culverts with smaller dimensions and their uniform filling energies 28 (often will be coated with a higher pattern on the photoresist layer 22 with a lithographic exposure process) 22 The contact culvert is not the same as: thickness. At the same time, it is difficult to reduce the accuracy and the size of the process is continuously reduced. The definition also has a southern aspect ratio (a SP e C t More difficulties. Please refer to the fourth figure. For the common sense organs on the semiconductor substrate 10, when filling the photoresist material, a lot of voids are often generated by L 'in order to improve the photoresist layer 2. The flatness of 2 is, however, this often leads to a decrease in the depth of the exposure to be defined in order to adjust the focus. On the contrary, the thickness of the photoresist layer 22 decreases.

Guang 497216 5. In the description of the invention (4), it is easy to make the shape that is located in contact with the opening of the culvert sunken. The surface of the square first resistive layer 22 is such that when the photoresistive layer 22 is subsequently entered into the trench opening pattern 24 in the second figure, light is often used to define a side wall that is inclined or curved. And two]: The trench opening pattern is used to protect a part of the photoresist layer 2 of the barrier layer 12 below. The above-mentioned excessive gaps 28 cannot accurately control the situation where the height also penetrates, resulting in the exposure of the barrier below it. Layer 丨 2 may cause subsequent distortion of the trench opening pattern of the cover layer 20 and the second dielectric channel, which reduces the overall = the purpose and summary of the invention: The main purpose of the film is to provide a combination of the polymer dielectric layer and the The method of defining the trench opening pattern on the semiconductor substrate by engraving the mask and enclosing the surname after the layer containing Shi Xi can further improve the lithography accuracy of the dual damascene process. Another object of the present invention is to provide a process of combining a polymer dielectric layer with a silicon-containing compound layer to effectively block a photoresist material and a low-dielectric-constant material 'and prevent via poisoning. The invention provides a method for forming a dual damascene structure on a semiconductor substrate.

497216 5. Method of Invention Description (5). First of all, the deposition layer, the second dielectric layer, and the above-mentioned film layers are sequentially shielded until they reach the upper surface. The deposit is then filled in a contact culvert. And noodles. Then apply a photoresist layer. It is worth noting that the combined cover structure will be effective, and prevent via poison from touching the cover cover. For the broken film, use the $ x film layer as the I engraving to define the bottom of the trench opening.份 高 聚 介面。 Polymer surface. Then, using a silicon-containing power, the masking layer and the second interface are formed on the surface of the stop layer. Its daughter dielectric material can protect the barrier molecular dielectric layer, and after the bit material is removed, it can be filled with a metal dual damascene structure. A barrier layer, a first dielectric layer, and a stop cap layer are deposited on the semiconductor substrate. Then, the barrier layer can be terminated, and the contact culvert is defined on the molecular dielectric layer on the upper surface of the masking layer, and a silicon-containing film layer is deposited on the surface silicon film layer on the polymer dielectric layer, wherein the photoresist layer A complex isolation photoresist material composed of a silicon-containing film layer and a polymer dielectric layer having a trench pattern and the occurrence of a second dielectric ing below. Subsequently, a photolithography process was used to perform the engraving process to define the trench opening. Engraving the mask power to the polymer dielectric layer | insect on the cover layer. Among them, the electrical material located in the contact culvert completely covers the barrier film and polymer dielectric layer underneath as the etched mask electrical layer to perform the etching process to define the trench opening. The above-mentioned high layer at the bottom of the contact culvert . In the process of removing a portion of the polymer dielectric remaining on the cover layer above the bottom of the contact culvert in the trench opening and the contact culvert to form a detailed description of the invention: The present invention provides a new method for preventing low dielectric constant materials from

Page 8 0 ^ 497216

The reaction of the photoresist material results in a correlation of via poisioning. ^ 'The composite king is formed by depositing a high-molecular dielectric layer and a stone-containing film layer. Heaping will effectively isolate the photoresist material from the low-dielectric system: f power material, thereby preventing via poisoning. In addition, a composite mask stack can be used as an etching mask stack to define the trench openings in the lower dielectric process. In this way, the yield of the overall dual damascene process can be improved. Detailed description of the present invention: two. However, the second and fifth pictures are provided firstly-a single crystal silicon substrate 50 with &lt; 100 &gt; crystal orientation. Generally speaking, other types of semiconductor materials, such as arsenide (gall1Um arsenide), germanium (germanium), or on the insulating layer :: = (Slllconon insulat〇r, so) can be used as semi-bulk materials use. In addition, due to the characteristics of the surface of the semiconductor substrate, the present invention does not cause special effects, and it can also choose <1 1 0> or ^ 11 ^ depending on its crystal orientation. Next, a barrier layer 52 may be deposited on the semiconductor substrate 50. t5, before forming the barrier layer 52, a variety of active components, passive components, peripheral circuits and the like required for the integrated circuit can be placed on the semiconductor substrate 50. In other words, various functional layers and material layers have been formed on the surface of the semiconductor substrate 50 in advance. Therefore, by forming the barrier layer 52, various elements on the semiconductor substrate 50 can be effectively protected. Then, a first dielectric layer 54 may be deposited on the barrier layer 52 for use as an interlayer dielectric layer (ILD). In the preferred embodiment, the first dielectric layer 54 is

Page 9 497216 V. Description of the invention (7) is made of a material with a low dielectric constant. For example, Bd, CORAL, SiLK, Flare, HSQ, Nanglass, etc. can be used as the first dielectric layer 54 with a low k value (k value less than 4). Then, a material such as a fossil evening engraved stop layer 56 can be deposited on the first dielectric layer and the second dielectric layer 58 on the etch scoop. The same 'here the second dielectric A + I is used for the interlayer dielectric layer, and its material can also choose I 筮 dielectric layer 5 4 similar to you + ^ 刊 贝 刀 jk 辉 兴 弟 一 β n recognize Catty people are low, | Electric coefficient material. Subsequently, a second layer 60 is deposited on the second dielectric chip layer ^^. ㈢8 on the surface so as to effectively protect the second dielectric below. Then, the stop layer 56, the first eight strokes, the cap layer 60, the second dielectric layer 58, and the etching stop surface can be stopped. In general, = /, 'layer 54 is defined, and the contact culvert 62 is defined in the case of the barrier layer 52, so that the subsequent production of the 逡 3 barrier layer 5 2 will also define the relevant opening pattern of the conductive substrate 50 -μ. When it is connected to the contact culvert 62, it can be turned on halfway. Then, as in the polymer dielectric of the sixth figure, it can be deposited in the material tube 62 such as SiLK, Flare and the like. Generally, the upper surface of the cover layer 60 is filled with contact culverts to deposit this polymer dielectric exhibition. The spin-on process can be used to cure the process, and the About 3 to 5 0 C solidification. In a preferred embodiment, it can be fully and uniformly filled in the contact culvert 6 2 while it can be completely filled, and the curing temperature can be adjusted to 400. (: Left and right, chance. I 妾 touch culvert 6 2 and reduce the gap between

Page 497216 “Then, a silicon-containing film layer (Si-base f Um) 66 is deposited on the second layer of the polymer medium. Among them, the silicon-containing film layer 66 can contain nitrogen and nitrogen at a temperature of about 3,000 psi. ::; 2: 亍 = And: The material can be selected from oxidized stone Xi, Xi or any combination of Si. Under better conditions, the control is continuously on the high, layer 64. Generally speaking, when the polymer dielectric layer 64 When it is under the surface, the silicon-containing film layer 66 can be more uniformly deposited and subsequently, a photoresist layer 68 is applied to define the trench opening in micro. Special emphasis should be placed on the second dielectric layer 58 and the stone-containing layer. The material of layer F and layer 68 of layer 66 corresponds to this. In this way, the above-mentioned deposition I can be used as a subsequent constant-electricity constant material and photo-resistance exposure pattern. The second effective pattern-blocking material resist layer 68 is contained in Shi Xi, developed, and cleaned 70 ′, and the exposure is higher than that of the previous description. The dielectric layer 58 with a masking structure prevents the ν iap. The effect of the etch mask on the sub-dielectric layer 6 4. On the film layer 66, and through the washing process, the photoresist layer 6 8 is exposed The traditional process described by the silicon-containing film layer 66, here is composed of the south molecular dielectric layer 64 and 'so it can effectively prevent the light out of the unsaturated groups from generating anti-i son i ng. In other words, the silicon-containing film layer 6 6 Except for this, it is possible to achieve the isolation of the low-intermediate 497216. V. Description of the invention (9) The surface of the layer 64. In this way, the trench opening pattern 70 can be defined in the stone-containing film layer 66. Generally, here During the etching process, the photoresist layer "will also suffer considerable damage. Therefore, after the pattern is defined, the thickness of the photoresist layer 68 will decrease. Then, as shown in the eighth figure, the residual dielectric layer 68 and the silicon-containing film layer 66 are used as etch masks to etch the polymer dielectric layer 64 to define a trench on the surface of the cover layer 60. Opening case 7〇 = In the preferred embodiment, plasma etching can be selected using an etching formula such as 〇2 or \ / 112, so-for the silicon-containing film sound 66 used as an etching mask, and for protection The masking layer 60 of the second dielectric layer 58 below, and the two molecules = layer 64 will have equivalent, the choice is more compatible than the second; in: The sergeant is removed in the carving process. 1 to: When: the molecular dielectric layer 6 "insects to the surface of the cover layer 60, if the excessive engraving process is continued, the polymer dielectric materials in 6 2 will also be affected by etching. The degree gradually decreases. "Insects, so that their surface is ~ 1-7. The ancient dielectric layer 64 in the grazing culvert 62 is completely removed, and it can be adjusted. Worm engraving-retain part of the polymer dielectric layer 64 in Contact culvert 62 bottom e j τ between 'system 52 harm

Cover the surface of the lower barrier layer 52. In other words, # &amp; ° 卩 ’can be completed, and it can be adjusted to remain in the contact culvert 62; Due to the etch time i and the residual high-molecular dielectric layer 64 :: ζ sub-dielectric layer, the barrier of the square of the trench pattern is therefore, as shown in Figure 28. In contact with culvert 6 2

497216 5. In part (10) of the invention description, part of the polymer dielectric layer 64 is still retained. As for the photoresist layer 66 originally remaining on the silicon-containing film layer 66, it is often completely removed during the over-etching process. Please refer to the ninth figure, and then use the silicon-containing film layer 66 and the polymer dielectric layer 64 7 as an etching mask to sequentially etch the cover layer 60 and the second dielectric layer 58 in order to define a trench opening pattern. 70 on the surface of the etching stop layer 50. ^ The above-mentioned residual polymer dielectric layer 64, which is located at the bottom of the contact culvert 62, will also decrease with the progress of the etching process, but it will be made to protect the barrier layer 52 below. In addition, as for the film-cutting layer 66 located on the interlayer dielectric layer 64, it is often cleared; in this case, it will be completely cleared, and the situation shown in the ninth figure will be completed when the narration process is completed. Please refer to line 64 to remove the process layer, and. Among them, plasma erosion and contact culvert metal material structure 72. The contact plug sequence in layer 58 is in order to remove the grooves located in the better realizing process (a bottom of camp 6 2 is opened in the trench, and the trench is connected to line 63. Then, the dielectric layer 64 enters the polymer dielectric. Electric + dielectric layer 64 # 5 〇Remove ashing cover layer 60 1 'can be filled with double inlay in second dielectric layer 5 4' can be cleared up and located in the cover contact culvert 6 2 In the embodiment, sh etching can be performed The residual high score α 7 0 contacts the double damascene junction structure 73, and the partial bottom score on the π dipyridine molecular cap layer 60 is selected to the semiconductor bottom) in order to thoroughly clean the dielectric layer 64. Of course, the culvert 62 and the structure 72 include forming

$ 13 页 497216 V. Description of the invention (11) = Double steel inlaid structure is used as an example. A barrier layer can be formed at the opening of the trench H. • Contact the surface of the culvert 62, and then deposit a copper seed layer (cu on the barrier). On the barrier layer. Then, by subjecting the semiconductor substrate to a copper diisocyanate solution to a chemical plating e = al Plating (ECP) reaction, a copper material layer can be deposited on the copper seed crystal: and filled in the trench opening 7 〇 in contact with the culvert 62. In this way, the poor perform a well-known chemical mechanical polishing process = line 71 and a fine double-knot junction with contact plugs === materials used. Dielectric molecules occur using the polymer macromolecule dielectric material of the present invention with good uniformity and the chance of covering voids. Furthermore, in addition to the dielectric layer, there is a chance that the dielectric material of the present invention is above. Method, which has the ability to fill the cap and disperse molecules, and can have considerable benefits. Among them, due to the contact with the culvert, it will have a specific photoresistance to effectively prevent the contact of the culvert with the addition of the dielectric material of vla polsoning to block the photoresist material and the silicon-containing film layer to completely cover the high-intensity In order to prevent the Vla p0s〇ning step, such as it to prevent it, in addition, in the present invention, the control is located in the contact, in addition to the side where the first dielectric layer can have, the protective wall by the culvert can be adjusted by etching. G of the polymer dielectric layer = the surface of the barrier layer below the height σ of the molecular dielectric material, and also the etchant erosion, which changed the angle of contact 497216. V. Description of the invention (12) The dimensions of the culvert. Therefore, by using the method of the present invention, the accuracy of defining the trench opening pattern and the dimensions of the contact culvert can be greatly improved. Furthermore, in the present invention, a silicon-containing film layer and a polymer dielectric layer are used as an etching mask when defining a trench opening pattern on the second dielectric layer. Therefore, compared with the conventional process, the thickness of the photoresist layer in the present invention can be greatly reduced. In this way, the process window during photolithographic exposure of the photoresist layer can be effectively improved, and the accuracy and yield of the overall dual-embedding process can be improved. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. For those skilled in the art, modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. ♦

Page 497216 Simple illustration of the diagram Simple illustration of the diagram: It will be easy to understand the above-mentioned content and the many advantages of this invention through the following detailed description in combination with the attached diagram, which forms a light image of the photoelectric layer; The first picture of the light-defining Nanfengou ditch is a cross-sectional view of a semiconductor wafer, showing the steps of forming a resistive layer on a semiconductor substrate and filling the first dielectric layer and the second dielectric culvert according to the conventional technology; The second figure is a cross-sectional view of a semiconductor wafer, showing the steps of patterning a trench opening pattern in a photoresist layer according to the conventional technology; the third figure is a cross-sectional view of a semiconductor wafer, which is formed on a contact culvert opening when a resist layer is applied in the conventional technology Of via ρ 〇is ο ning. Now when the fourth picture is the semiconductor resistive layer, the fifth picture may be the opening of the semiconductor culvert. The second sixth picture is the semiconductor sub-dielectric layer and silicon. The seventh picture is the semiconductor opening pattern. The eighth figure of silicon is a cross-sectional view of a semiconductor opening pattern in the south. The ninth figure is a cross-sectional view of a semiconductor opening pattern on a second wafer. Defects such as voids, recessed surfaces, etc .; a cross-sectional view of a wafer, showing steps in a dielectric layer and a first dielectric layer according to the technology of the present invention; a cross-sectional view of a wafer, showing a film layer deposited on a second dielectric layer according to the present invention Steps above; Sectional view of wafer showing steps in defining film layer according to the invention; Sectional view of wafer showing steps in defining sub-dielectric layer according to the invention; Sectional view of wafer showing dielectrics defined according to the invention Steps in a layer; and

Page 16 497216 Brief Description of Drawings The tenth drawing is a cross-sectional view of a semiconductor wafer, showing the steps for making a dual copper damascene structure according to the present invention. Drawing number comparison table: Conductor substrate, dielectric layer, dielectric layer, contact culvert, bulk substrate, substrate, dielectric layer, dielectric layer, contact culvert, silicon film layer, channel opening pattern, channel connection structure 10 half 14th 18th 2nd 2nd 26th Hard 50 Single 54th 58th 62nd 66th Including 70 grooves 73 grooves 12 barrier layer 1 6 stop layer 2 0 cover layer 2 4 trench opening pattern 28 gap 5 2 barrier layer 5 6 money stop layer 6 0 masking layer 6 4 polymer dielectric layer 6 8 photoresist layer 7 2 dual mosaic structure

Page 17

Claims (1)

497216 (1) Application scope 1. A method for forming a dual damascene structure on a semiconductor substrate, the method including at least the following steps: sequentially depositing a first dielectric layer, an etch stop layer, a second dielectric layer, and A cover layer on the semiconductor substrate; I etch the cover layer, the second dielectric layer, the stop layer, and the first dielectric layer to define contact with the culvert on the surface of the semiconductor substrate; deposit a polymer dielectric layer On the upper surface of the cover layer and filled in the contact culvert; depositing a stone-containing film layer on the upper surface of the polymer dielectric layer; etching the silicon-containing film layer to define a trench opening pattern therein, and exposing a portion The surface of the polymer dielectric layer; using the silicon-containing film layer as an etching mask, the polymer dielectric layer is etched in order to define the trench opening on the cover layer, wherein a portion is reserved at the bottom of the contact culvert Share the polymer dielectric material to completely cover the surface of the semiconductor substrate; perform an etching process on the cover layer and the second dielectric layer to define trench openings in it; ♦ remove remaining residues in the The polymer dielectric layer on the semiconductor substrate; and a metal filled in the trench opening and the contact culvert to form a dual damascene structure. 2. The method according to item 1 of the patent application range, wherein the polymer dielectric material located at the bottom of the contact culvert can prevent the semiconductor substrate from being damaged by etching. Page 18 497216 t. Patent application scope 3. The method of the first patent application scope, before the first dielectric layer is deposited, further includes the step of forming various elements or material layers on the semiconductor substrate. 4. The method according to item 1 of the patent application range, wherein the first dielectric layer and the second dielectric layer are made of a material having a low dielectric constant (k value &lt; 4). 5. For the method according to item 1 of the scope of patent application, wherein the above-mentioned polymer dielectric layer is deposited using a spin coating process, and the curing process can be performed at a temperature of about 300 to 500 ° C, and It can be filled in the contact culvert sufficiently uniformly. 6. The method according to item 1 of the patent application range, wherein the silicon-containing film layer is deposited in an environment at a temperature of about 300 to 600 ° C, and the material of the silicon-containing film layer can be selected from silicon oxide, Silicon oxynitride, silicon nitride, or any combination thereof. 7. The method according to item 1 of the scope of patent application, wherein the macromolecule dielectric layer is etched using the above-mentioned stone-containing film layer as a masking power to define the etchant used when the trench opening is defined. Choose 02, N2 / H2, or any combination of them. 8. If the method of the scope of patent application No. 7 is applied, it can be adjusted by etching Page 19 497216 (1) Application scope The time of the polymer dielectric layer is engraved in order to control the height of the polymer dielectric material remaining at the bottom of the contact culvert. 9. The method according to item 1 of the scope of patent application, wherein the above-mentioned removal of the residual polymer dielectric layer at the bottom of the covering layer and the contact culvert can be performed by an ashing process. 10. The method is used to deposit a coating layer on a deposited culvert to deposit a coating layer; a program is used to determine a method for forming a dual damascene structure on a semiconductor substrate, which includes the following steps: m A barrier layer on the semiconductor substrate; a first dielectric layer on the barrier layer; a stop layer on the first dielectric layer; a second dielectric layer on the stop layer; a cover layer on the second dielectric On the electrical layer; the cover layer, the second dielectric layer, the stop layer and the first dielectric contact culvert, and exposed part of the upper surface of the barrier layer; a polymer dielectric layer on the upper surface of the cover layer And fill the silicon-containing film layer on the upper surface of the polymer dielectric layer; a photoresist layer on the silicon-containing film layer, wherein the photoresist layer has a trench; the photoresist layer serves as an etching mask; The silicon-containing film layer is used to etch the trench opening; the film-containing film layer is used as a power mask to feed the polymer dielectric layer. Page 20 497216 6. The scope of the patent application is etched to define the trench opening on the cover layer, where the polymer dielectric material is still partially located at the bottom of the contact culvert, completely covering the surface of the barrier layer below. ; Using the stone-containing film layer and the polymer dielectric layer as a money engraving mask, and performing a engraving process on the covering layer and the second dielectric layer to define a trench opening on the surface of the stop layer, wherein The polymer dielectric material located at the bottom of the contact culvert can protect the barrier layer; removing the residual polymer dielectric layer on the cover layer, and removing a portion of the polymer dielectric at the bottom of the contact culvert Material; and filling metal in the trench opening and the contact culvert to form a double-inlaid structure. 11. The method of claim 10, wherein before forming the barrier layer on the semiconductor substrate, the method further includes the step of forming various elements or material layers on the semiconductor substrate. 12. The method of claim 10, wherein the first dielectric layer and the second dielectric layer are made of a material with a low dielectric constant (k value &lt; 4). 13. For the method of applying for item 10 of the patent scope, wherein the above polymer dielectric layer is deposited using a spin coating process, and a curing process can be performed at a temperature of about 300 to 500 ° C, And it is filled in the contact culvert sufficiently uniformly. P.21 497216 VI. Application scope of patent 14. The method of item 10 of the scope of patent application, wherein the above silicon-containing film layer is deposited in an environment at a temperature of about 300 to 600 ° C, and the The material of the silicon film layer can be selected from silicon oxide, silicon oxynitride, silicon nitride, or any combination thereof. 15. The method according to item 10 of the scope of patent application, wherein when the above-mentioned stone-containing film layer is used as a power mask, the macromolecule dielectric layer is worm-etched to define the trench opening. The etchant can be selected from 02, N2 / H2, or any combination thereof. 16. The method according to item 15 of the scope of patent application, wherein the time for etching the polymer dielectric layer can be adjusted to control the height of the part of the polymer dielectric material remaining at the bottom of the contact culvert. 17. The method of claim 10 in the scope of patent application, wherein the above-mentioned removal of the residual polymer dielectric layer at the bottom of the cover layer and the contact culvert can be performed using an ash plasma etching process. Page 22