TW494480B - Device with vertically isolated source/drain and a method of fabricating the device - Google Patents

Abstract

A method of controlling ion implant straggle and dopant diffusion in Field Effect Transistors (FETs) having a shallow junction depth in order to reduce short channel effects, and a device fabricated using the method. The method comprises the steps of etching a portion of a polysilicon layer of the device to expose a portion of the gate dielectric, forming a first oxide over a remaining portion of the polysilicon layer, etching a portion of the dielectric layer to (i) expose the isolation region and (ii) form a trench in the substrate; forming a second oxide layer on the trench; disposing a spacer over a portion of the second oxide layer and adjacent the first oxide layer; removing an exposed portion of the second oxide to expose a surface of the trench; removing the spacer; and disposing a semiconductor over the second oxide layer and the exposed surface of the trench.

Description

49448〇 and description of the invention (1) Field of the Invention The present invention relates generally to a plate conductor device 'and more specifically to a method for controlling the diffusion of ion implantation and dopant diffusion in field telephone crystals (FETs). A shallow junction depth in order to reduce short channel effects, and a device made using this method. BACKGROUND OF THE INVENTION As semiconductors become smaller and packed tighter on a common substrate, girls experience leakage currents and parasitic lightning related to junction insulation: and circuit performance has increasing adverse effects. There is increasing demand. In the prior art, the islands on the substrate are crystallized with dielectric regions. Individually. In this projective hard integrated circuit technology, the square surface is in the groove, and the integrated dielectric medium arranged in the single-domain surrounded device is exposed in a thick manner. The engraved polycrystalline material can be connected to meet the requirements. Circuit; a mesh-shaped groove to leave a single crystal substance to coat the groove with a dielectric layer and an exposed layer to cover the dielectric layer, and then grind off the single island. This provides a structure in which each single crystal island in the polycrystalline matrix is fabricated in a single single crystal semiconductor island to build a low-density integrated circuit, which has not yet proven to be suitable for high-density semiconductors. Very high Hungarians with sufficient insulation power are prepared with a single crystal substrate, covering the implantation under the surface of the substrate. This :: Oxygen is used to exercise the apex of this implanted oxygen distribution well. ^ Forming a thin masking dielectric layer. The implant can be made between the surface and the implanted dielectric layer.

V. Description of the invention (2) Structural damage in the crystal region. Although this method can be overwhelmingly disadvantageous. For example, the manufacture of high-degree circuits is still affected by several bright doses in the single-crystal region. 丄 = Very high implantation required for the insulating layer. This chaotic density is extremely high, and the crystal is damaged. Even during thick exercise, its reduced current and some confusion can cause unwanted parasitic leakage in the masked dielectric region J. It can. Furthermore, when the Mos device manufactures the back gate bias contact point: in the sun body layer, it is necessary to provide the -dielectric area of the individual device to extend between the spaces = washroom: difficult, because 'the masking of the previous technology must use the main effect Come two two == below and below the touch point. This makes ㈣ a typical source, and can be difficult or impossible. -Degree chart. The deep dopant 100 and background doping / n9 junction 104 at the traditional VΛ concentration on the FET split silicon profile occur at the tangent part of the curve at the source / drain dopant dopant rich parent point. Figure 1 A As shown in Figure π, degrees, relative relationship. The spread is too deep. This results in a non-Ion 'oxide barrier 1 0 8 preventing dopant as a result of dopant concentration and depth 12. Relevance: 1. 8 5 months According to the present invention, the graph of the voltage (vt) of the old ΓΛ device Λ near Λ versus the length of the productive channel (Leff) of the traditional fet and the fet of the present invention. In FIG. 2, 200 is a graph of vt versus Leff in an ideal case, 200 is a graph of traditional fet vs. Lef f, and 204 is a graph of vt vs Lef f of a FET according to the present invention. As is self-evident in Figure 2, the Vt of curve 204 will not drop as fast as the shorter channel (L e f f).

O: \ 67 \ 67949.ptd Page 6 494480 V. Description of the invention (3) US Patent 4,683,637 issued to Varker and others and US Patent 4,700,454 issued to Baerg and others Fabrication of a structure comprising a masking oxide layer. Varker and others teach a structure that masks the oxide layer as well as the shallow trench insulation structure of the F E T device and the sloping edge. b a e r g and others teach masking the structure of the oxide layer and the thick heat of the FET device to grow the oxide. Varker and others and Baerg and others have explained a process. After the formation of the stacked structure, deep oxygen implantation is performed, and then a masked oxide layer is formed by exercise. Depth implantation is performed on the surface of the substrate via a thin film stack (specifically, oxides from gate oxides). ,-In Varker and others and BaergA others, oxygen implantation is performed through the silicon crystal of the device, so the implantation energy must be high. Furthermore, the implantation is performed through a thin film (residual gate oxide film) on the silicon surface of the device. Because Varker and others and Baerg and others all need to go deep into the device silicon crystals with high-energy oxygen implantation, they will also cause defects in the device silicon crystals, and 'Varker and others and Baerg and others will be masked. The object area, which is aligned and defined by it, the width of the FET gate and the location of the hafnium oxide. In this way, neither Varker and others and Baerg and other I are allowed to form oxides with different thicknesses than those defined by the gate and field oxides. In other words, it cannot produce structures with oxides that are smaller than those protruding =. This is a disadvantage because it eliminates the possibility of placing s2 under a slightly doped drain or increasing shallow implantation under a protrusion near the gate '. Therefore, there is a continuing need for improved devices and methods for manufacturing dielectric insulation devices.

Page 7 V. Description of the invention According to this, the third and method of the present invention, in which the dielectric insulation is: the improvement device for the dielectric insulation device is below the device but not in the action zone:: extends to the terminal or the contact part of the device

In order to solve the shortcomings of the X miscellaneous description in conventional semiconductor field-effect transistors (FETs) made by A, the present invention is related to the control method. The field-effect transistor is made by the method of diffusion and dopant diffusion and manufactured by this method ^ 妾: the degree of ice in order to reduce the short channel effect, in accordance with the steps included in the present invention, the right field region is on the surface of the semiconductor substrate " conductor substrate " The semiconductor substrate and the oxide layer are formed on the polymorph, and part of the gate dielectric; when the layer is formed, the polycrystalline silicon layer is etched to be exposed; the dielectric sound of the part is engraved == polycrystalline stone The trench in the remaining part of the layer; forming the first, second π 1 * road insulation area and ii) forming the base second oxide on this trench: configuration-spaced the exposed part of the part to expose this trench milk = layer 'Remove the second oxide conduction: = aerobic :: layer ===: and configure the half-pole / drain-pole v two v. Bulk device, which has-masked in the source of the device is related to One lane touches the oxide plutonium under the a-squid region: clothing, which has two masks at the source / x And with reading the following detailed description of the accompanying illustration to give 494480

The best understanding. It is emphasized that, according to general practice, the characteristics are not actual proportions. On the contrary, it is different for the sake of brevity. Contained in the figure are the following., ^^, ruler Figure 1 A-1 β is a graph of the relative depth of the dopant concentration; Figure 2 is the relative effective length of the device threshold voltage (Vt) ( Lef m; Figure 7-11 is a side view of a processing step illustrating an exemplary embodiment of the present invention; Figure 12 is a device illustrating a second exemplary embodiment of the present invention @Partial side view 1 3-1 5 are partial side views illustrating the first step of the present invention; 2 additional processing steps of the exemplary embodiment. Fig. 16 is a flowchart illustrating the first exemplary embodiment of the present invention; and Fig. 17 is a flowchart illustrating the first exemplary embodiment of the present invention. The flow chart of two specific examples. The details of the present invention are contrary to the prior art. According to the method and structure of the present invention, a silicon etching is performed, a low-energy surface implantation is performed, and then generated by selective = extended growth 1 Shi Xijing. Therefore, the implanted defects are reduced to the most in the device. The professor of the present invention uses a spacer film to define a masked oxide region, which aligns the FET gate and field oxide, but defines a thick yield. Less than FET gate and field Spacing between the compound. This aspect of the present invention allows to produce a plurality $ masking oxide fluctuation width. Thus, in a very lightly doped or not to use the extended FET structure, the masking oxide regions and shallow implantation can be

494480 V. Description of the invention (6) It can be formed at a shallower depth of Shi Xijing, and the masking oxide in the deep source / drain region can be formed at a deeper position of the silicon crystal. 3 to 11 and 16 illustrate a manufacturing method according to a first exemplary embodiment of the present invention. Fig. 3 is a partial side view seen through a part of a device according to a first exemplary embodiment of the present invention. Fig. 6 is a process of manufacturing a device according to a first exemplary embodiment of the present invention. In FIG. 3, a substrate 300, such as a silicon crystal, includes a shallow trench insulation (ST1) 302 formed therein. The depth of the STI 302 may be between about 100 A and 400 A, and preferably about 2000 A. The dielectric layer 304 is formed on the surfaces of the substrates 300 and 37; and can be regarded as a gate dielectric. The thickness of this dielectric layer 304 is about 20 A to 40 A 'and is preferably 30 A. A polycrystalline stone layer 306 is formed on this dielectric layer 302 and has a thickness between about 1000 A and 3000 A, and preferably about 1500 A. The Shi Xi oxide layer 308 is then formed on the polycrystalline silicon layer 306. The thickness of the silicon oxide layer 308 may be between about 300 people and 1200 A, and preferably about 700 A: the matrix 300, the STI 300, the dielectric layer 304, and the polycrystalline silicon layer 3 0 6 and the oxide layer 3 0 8 are the starting points of the first exemplary manufacturing method according to the present invention. / 、 ®Beiyiyi In Figure 4, perform (Figure 丨 6 step 丨 6 〇) active ion said "remove the layer 3 ° 8 and part of = = the formation of the evening sun silicon block 402 This RIE also exposes a portion of the dielectric sound 304. The crystalline silicon block 402 is then oxidized (Figure oxide layer 40. Fine top paste in the polycrystalline crystalline region; the thickness of the oxide side can be about 40A Details :; table = heart 494480 V. Description of the invention (7) Approximately 40 A. In Figure 5, two steps of RIE are performed. The first RIE step (step 16 0 4 of Figure 16) uses the selected A silicon etchant, such as c H F3 with argon, removes a portion of the dielectric 304, which is not covered by the oxide layer 400 or the polycrystalline block 402. The resulting dielectric is shown in Figure 5 304A in the second rIE step (step 16 16 of FIG. 16) using a selected oxide etchant such as

Cl2 + HBr + He + 02 or HBr + He + 02 produces a groove 500 defined by the lower surface 502 in the matrix 300. The depth of the trench 500 may be about 250 Ato 100 A, and preferably about 400 A. The combination of the result of the oxide layer 400, the polycrystalline block 402, and the dielectric layer 304A forms the gate 504. In FIG. 6, an oxide layer 600 is formed (step 16 0 8 in FIG. 16), and is implanted on the lower surface 5 2 of the groove 5 0 by using the ion ˜ implantation. In the illustrated specific example, oxygen ions are implanted into the exposed lower surface 502 at a dose (approximately 5E1 6 cm2) between about 2 E 16 cm2 and 7E 16 cm2 (energy is preferably about 50 Kev). Although oxygen ions are used, ions of other elements which are stable in the formation of silicon crystals during exercise can also be used as desired. It is intended that nitrogen or carbon atoms can be used to produce silicon nitride or silicon carbide insulating materials, respectively. The thickness of the oxide layer 600 may be between about 100 A and 300 A, and preferably about 200 A. After the oxide layer 6 0 0 is formed, exercise in the matrix 3 0 (step 16 1 0 of FIG. 16) for approximately 15 to 120 seconds at a temperature between 1 0 0 ° C and 1 3 0 Between 0 ° C, it is preferably about 1 100. This is known as rapid thermal exercise (RTA). As shown in FIG. 6, a portion 602 of the oxide layer 600 is formed under the layer dielectric 304 because the ions propagate through the groove 500 side. In FIG. 7, an interval of 70 0 is formed (step 16 of FIG. 16 16 2) in the trench 5 0 0 and the gate

O: \ 67 \ 67949.ptd Page 11 494480 V. Description of the invention (8) 5 0 4 on the side wall 7 04. The interval of 7 0 0 can be formed by the precipitation of conformal Si 3N4, for example, and R IE etching to select an oxide etchant, such as ^ 4 + (: 1 ^ 3 +) 2. The interval of 700 The contour or shape 7 0 2 can be changed with the height and width of the space 70. The purpose of the space 700 is to protect the oxide layer 4 0 and part of the oxide layer 6 0 0 during further processing steps. Figure 8 In the RIE etching, the selected silicon etchant and silicon nitride, such as CHF3 with argon, are used to remove a portion of the oxide 6 0 0 that is not covered by the gap 700 (Step 1614 of Fig-16). Results of RIE The surface of the substrate 3 0 0 0 is exposed where the space 7 0 0 does not appear. In addition, the oxide block 8 2 2 is formed under the protection of the space 7 0 0 supply. Also shown in FIG. 8, the part 8 0 2 of the oxide block remain under the gate 5 0 4 in the part of the substrate 3 0. In FIG. 9, the wet etching of Η3Ρ04 is used to remove, for example, an exposed part of the oxide block at intervals of 70 0. 8 0 2 (step 16 16 of FIG. 16). Then perform preliminary cleaning using HF acid or H 2 at about 1000 ° C for about 60 seconds (RTA bake). To remove the native oxide (not shown) from the surface 800 (step 1618 of FIG. 16). In FIG. 10, selective epitaxial growth is performed to rebirth biomass 100, such as silicon, from the bottom of the silicon trench and The side walls of the adjacent gates 5 0 4 fill the trench 5 0 0 (step 1620 of FIG. 16). In FIG. 11, a region 1100 is formed in the matrix 300. In step 1622 the first shallow extension or π micro-doped drain The pole π (I dd) 1 1 0 6 is formed and aligned under the gate 5 04. At step 16 2 4, the interval 9 0 2 is formed on the side gate in a similar manner as described above to form the interval 7 0 0 On pole 5 04. At step 16 26, perform the second, deeper "source and drain 11 (S / D) implant 1 104. At step 16 2 8 perform RTA to diffuse this Idd And S / D implantation and activation of doping in silicon

O: \ 67 \ 67949.ptd Page 12 494480 V. Description of the invention (9) Agent 0 is separated by 9 0 2 to protect I d d 1 1 0 6 and oxide block 8 0 2 without additional implantation. As a result of the above steps, the Idd 1106 in the region 1100 overlaps the surface 1 1 2 of the oxide block 8 2, and the additional portion 1 1 4 of the region 1 1 0 0 is formed in the fusiform 3 0 0 Below the vertical position of the adjacent oxide block 8 〇 'Result & is the oxide block 8 02, masked under the edge of the gate 504, the prevention zone ^ 丨 丨 = in the oxide block Visible diffusion at 80 2 provides a defined angle of 3 channels 11 08 in the matrix 3 0 0. Referring again to FIG. 1B, it shows that the actual position and size of the dopant concentration phase oxide block 802 can be adjusted by changing the width of the interval. In general, the higher-quality epitaxy comes from the physical block 802. At first

Fig. 12 is a partial diagram of a device according to a second exemplary embodiment of the present invention. The device of Fig. 12 is formed in half according to this sequence of Figs. 3-6, 13-15 and 7-11. The processing of FIGS. 3-6 (steps 16 0 0-1 6 1 0 in FIG. 17) is above and a V is not repeated here. # 卸 间 述

After forming the oxide layer 6 in the trench 5 0 in FIG. 13, perform the step 1 70 0 of the epitaxial 1 3 0 0 j figure — similar to the above step 16 ^ with respect to FIG. 10 to cover the oxide layer. 6 0 0 and fill the trench 5 0 0. J

In Figure VII, RIE (step 1702 of FIG. 17), using the selected oxide etchant, the lower surface defined in the substrate 3 00 4 00 2 grooves 4 4 oxide layer 6 above the spot 6 〇〇 spaced. The depth of the groove may be between about 250, 1000 A and preferably about 400 a. 015 中 ’’ the first oxide block 1500 is formed in the matrix 300 (the

494480 V. Description of the Invention (ίο) Steps 1704 and 1706) are similar to the oxide block 600 described above with respect to FIG. 6 on the oxide block 600. After the formation of oxide block 1 & 〇 〇, the steps described above with respect to Figs. 7-11 (steps 1612-1628 of Fig. 17) are performed. The resulting device is shown in FIG. 12. As shown in Fig. 12, the position of the 'oxide block 600' is below the oxide block 12 00. In addition, the oxide block 6 0 contacts the STI 302 and extends slightly below the gate 504. Although it has been shown and spoke through the Japanese and Japanese 2 Yikou

Such specific examples are good examples, which can be physicalized, changed, and replaced. Style. Numerous changes will not depart from the essence of the present invention. Now those who are familiar with this technique are covered by the present invention ^ j. Therefore, all such changes in the spirit and scope of the patent application.

Page 14 494480 _Case No. 89127983 $ 7Year factory month // Amendment Simple description of the drawing Page 15 O: \ 67 \ 67949-910517.ptc

Claims (1)

494480 Qi j winter fE / 1U burst 494480 _Case No. 89127983 This month and 7th month " Amendment_ VI. Patent application scope The second part of the domain is located on the second area. 8. The device according to item 7 of the patent application scope, further comprising an insulation region, wherein the first region is spaced from the insulation region and the second region is in contact with the surface of the insulation region. 9. The device as claimed in claim 7 wherein the third region is in contact with the surface of the second region. 10. The device according to item 7 of the patent application scope, wherein the semiconductor device is a field effect transistor (FET). 11. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having: an insulating region in the semiconductor substrate; a dielectric formed on a surface of the semiconductor substrate and the insulating region; and a polycrystalline silicon A layer is formed on the dielectric, and an oxide layer is formed on the polycrystalline silicon layer; (b) a portion of the polycrystalline silicon layer is etched to expose a portion of the gate dielectric; (c) a remainder of the first oxide on the polycrystalline silicon layer is formed (D) etching a portion of the dielectric layer to i) expose the insulating region and ii) form a trench in the silicon substrate; (e) form a second oxide layer on the trench; (f) configure a space between A portion of the second oxide layer adjacent to the first oxide layer; (g) removing the exposed portion of the second oxide layer to i) form an oxide block and ii) expose a surface of the trench ; O: \ 67 \ 67949-910517.ptc Page 17 494480 _Case No. 89127983 amended / fifth of July 7_ Patent application scope (h) remove this interval; and (i) configure a semiconductor in the second oxidation Layer and on the exposed surface of the trench. 12. The method according to item 11 of the patent application, wherein the semiconductor device is a field effect transistor (F E T). 13. The method according to item 11 of the patent application, wherein the semiconductor substrate is silicon. 14. The method of claim 11 in the scope of patent application, wherein the insulation region is shallow trench insulation (STI). 15. The method according to item 14 of the patent application, wherein the depth of the ST I is approximately 2000 A. The method according to item 11 of the patent application, wherein the depth of the gate dielectric is approximately 3 0 A. 1 7. The method according to item 11 of the patent application, wherein the polycrystalline silicon layer has a depth of about 15 0 A. 18. The method according to item 11 of the patent application, wherein the depth of the first oxide layer is about 1000A. 19. The method according to item 11 of the scope of patent application, wherein the etching step is completed by reactive ion etching (R I E). 20. The method according to item 11 of the patent application, wherein the depth of the sidewall oxide is between about 40A and 80A. 2 1. The method according to item 11 of the scope of patent application, wherein the depth of the groove is about 250 A and 100 A. 2 2. The method according to item 11 of the patent application, wherein the second oxide O: \ 67 \ 67949-910517.ptc Page 18 494480 _Case No. 89127983 f / year XT /// Amendment__ VI. Patent Application ^ (The thickness of the layer is between about 100 Α and 300 Α. 2 3. For example, the method of claim 11 in the patent scope, wherein the depth of the second oxide layer is about 200 A. 2 4. The method of claim 11 in the patent scope, wherein the formation of the second oxide layer is I) Oxygen ions with an implant dose between approximately 3E 16 cm2 and 7E 16 cm2 and an energy of 50 Ke v and ii) at high temperatures between approximately 100 ° C and 130 ° C work out. 25. The method according to item 11 of the patent application scope, wherein the second oxide layer is formed by i) implanting oxygen ions at a dose of about 5E16 cm2 and an energy of 50 Kev and ii) at about 1 1 0. ° C high temperature exercise. 26. The method according to item 11 of the patent application, wherein the sidewall is formed of Si3N4. 2 7. The method according to item 11 of the application, wherein the space is removed by H3 P04 wet etching. 2 8. The method according to item 11 of the scope of patent application, wherein the position of the oxide block is adjustable. 29. The method according to item 28 of the scope of patent application, wherein the position of the oxide block can be adjusted by the interval width in the adjusting step (f). 30. A semiconductor device comprising: a first semiconductor substrate having a groove; a first region formed on the semiconductor substrate and adjacent to the groove; a dielectric formed on a first surface of the semiconductor substrate; A polycrystalline silicon layer on the dielectric; a first oxygen formed on a first surface and a terminal surface of the polycrystalline silicon layer O: \ 67 \ 67949-910517.ptc page 19 494480 _ case number 89127983 f / year f month / > Amendment_ Sixth, the scope of the patent application / compound layer; one formed in the first silicon substrate in the part and the An oxide block on the surface of the trench, the oxide block being formed under an end portion of the polycrystalline silicon layer; and a second semiconductor disposed on the oxide block after the oxide block is formed. 31. The device as claimed in claim 30, further comprising a portion adjacent to the edge portion of the first oxide layer and a portion of the oxide block. 3 2. The device of claim 30 in the scope of patent application, wherein the first region is an insulating region. 33. The device of claim 30, wherein the first region is a shallow trench insulation (STI) region. 34. For the device under the scope of patent application No. 33, the depth of the STI is approximately between 100 A and 400 A. 35. For the device under the scope of patent application No. 33, the depth of the STI is about 2000 A. 36. The device according to item 30 of the scope of patent application, wherein the position of the oxide block is adjustable. 37. The device according to item 30 of the scope of patent application, wherein the position of the oxide block is adjusted by adjusting the interval width. 38. The device of claim 30, wherein the semiconductor device is a field effect transistor (FET). 39. The device of claim 30, wherein at least one of the first semiconductor substrate and the second semiconductor is silicon. O: \ 67 \ 67949-910517.ptc Page 20 494480 Case No. 89127983 Amendment VI. Patent application scope where the dielectric is deep where the dielectric is deep where the polycrystalline silicon layer is among the polycrystalline silicon layer where the first oxide layer is The depth of the trench is in the oxide block, in which the oxide block is in the second part of the second region, and the second part of the second region is 40. The degree of installation of the 30th item in the patent application range is about 20A And 40A. 4 1. The degree of the device in the scope of patent application 30 is approximately 30 A. 4 2. The depth of the device in the scope of patent application 30 is between approximately 1 00 A and 2 0 0 A. 4 3. The depth of the device such as the 30th in the scope of patent application is about 1500A. 4 4. The depth of the device such as the 30th in the scope of patent application is about 1000A. 4 5. The device according to item 30 of the scope of patent application is approximately between 250 A and 100 A. 46. The thickness of the device according to item 30 of the patent application range is between about 100A and 300A. 47. The thickness of the device in the 30th scope of the patent application is about 200A. 48. If the device according to item 1 of the patent application range, part of the device is in contact with the upper surface of the first region, and part of the device is in contact with the bottom surface of the first region. The first region is a semiconductor in a mass. It also includes an oxide block formed on the gate 4 9. Such as the device of the patent application No. 48 and the second area is exercise to base 50. As the patent application of the first scope of the device, and the second Area adjacent to the interval. 51. The device as claimed in claim 50, wherein the interval contacts the device. O: \ 67 \ 67949-910517.ptc Page 21 494480 a_Amendment No. 89127983 6. Scope of patent application Gate and second area. IB1 Page 22 O: \ 67 \ 67949-910517.ptc