TW492105B - Monitor method for bipolar transistor emitter opening etching process - Google Patents

Abstract

This invention provides a monitor method for bipolar transistor emitter opening etching process. The invention method at least includes: providing a substrate with a silicon oxide layer and forming a silicon nitride layer on the silicon oxide layer; depositing a semiconductor layer on the silicon nitride layer; then, forming a conductor area of the first conductor type in the semiconductor layer; forming a dielectric layer on the semiconductor layer; anisotropically etching the dielectric layer and the semiconductor layer and stopping on the silicon oxide layer to define the emitter area of the bipolar transistor; and finally isotropically etching the silicon oxide layer.

Description

492105 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for monitoring the etching process of a bipolar transistor emitter window. Background: BiCMOS complementary metal-oxide-semiconductor (BiCMOS) integrated circuits combine dual-carrier transistors (BJT) and complementary metal-oxide-semiconductors (CMOS stomachs) in a single chip, and have the advantages of most functions in the process. Therefore, the Bi CMOS integrated circuit has the advantages of BJT speed and a good analogy, and has the advantages of low energy consumption and high aggressiveness of CMOS. Immediately remove the right rate, etch the right time, do not shift, and do not say, the same rate, come or when. In addition to the fast-moving example, it is not suitable for engraving. The conductive, semi-conducting, semi-conducting layer, and short-circuit maps of the electrically conductive half-film layer are not conductive and are engraved on the thin-film layer or with #. The thin layer of the bundle is well-defined. It is important to enclose the key to the heart of the Supervisory Committee of the Supervisory Committee, which is the guide for the video guide. # 想 自 所 小 度 Mid degrees except each must be slightly over-shifted will be the same as the moment and the current level is stippling and engraving. Divide the money into the money

492105 V. Description of the invention (2) The time is further poor and expensive, so many related processes do control the end point of the etching is very heavy. The end point of the worm must be correctly predicted from the worm in the field. Because the thickness of the thin film layer is related to the concentration change, it is difficult to predict the endpoint. Factors, including the concentration of remaining pesticides, I insects and so on. Accurate control of these factors concentration control. Reliability. Semiconductor wafers are extraordinary steps, such as those required in the etching step. Measurement and discovery can make it stop at the degree of intention and structure. But the etching temperature, the flow rate of the I insect, the time of the I insect and the end of the I insect, the I insect rate is dependent on the temperature of most agents. Thickness and thin film characteristics require very expensive equipment, such as Φ. For these reasons, it is highly desirable to seek a method to monitor the etching process of the bipolar transistor emitter window to reduce the problem of substrate over-etching. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, many disadvantages caused by the traditional semiconductor device manufacturing process, a method for monitoring the etching process of a bipolar transistor emitter window is provided in the present invention. The substrate can be easily controlled from the problem of excessive etching.

492105 V. Description of the invention (3) The main purpose of the present invention is to provide a method for monitoring the etching process of a bi-carrier transistor and an emitter window, so as to obtain better quality. Another object of the present invention is to provide a method for monitoring an etching process of a bipolar transistor emitter window, which can easily control a substrate through an etching monitor. According to the above object, the present invention discloses a method for monitoring an etching process of a bipolar transistor emitter window. The method includes at least providing a substrate having a oxidized stone layer and a nitrided layer on the oxidized stone layer. Then, the semiconductor layer is deposited on the silicon oxide layer and the silicon nitride layer. Furthermore, a conductive region of a first conductive type is formed in the semiconductor layer. Next, a dielectric layer is formed on the semiconductor layer. Then, the dielectric layer and the semiconductor layer are anisotropically etched to terminate on the silicon oxide layer to define an emitter region of the bipolar transistor. Finally, the silicon oxide layer is etched isotropically. The purpose and many advantages of the present invention will become apparent from the following detailed description of the preferred embodiments and with reference to the accompanying drawings. 5-4 Detailed description of the preferred embodiments: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention 1

492105 V. Description of the invention (4) When a preferred embodiment is used to describe the method of the present invention, those who are familiar with this field should recognize that many steps can be changed and materials and impurities can be replaced. These general replacements are undoubtedly The land does not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate the description, but it should not be used as a limited recognition. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. Figures A to F are cross-sectional views of a method for monitoring an etching process of a bipolar transistor emitter window according to a preferred embodiment of the present invention. Referring to FIG. 1A, the manufacturing process of the integrated circuit is described, including the silicon substrate 100 and the field oxygen region 102, all of which use the conventional process of the double-carrier complementary metal oxide semiconductor transistor. A field oxygen region 102 is formed as a device isolation structure on the surface of the substrate 100. The area around the field isolation structure is suitable for the generation of components and the definition of a bipolar transistor for the component. The field oxygen isolation region 102 is formed by a local thermal silicon oxide technology. Then, a silicon dioxide layer 104 is formed on the substrate 100 and the field oxide region 102. The thickness of the silicon dioxide layer 104 is between 100 and 500 Angstroms. The silicon dioxide layer 104 makes it easy for the etching monitor to detect the etching end point. The reason is that the etching selection ratio of the silicon dioxide layer 104 and the substrate 100 is different. Next, a first dielectric layer 106 is formed on the SiO2 layer.

492105 V. Description of the invention (5) 10 4. The first dielectric layer 106 includes at least silicon nitride. The thickness of the first dielectric layer 106 is between 300 and 500 angstroms. The first dielectric layer 106 is formed by a low-pressure chemical vapor deposition method. For example, an n-type silicon substrate 100 can form different passive and active components, including P-channel complementary metal oxide semiconductor transistors and bipolar transistors. In a typical BiCMOS process, η + is implanted into a p-type substrate to form an NPN bipolar transistor or a PMOS device. Similarly p-type boron is implanted to form a P + well, forming a NMOS element. A field oxide region 102 is formed by a mask to define an oxidized growth region. The first dielectric layer 106 is deposited and patterned by a photomask, and the first dielectric layer 106 is removed from the field oxide region 102, where an active device can be placed. These areas are then etched into the epitaxial layer. The field oxidation region is grown by a local oxidation method to isolate the active element from the passive element. Referring to the first B diagram, a first photoresist layer (not shown) is deposited on the first dielectric layer 106. The first photoresist layer has an opening by a conventional lithography technique. Then, using the first photoresist layer as a mask, the first dielectric layer 106 is etched. Then, a part of the first dielectric layer 106 is removed to expose the silicon dioxide layer 104 to define a region of the bipolar transistor. Then, a first semiconductor layer 108 is deposited on the silicon dioxide layer 104. The first semiconductor layer 108 includes at least amorphous silicon and polycrystalline silicon. The thickness of the first semiconductor layer 108 is between 500 and 300 Angstroms. Simultaneous implantation of most p-type ions into the first semiconductor layer

492105 V. Description of the invention (6) 108, using boron ion implantation. Then, a second dielectric layer 110 is deposited on the first semiconductor layer 108. The second dielectric layer 110 includes at least silicon nitride. The thickness of the second dielectric layer 110 is between 1000 and 5000 angstroms. The second dielectric layer is formed at 110 ° by low pressure chemical vapor deposition (LPCVD), plasma gain chemical vapor deposition (PECVD), or atmospheric pressure chemical vapor deposition (APCVD). Two photoresist layers (not shown) are on the second dielectric layer 110. The second photoresist layer is provided with an opening by a conventional lithography technique. Then, using the second photoresist layer as a mask, the second dielectric Φ layer layer 1 10 and the first semiconductor layer 108 are etched. This etching step is stopped on the silicon dioxide layer 104 to define the emitter region 1 1 1 of the bipolar transistor. The emitter region 1 1 1 is formed by the anisotropic I insect. Referring to the first D diagram, the silicon dioxide layer 104 is etched under the first semiconductor layer 108. The etching method is an isotropic etching method. The isotropic etching method causes an undercut phenomenon under the first semiconductor layer 108. Then, a second conformal semiconductor layer 1 12 is deposited on the substrate 100, the sidewalls of the emitter region and the second dielectric layer 110. The second conformal semiconductor layer 1 1 2 includes at least amorphous silicon and polycrystalline silicon. The thickness of the second conformal semiconductor layer 1 12 is between 100 angstroms and 200 angstroms. In the present invention, the optimal thickness of the second conformal semiconductor layer Π 2 is 1 2 0 Angstroms. The second conformal semiconductor layer 1 1 2 is filled on the first semiconductor layer 108, the emitter region 1 1 1 and the undercut.

492105 V. Description of the invention (7) Referring to the first diagram E, the second conformal conductive layer 1 12 is oxidized to form an oxide layer 112a. At the same time, most p-type ions are implanted into the substrate 100, so that boron ions are implanted. Then, a third dielectric layer (not shown in the figure) is deposited on the oxide layer 1 1 2 a and the emitter region 1 1 1. The third dielectric layer includes at least silicon nitride. Then, the third dielectric layer is etched back to form a silicon nitride spacer 1 1 4 on a side wall of the bipolar emitter region 1 1 1. Referring to the first F diagram, the oxide layer 1 1 2 a is etched by an isotropic etching method. Then, a third conformal semiconductor layer Π 6 is deposited on the surfaces of the substrate 100, the second dielectric layer 1 10 and the spacers 114. Finally, a large number of η-type ions are implanted into the third conformal semiconductor layer 1 16 so as to be implanted with arsenic ions. The method provided by the method of the present invention for monitoring the etching process of a bipolar transistor emitter window has the following advantages: 1. A method for monitoring the etching process of a bipolar transistor emitter window is provided. For better quality. 2. To provide a method for monitoring the etching process of the bipolar transistor emitter window, which can easily control the substrate to prevent over-etching by means of an etching monitor. The above is only an embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other without departing from the spirit disclosed by the present invention

Page 10 492105

492105 The drawings briefly illustrate the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to describe the details below. Among them: Figures A through F show the method according to the present invention. A cross-sectional view of a method for monitoring an etching process of a bipolar transistor emitter window. Representative symbols of the main parts: 100 semiconductor substrate 102 field oxide region 104 silicon oxide layer 106 first dielectric layer 108 first semiconductor layer 110 first-dielectric layer 111 bipolar emitter 112 first-conformal semiconductor layer 112a Oxide layer 114 silicon nitride spacer 116 third conformal semiconductor layer

Page 12

Claims (1)

492105 VI. Scope of patent application 1 · A method for performing an etching process of a bipolar transistor emitter window, the method includes at least: providing a substrate having a layer of oxide and a layer of nitride On the silicon oxide layer, a semiconductor layer is on the silicon nitride layer, a conductive region of a first conductivity type is in the semiconductor layer, and a dielectric layer is on the semiconductor layer; the dielectric layer is anisotropically etched And the semiconductor layer to terminate on the silicon oxide layer to define an emitter region of the bipolar transistor; and isotropically etch the silicon oxide layer. 2. The method according to item 1 of the patent application, wherein the above substrate contains at least silicon. 3. The method according to item 1 of the scope of patent application, wherein the thickness of the aforementioned silicon oxide layer is between about 200 and 300 angstroms. 4. The method according to item 1 of the patent application range, wherein the above-mentioned dielectric constant layer includes at least nitride. 5. The method according to item 1 of the patent application range, wherein the semiconductor layer is selected from the group consisting of amorphous silicon and polycrystalline silicon. 6. A method of forming a bi-electric transistor with a metal oxide semiconductor transistor in the substrate, the method at least comprising: forming a silicon oxide layer on the substrate; Page 13 492105 VI. The scope of the patent application protects the deposition-forming one; forming a non-isotropic isotropic deposition-one of the emitter regions oxidizing forming-isotropic deposition-forming an integrated layer The first metal oxide semiconductor transistor has a first dielectric layer; the first semiconductor layer is on the first dielectric layer; one of the first conductive forms is a first conductive region in the semiconductor layer and the second dielectric layer is in On the first semiconductor layer; etching the second dielectric layer and the first semiconductor layer to terminate the layer to define an emitter region of the bipolar transistor; etching the silicon oxide layer; conformal A second semiconductor layer on the substrate, the sidewall and the second dielectric layer; a second semiconductor layer to form an oxide layer; a silicon nitride spacer on one of the sidewalls of the emitter; etching the oxide layer; Three semiconductor layers are on the substrate; and one of the second conductive patterns is a second conductive region opposite the third semiconductive one conductive pattern. 7. If the method of applying for item 6 of the patent scope contains Shi Xi. 8. The thickness of the method according to item 6 of the patent application is between 200 and 300 Angstroms. Wherein the above-mentioned substrate includes at least the above-mentioned silicon oxide layer _ 9. The method according to item 6 of the patent application scope, wherein the above-mentioned first dielectric layer Page 14 492105 VI. The scope of patent application At least includes nitride stone. 10. The method according to item 6 of the scope of patent application, wherein the second dielectric layer includes at least nitride. 1 1. The method according to item 6 of the scope of patent application, wherein the first semiconductor layer is selected from the group consisting of amorphous silicon and polycrystalline silicon. 12. The method according to item 11 of the patent application range, wherein the second semiconductor layer is selected from the group consisting of amorphous silicon and polycrystalline silicon. 13. The method according to item 11 of the application, wherein the third semiconductor layer is selected from the group consisting of amorphous silicon and polycrystalline silicon. 14. A method of forming a bipolar transistor with a metal oxide semiconductor transistor on the substrate, the method comprising at least: providing a substrate; depositing a silicon oxide layer on the substrate and a first A silicon nitride layer on the stone oxide layer; removing a part of the first silicon nitride layer to expose the silicon oxide layer to define a region of a bipolar transistor; depositing a first semiconductor layer on the nitrogen Forming a silicon conductive layer; forming a first conductive region of a first conductive form in the first semiconductor layer; Page 15 492105 VI. Patent application scope Deposit a second silicon nitride layer on the first semiconductor layer; Anisotropically etch the second silicon nitride layer and the first semiconductor layer to terminate on the silicon oxide layer The silicon oxide layer is isotropically etched by defining an emitter region of the bi-electric transistor; a conformal second semiconductor layer is deposited on the substrate, and a sidewall of the emitter region and the second nitrogen Oxidizing the second semiconductor layer to form an oxide layer; forming a silicon nitride spacer on one side wall of the emitter; isotropically etching the oxide layer; depositing a third semiconductor layer on the bottom Material; and forming a second conductive region of a second conductive pattern opposite the first conductive pattern in the third semiconductor layer. 15. The method according to item 14 of the patent application range, wherein the above substrate contains at least silicon. 16. The method according to item 14 of the scope of patent application, wherein the thickness of the aforementioned silicon oxide layer is between about 200 and 300 angstroms. 17. The method according to item 14 of the scope of patent application, wherein the first semiconductor layer is selected from the group consisting of amorphous silicon and polycrystalline silicon. 18. For the method according to item 14 of the patent application scope, wherein the second semiconductor Page 16 492105 Page 17