TW492087B - Gate structure and its manufacturing method - Google Patents

Abstract

The present invention discloses a novel gate structure and its manufacturing method. The gate structure of the present invention includes: a substrate; a high-k gate dielectric layer formed on the surface of the substrate; a gate formed on the surface of the gate dielectric layer; a low-k dummy spacer formed on the gate sidewall; and a main spacer formed on the sidewall of the dummy spacer. In accordance with the present invention, the gate structure has an excellent performance and can be applied in CMOS devices with a dimension smaller than sub-micron. The present invention also includes the manufacturing method of the gate structure.

Description

492087 V. Description of the invention α) Field of the invention: The present invention relates to a semiconductor process technology, and particularly to a two-performance gate structure and a manufacturing method thereof, and is particularly suitable for application to sub-micron CMOS devices. · Background of the Invention: Metal-Oxide-Semi ccmductor Transistor (MOS) is a kind of basic electronic component which is very important in integrated circuit technology. It consists of three basic materials, namely metal conductor layer and oxide layer. A gate transistor is formed on a semiconductor substrate with a semiconductor layer. In addition, 胄 includes two semiconductor regions located on both sides of the gate transistor and electrically opposite to the semiconductor substrate, which are called source and drain. At present; in the first gate transistor, the metal conductive layer is mostly composed of doped polysilicon and metal. In addition, the sidewalls of the interelectrode are mostly nitrided as a spacer. Transistors are available with hibiscus, and as semiconductor technology has been widely adopted, they have been widely used in the past, and the current cattle conductor technology requires accumulation .... The spacers of the oxide layer break will have a lot of adverse effects. As a matter of fact, the nitride shrinkage is limited when the size of the device is wide.皋 你 _ And ... When the size of the vulture is reduced, the gate oxidation is small, but when the gate oxide layer becomes thin, the grass must also be compressed, and its electric field strength increases. So come? Electricity: The method of operating electricity (tunnei ing) generates leakage current or crashes. Another can be worn by page 4: 0503-6236TWF; TSMC2001-0048; Esmond.ptd 492087 V. Description of the invention (2) When the size of the component is reduced, the width of the spacer will also become thinner, which will increase the light weight. … While the isolation between the gates becomes worse. k attack source and / or pole and therefore, A has made the technology of M0S transistor can be matched with the development of miniaturization and the need to increase the component accumulation degree to solve the problem of ζ in order to improve. To summarize the above invention: The main purpose of the present invention is to solve the high-performance gate structure. One of the features of the present invention is to use a dielectric layer with a high dielectric constant (hlgh-k) as the gate dielectric layer. '| 冤 y The second feature of the present invention is to use a dummy sPacer with a low dielectric constant (low_k) between the main spacers. In another embodiment of the present invention, This idle spacer is removed so that a gap is formed between the main spacer and the interelectrode). The second feature of t, is a combination of the aforementioned two features and uses a pre-doped polycrystalline stone layer or a polycrystalline stone material (p〇ly_, material) to achieve the best component performance. Optimization, including direct current (larger current driving force) and alternating current (smaller gate-to-source / drain characteristics). Order / He Wan · According to a preferred embodiment, the gate structure of the present invention includes : A substrate; a gate dielectric layer with a high dielectric constant, formed on the surface of the substrate; a pole 'formed on the surface of the gate dielectric layer;

0503-6236TW; TSMC2001-0048; Esmond. The gate structure includes: a substrate; a gate dielectric layer formed on the surface of the substrate, the gate dielectric having two first dielectric constants ει;-a gate 'formed on the surface of the gate dielectric layer V this The gate has a second dielectric constant; an idle spacer formed on a side wall of the gate, the idle spacer has a third dielectric constant ^; and a side wall of the main spacer, the main spacer has a fourth dielectric Electric crane number ε4, where g2 > ^.

ί ϋ 2 S㈣ includes a manufacturing method for providing a gate structure. I

Ji; :: The above and other objects, features, and advantages can be made clearer = such as; the preferred embodiment is given, and a simple description of the detailed drawings is given in conjunction with the accompanying drawings. Figure 1 shows a comparison of the present invention. Sectional view of the gate structure of the preferred embodiment. It is used to illustrate a preferred embodiment of the present invention. Figures 2 to 11 are a series of cross-sectional views. Explanation of symbols 11 ~ Isolation area; 14, 104a, 106a ~ gates 18, 11 ~~ main spacer; 22, 122 ~ metal fragments; 108 ~ hard mask; 10, 100 ~ semiconductor substrate; 12, 102 ~ gate dielectric layer; 16, 106a ~ idle spacer; 20, 1 2 1 ~ source / inverted area; 102, 104 ~ conductive layer; 0503-6236TW; TSMC2001-0048; Esmond.ptd 492087

110 to bottom anti-reflection layer; 114, 12 to ionic cloth value; 1 2 to 4 air gap. 11 2 ~ photoresist layer; 11 5 ~ lightly doped source / drain region; Embodiment " Refer to FIG. 1 for a cross-sectional view of a gate structure according to a preferred embodiment of the present invention. Forming an NMOS device is described as an example, but those skilled in the art can also form a puppet device according to the structure disclosed in the present invention. The gate structure of the present invention is formed on a semiconductor substrate 10, such as a P-type silicon substrate with a direction of 100 or a silicon substrate with a p-well. An isolation region 11 is formed on the substrate to define an active region. The gate structure of the present invention includes a gate dielectric layer 12 with a high dielectric constant, and is formed on the surface of the substrate. A gate electrode 4 is formed on the surface of the gate dielectric layer i 2. A low dielectric constant idle spacer 6 is formed on the side wall of the gate electrode 4 and a main spacer 8 is formed on the side wall of the idle spacer 6. In addition, in order to form a complete transistor, the substrate shown in FIG. 1 further includes an active / drain region 20, and a channel region therebetween, and formed between the gate 14 and the source / drain. Metal silicide 22 on pole 20. According to the present invention, if the gate dielectric layer 2 has a first dielectric constant ε, the gate 14 has a second dielectric constant ε 2, the idle spacer 16 has a third dielectric constant S3, and the main spacer 18 has a first dielectric constant S3. Four dielectric constants ε4, then the size of the dielectric constant is preferably (but not limited to) the following relationship: εθ ε4 > ε3 〇 In a preferred embodiment, the dielectric constant of the gate dielectric layer 2 is the most It is preferably greater than 10, and the dielectric constant of the idle spacer 16 is preferably less than 3. Main interval

/

The dielectric constant of the object 18 is between 3 and 10. 4 In the above invention, since the conventional closed-electrode layer is replaced by the dielectric layer 12 with a high dielectric constant, when the device is exposed to / 5 clock. High inversion carrier beat, degree (Qinv; inversion carrie: "Heart", no need to resort to drastically reduce the thickness of the dielectric layer. In this way, you can also: the thickness of the dielectric layer is too thin to cause leakage The current (Jg) or breakdown is increased for Qinv / Jg). In another aspect, the present invention forms an idle spacer 16. The idle spacer 16 may be composed of a material having a dielectric constant less than 3, or may be a simple air gap (in this case, the dielectric constant of the air gap is 丨). Because this idle spacer has a low dielectric constant, the coupling electric field from source / drain to gate can be minimized. To sum up, the gate structure of the present invention using a high dielectric constant gate dielectric layer and a low dielectric constant (or air gap) spacer has at least the following advantages: (1) still has a high current at a low supply voltage Driving force; (2) reduce parasitic capacitance from source / drain to gate; (3) reduce dielectric layer leakage current to suit low-power applications (such as some portable products). The fabrication process of the gate structure of the present invention will be described below with reference to Figs. 2 to 11. First, please refer to FIG. 2, which shows the initial steps of the present invention. In the figure, the substrate 100 is made of a semiconductor material, such as a p-type silicon substrate with a direction of 100 or a stone evening substrate with a P well ( silicon), germanium (germanium), or gallium-arsenide materials, and the formation method is epitaxial (expitaxial) or insulating layer with siHcOn 〇rl insulator, etc., for convenience, This embodiment uses a silicon substrate with a p-well as an example.

492087 V. Description of the invention (6) Traditional active isolation methods, such as LOCOS or 4-slot isolation method (sti), are used to define the active area (actiVe area) on the substrate 100 in order. A dielectric layer 102 having a dielectric constant, and a conductive layer 104 and 106. In the present invention, the dielectric layer 〇2 is used to replace the conventional gate oxide layer formed by the thermal oxidation method, and its dielectric constant is preferably greater than 〇〇. Suitable materials include Zr02, Hf02, Ta2 05 , Ti02, and Al203. The conductive layers 104 and 106 are used as gate electrodes. In the present invention, the conductive layer 104 is preferably one of a doped polycrystalline silicon layer or a poly-SiGe. The conductive layer 106 is preferably an un-doped polycrystalline stone. · Please refer to Figure 3, using traditional lithography and etching methods, to form a mask with a gate pattern on the stacked structure of Figure 1, including a hard mask 108, an anti-reflection layer at the bottom and photoresist Layer 112. The material of the hard cover 108 is usually nitride nitride (Sbbi) or silicon oxynitride (§ i × χ Ny). Please refer to FIG. 4 'removing the bottom anti-reflection layer 110 and the photoresist layer 112 ^' using a dry etching method such as plasma etching or reactive ion etching (R 丨 E) to sequentially etch the conductive along the hard mask 108 Layers 106 and 104 define a stacked gate, which includes a lower gate 104a and an upper gate 106a. In the rest of the process, the etching rate of the conductive layer 104 (doped polycrystalline silicon layer or polycrystalline silicon germanium) is higher than that of the conductive layer 10 6 (undoped polycrystalline silicon), so _ such as The undercut phenomenon (un (jercut)) shown in the figure. That is, the lower gate 10 & will be narrower than the upper gate 106a. Please refer to FIG. 5, and then use a hard mask 108 and the gate to cover Screen, with a fill as the ion source, lightly doped ion implantation 114, after a rapid thermal return

492087

The fire process forms a lightly doped source / drain region 115 to prevent channel effects. In addition, if necessary, a halo ion implant μ is applied to the substrate 10 to form a halo doped region (not shown) below the lightly doped source / drain region U5. To avoid the punch-through effect of the Mos element, please refer to Figure 6, after removing the hard mask 108 from the gate, deposit a layer of low dielectric constant on the substrate. Dielectric layer 116. According to the present invention, the dielectric constant of the & dielectric layer 116 is preferably less than 3. Suitable materials include, for example, fluorine-doped silica glass (FSG), HSQ (hydrogen silsesquioxane), MSQ (methyl silseSquioxane), FLARE (made by A1Ued ^ 叩 & 1), PAE-2 (made by Schumacher), and SILK (made by Dow Chemical). The dielectric layer 116 may be formed by spin-on-coating after baking, or formed by low temperature chemical vapor deposition (LT-CVD).凊 Referring to FIG. 7, the low dielectric constant dielectric layer 116 is etched back by anisotropic (anisotropic) etching, so as to form a gate on the sidewalls of the gates 104a and 106a. Dummy spacer 116a with a low dielectric constant. Referring to FIG. 8, a main spacer 118 is formed on the sidewall of the idle spacer 116a according to the deposition-etchback method. The main spacer 118 functions like a traditional gate spacer, and is generally a silicon oxide layer. It can use tetraethoxysilane (TEOS: tetra-ethyl-ortho-silicate) as the main reactant, and uses low-pressure chemical gas. A phase deposition (LPCVD) process is performed. In addition, the main spacer 118 may be a silicon nitride layer or a silicon oxynitride layer. Therefore, the main spacer 118

0503-6236TWF; TSMC2001-0048; Esmond.ptd Page 10

492087

The dielectric constant is usually between 3 ~ 10. So far, it has been reported again, but in order to complete the entire M 0S transistor, it still includes forming a source / drain and a metal silicide. The gate structure has been fabricated. Please refer to Figure 9 for the next steps. Then, using the gate structure and the main spacer " curtain, using phosphorus or arsenic as the ion source, perform high concentration and deep cage semiconductor substrates. Ion implantation 120, that is, heavily doped, forms a source / drain 121 / also shown in FIG. 10, and a self-aligned metal silicide (salicide) is formed on the surface of the gate 106a and the source / drain 121. ) 1 22. Usually, a titanium film is first formed on the base of Shi Xi by means of low-level plating deposition, and a rapid thermal tempering process of ~ t is used to make the titanium metal and the silicon on the source / drain and the complex repair on the gate Reaction 'to form a C49 phase shattered titanium (TiS) with a resistance value of about 60-80 #Qcin. Whereas, the metal titanium not participating in the reaction or remaining after the reaction is removed by wet etching. After that, a rapid thermal tempering at a higher temperature was used to convert the C49 phase titanium silicide into a C 5 4-phase stone with a low resistance (1 6 to 2 0 # Ω cm) at 70 0 to 90 0 ° C. Evening titanium. In addition, in addition to plutonium, other metal silicides can be formed, such as cobalt silicide (CoS i2) and nickel silicide (N i S i). FIG. 11 illustrates a gate structure according to another preferred embodiment of the present invention. In this embodiment, the idle spacer 116a in FIG. 10 is removed, and an air-gap spacer 124 (air-gap spacer) 124 is formed between the gate sidewall and the main spacer 118. The dielectric constant is the dielectric constant 1 of air, which can also achieve the purpose of the present invention. The idle spacer 11 6 a can be selectively removed by a wet-touch method. It should be noted that if the air gap spacer 1 24 shown in FIG. 11 is finally formed in the present invention, the idle interval

0503.6236BiF; TSMC2001-0048; Esmond.ptd Page 11 492087 V. Description of the invention (9) The material of the material 11 6a does not necessarily use a low dielectric constant holding material. The material of the idle spacer 11 6a is against the main space. The quality of the substance 11 8 has only one, and it must be selectively etched so that it can be selectively removed. "You Xiangyu Although the present invention has been disclosed in a preferred embodiment as above," but it is not a person skilled in this art "without departing from the spirit of the present invention," Although it can be slightly modified and retouched, so the present invention The protection of the Wai Wai shall be subject to the definition of the scope of the attached patent application.

Claims (1)

^ yzu6 / VI. Patent application scope ~ — ---- 1 · A gate structure includes: a substrate; a gate dielectric layer with a dielectric constant formed on the surface of the substrate; a gate formed on A surface of the gate dielectric layer; an idle spacer with a low dielectric constant formed on a side wall of the gate; and a main spacer formed on a side wall of the idle spacer. 2 · The gate structure as described in item 丨 of the patent application scope, wherein the dielectric constant of the gate dielectric layer is greater than 10. 3. The gate structure as described in item 2 of the scope of patent application, wherein the material of the gate dielectric layer is selected from the group consisting of: Zr%, Hf%, Ta205, Ti02, and ai203. 4. The gate structure as described in item 1 of the scope of patent application, wherein the dielectric constant of the idle spacer is less than 3. 5. The gate structure as described in item 4 of the scope of the patent application, wherein the material of the idle spacer is selected from the group consisting of: fluorine-doped silica glass (FSG), HSQ (hydrogen silsesquioxane) MSQ (methyl silsesquioxane) , FLARE (made by Allied Signal), PAE-2 (made by Schumacher), and SILK (made by Dow Chemical). 6. The gate structure as described in item 1 of the scope of patent application, wherein the dielectric constant of the idle spacer is equal to 1. 7. The gate structure according to item 1 of the scope of patent application, wherein the idle spacer is air. 8. The gate structure described in item 1 of the scope of patent application, wherein the base 6. Scope of patent application-/, source region, a drain region, and a channel region in between. is θ t The gate structure described in item 1 of the scope of the patent application, wherein the gate eight: a stacked structure, which sequentially includes a first conductive layer formed on the gate; 丨 "on the layer" and a second conductive A layer is formed on the first conductive layer. 10. The gate structure as described in item 7 of the scope of the application for a patent, wherein the first conductive layer is selected from a doped polycrystalline silicon layer and a polycrystalline silicon germanium. 1. The gate structure according to item 7 in the scope of the patent application, wherein the first conductive layer is an undoped polycrystalline chip. 1 2-A gate structure including: a substrate; g A gate dielectric layer is formed on the surface of the substrate, the gate dielectric layer has a first dielectric constant ει; /, a gate is formed on the surface of the gate dielectric layer, and the gate has a second dielectric Constant ε2; ^ an idle spacer formed on the side wall of the gate, the idle spacer JL has a third dielectric constant ^; and a Bayi main spacer formed on the side wall of the idle spacer, the main spacer has The fourth dielectric constant ε4, of which epepepeg. 1 3 · The gate as described in item 2 of the patent application scope Structure, wherein the dielectric constant of the gate dielectric layer is greater than £ 1. 14. The gate structure according to item 13 of the patent application scope, wherein the material of the gate dielectric layer is selected from the following Groups formed: ^ Hf〇2, Ta2 05, Ti02, and ai203. · 2, 0503 -6236TW; TSMC2001 -0048; Esmond. Ptd p. 14 90114877_ (year 15 · The gate structure as described in item 1.2 of the patent application scope, wherein the dielectric constant ε 3 of the idle spacer is less than 3. 16 · The gate structure described in item 15 of the scope of patent application, wherein the material of the idle spacer is selected from the group consisting of: fluorine-doped silica glass (FSG), HSQ (hydrogen silsesquioxane) MSQ (methyl silsesquioxane), FLARE (made by Allied Signal), PAE-2 (made by Schumacher), and SILK (made by Dow Chemical). 17 · The gate structure as described in item 12 of the scope of patent application, wherein the dielectric constant ε i of the idle spacer is equal to 1. 1 8 · The gate structure as described in item 12 of the patent application scope, wherein the substrate has a source region, an electrodeless region, and a channel region therebetween 0 1 9 · as the patent application scope The gate structure according to item 12, wherein the gate has a stacked structure, which sequentially includes a first conductive layer formed on the gate dielectric layer, and a second conductive layer formed on the first conductive layer. On the floor. 2 0. The gate structure according to item 9 of the patent application scope, wherein the first conductive layer is selected from one of a doped polycrystalline silicon layer and a polycrystalline silicon germanium. 2 1 · The gate structure as described in item 9 of the patent application scope, wherein the first conductive layer is an undoped polycrystalline stone. 2 2 · The gate structure as described in item 12 of the scope of patent application, wherein the dielectric constant of the main spacer is between 3 and 10. 23. The gate structure as described in item 22 of the scope of the patent application, wherein the material of the main spacer is selected from the group consisting of oxide stone, nitride 492087 6. Scope of patent application Silicon and silicon oxynitride. 2 4 · A method for manufacturing a gate structure, including the following steps: (a) forming / high dielectric constant dielectric layer on a semiconductor substrate; (b) forming a conductive layer on the dielectric layer; c) the meaning of the conductive layer and the high dielectric constant dielectric layer to form a gate and a gate dielectric layer respectively; (d) forming an idle spacer with a low dielectric constant on the side wall of the gate; And (e) forming a main spacer on a side wall of the idle spacer. 25. The method according to item 24 of the scope of patent application, wherein step (a) _ is to form a dielectric layer with a dielectric constant greater than 10. 26. The method as described in item 25 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of: Zr02, Hf02, Ta205, Ti02, and Al203. 27. The method of claim 24, wherein step (b) includes forming a first conductive layer on the gate dielectric layer, and forming a second conductive layer on the first conductive layer. On the floor. • 28. The method as described in item 27 of the patent application scope, wherein the first conductive layer is selected from x-one of a doped polycrystalline silicon layer and a polycrystalline silicon germanium. 29. One of the methods described in item 27 of the scope of patent application. The conductive layer is undoped polycrystalline silicon. /, Τ β, I, where step (c) is performed on the semiconductor substrate 30. The method described in item 24 of the scope of patent application and step (d) further include ... Doping process. ’ 3 1 · The method according to item 24 of the scope of the patent application, wherein step (d) is to form an idle spacer having a dielectric constant of less than 3. 3 2 · The method as described in item 31 of the scope of the patent application, wherein the material of the 5 xuan idle spacers is selected from the group consisting of: fluorine doped stone glass (FSG), HSQ (hydrogen sil sesQUioxane) MSQ ( methyl s i1sesqu i oxane), FLARE (made by Allied Signal), PAE-2 (made by Schumacher), and SILK (made by Dow Chemical). 33. The method according to item 24 of the patent application scope, wherein after step (e), the method further comprises: using the gate electrode and the main spacer as a mask to perform a doping process on the semiconductor substrate. 3 4 · A method for manufacturing a gate structure, including the following steps: (a) forming a high-k dielectric layer on a semiconductor substrate; (b) forming a conductive layer on the dielectric layer; c) defining the conductive layer and the high dielectric constant dielectric layer to form a gate and a gate dielectric layer respectively; (d) forming an idle spacer on the side wall of the gate; (e) at the idle A sidewall of the spacer forms a main spacer; and (f) selectively removing the idle spacer to form a gap between the gate and the main spacer. 35. The method as described in claim 34, wherein the material of the idle spacer has a high etching selectivity with respect to the material of the main spacer. 3 6-A method for manufacturing a gate structure, including the following steps: (a) forming a dielectric layer on a semiconductor substrate, the gate dielectric layer 0503 -6236TWF1; TSMC2001 -0048; Esmond.ptc page 17 492087 6. The scope of the patent application has a first dielectric constant of £ l; (b) a conductive layer is formed on the dielectric layer, and the conductive layer has a Two dielectric constants; (c) defining the conductive layer and the dielectric layer to form a gate and a gate dielectric layer, respectively; (d) forming an intervening spacer on the side wall of the gate, the idle spacer Having a third dielectric constant ε3; and (e) forming a main spacer on a side wall of the idle spacer, the main spacer having a fourth dielectric constant e4, wherein £ 2> £ ι> ε4> ε3. I 37. The method as described in claim 36, wherein step (a) is to form a dielectric layer having a dielectric constant greater than 10. 38. The method according to item 36 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of: Zr〇2, Hf 02, Ta205, Ti02, and Al203. 39. The method of claim 36, wherein step (b) includes: forming a first conductive layer formed on the gate dielectric layer, and forming a second conductive layer formed on the first conductive layer. On the floor. 40. The method according to item 39 of the application, wherein the first conductive layer is selected from one of a doped polycrystalline silicon layer and a polycrystalline silicon germanium. < 41. The method as described in claim 39, wherein the second conductive layer is undoped polycrystalline silicon. 〃 42. The method as described in item 36 of the scope of patent application, wherein steps (c) and (d) further include: using the gate electrode to cover the semiconductor substrates & The bottom is lightly doped. ^ 4 3 · The method described in item 36 of the patent application, wherein step (d) is to form an idle spacer with a dielectric constant of less than 3. 44. The method according to item 43 of the scope of patent application, wherein the material of the idle spacer is selected from the group consisting of: fluorine-doped silica glass (FSG), HSQ (hydrogen silsesquioxane) MSQ (methyl silsesQui〇 xane), fLare (made by Allied Signal), PAE-2 (made by Schumacher), and SILK (made by Dow Chemical). 45. The method according to item 36 of the scope of patent application, wherein step (e) is to form a main spacer having a dielectric constant between 3 and 〇. 46. The method according to item 45 of the scope of patent application, wherein the material of the main spacer is selected from the group consisting of silicon oxide, silicon nitride, and oxynitride. 47. According to the method described in the item No. 1 of the Shenqing Patent Fanyuan ’, after step (e), the method further includes: using the gate and the; spacer as a mask, performing a thick impurity doping process on the semiconductor substrate. 19th buy 0503 -6236TWF1; TSMC2001 -0048; Esmond.p t c