490763 五、發明說明（1) 本發明係有關於一種在半導體基底上沉積絕緣層之方 法’特別有關於一種使用高密度電漿（High Density490763 V. Description of the invention (1) The present invention relates to a method for depositing an insulating layer on a semiconductor substrate, and more particularly to a method using a high density plasma (High Density
Plasma)進行未摻雜石夕玻璃層（und〇ped silicate Glass) 之化學氣相沉積（Chemical Vapor Deposition)方法，在 進行隔離槽（trench)填補（gap filling)時，可避免被沉 積層因遭受濺擊（sputter)所產生之雜散粒子阻塞隔離槽 而造成晶片上之缺陷。 近年來由於積體電路之尺寸越來越小，使得在積體電 =中=來做為元件間絕緣之用的溝槽（trench)也越來越 乍，思即其長寬比越來越高。在具有高長寬比的溝槽中使 用傳統之化學氣相沉積法進行絕緣層之沉積時，會造成絕 ^層中產生許多空洞（V〇id)。因此，在高長寬比溝槽中進 打絕緣層之沉積時，一般均使用可提供較高長寬比沉積層 之尚密度電漿化學氣相沉積法（HDp—CVD)來進行。 高密度電漿化學氣相沉積法與傳統化學氣相沉積法最 处2不同係'•其在反應氣體中被沉積層之附近提供一射頻 = =(RF energy)。此射頻能量包含一源射頻能量（srf)及 一偏射頻能量（BRF)，源射頻能量將反應氣體解離 (r:=i〇n)而形成電毁，偏射頻能量則提供電漿中之 離子轟擊（bombardment)被沉積表面所需之能量。因此， =密度電聚化學氣相沉積法會同時對被沉積層進行濺擊蝕 xKsputter-etching)及沉積。藉此，高密度電漿化 ;沉積法不需在高溫之環境下1可使被沉積層與反應氣 體進行化學反應。 谓θ，、久應虱Plasma) chemical vapor deposition (undoped silicate glass) chemical vapor deposition (Chemical Vapor Deposition) method, when performing trench filling (trench filling), can avoid the deposited layer due to suffering The stray particles generated by the sputter block the isolation trench and cause defects on the wafer. In recent years, as the size of integrated circuits has become smaller, the trenches used for the insulation between components have become more and more obvious. high. When a conventional chemical vapor deposition method is used to deposit an insulating layer in a trench having a high aspect ratio, many voids (Voids) are generated in the insulating layer. Therefore, when depositing an insulating layer in a high aspect ratio trench, a high density plasma chemical vapor deposition (HDp-CVD) method that can provide a higher aspect ratio deposited layer is generally used. The difference between the high-density plasma chemical vapor deposition method and the traditional chemical vapor deposition method is that it provides a radio frequency (RF energy) near the layer to be deposited in the reaction gas. This radio frequency energy includes a source radio frequency energy (srf) and a bias radio frequency energy (BRF). The source radio frequency energy dissociates the reactive gas (r: = i〇n) to form electrical destruction. The bias radio frequency energy provides ions in the plasma. The energy required to bombard the deposited surface. Therefore, the = density electropolymerized chemical vapor deposition method will simultaneously perform sputtering and deposition on the deposited layer (xKsputter-etching) and deposition. Thereby, the high-density plasmatization; the deposition method does not need to be in a high-temperature environment, and the chemical reaction between the deposited layer and the reaction gas can be performed. Called θ, long-term lice
五、發明說明（2) 第1圖； 聚^化學氣相 螭沉積之方 首先， 及矽酸鹽氣 量，此時便 5〇 A厚之矽 接著， 1 5 〇 0瓦以下 螭層。 最後， 代上述之低 槽被填滿。 然而在 一次在僅有 旦在低偏射 行濺擊時， 氧化吩層）病 化學反應會 之進行而產 因此， 度電漿進行; 底。將該基> 頻能量以形， •、員不了傳統在一爐箱（chamber)内使用高 晶圓之隔離溝槽中進行未推匕玻 f步驟11，在爐箱内之反應氣體（氩氣 體)中提供一約_瓦之源射頻能 隔離溝槽底部及側壁形成一約 在步驟1 2中，繼續提供該源頻能量並再加一 之低偏射頻能量，再沉積一厚約i50 Α之矽玻 ，將一約30 00瓦之全偏射頻能量取 、頻此S，開始進行主沉積動作直至隔離溝 上述傳統之HDP-CVD USG沉積方法中，由於第 源2頻能量時所形成之矽玻璃層只有5〇人，一 頻旎ϊ或全偏射頻能量被提供而開始對晶圓進 會使其下之半導體層（如矽基底、氮化矽層或 卜電漿產生化學反應。在實際之經驗中，此種 f生約5〜6/m大小之雜散粒子，阻礙沉積動作 缺陷。逆種缺陷使產品之良率降低約1 0%。 …了解決上述問題，本發明提供一種使用高密 緣層/儿積之方法，包括以下步驟。提供一基 j入一反應氣體中。提供該反應氣體一源射 一電漿而在該基底上沉積一第一絕緣層。再 490763 五、發明說明（3) ^序提供該電漿一低偏射頻能量及一全偏射頻能量而使該 絕緣層被濺擊蝕刻並同時沉積一第二及第三絕緣層。 :，忒第一絕緣層具有一厚度使該第一絕緣層被濺擊蝕 刻時仍保持該基底與該電漿隔離。 功缺ϊ Γ ’基底係一石夕基底。反應氣體係由氬氣、氧氣及 古二孤軋體混合而成。源射頻能量約為4〇〇〇瓦。電漿為一 2密度電漿。帛-、第二及第三絕緣層為未摻雜之矽玻璃 工。第-絕緣層之厚度大於200 A。第二絕緣 度約 瓦低偏射頻能量約伽瓦’而全偏射頻能量約 本發 絕緣層沉 底上依序 明之另 積之方 目的在於提供一種使用高密 度電漿進行 供一基底。在該基 。餘刻該氮化層、 中之凹槽。在該凹 化層。將具有該氮 法，包括以下步驟。提 層及一氮化層 一深及該基底 形成一第二氧 之該基 形成一第一氧化 第一氧化層及基底而形成 基底中之側壁上 槽位於該 化層、第 中。提供 第一絕緣 射頻能量 及第三絕 絕緣層被 與該電漿 v 本發 將該絕緣 一、第二氧化層 該反應 層。再 而使該 緣層。 濺擊蝕 隔離。 明藉由 層之厚 及凹槽 氣體一源射頻能 依序提供該電聚 第一絕緣層被濺 第一絕 持該第 其中，該 刻時仍保 在第一次提供偏 度增加，使其能 底置入 里以形成一電 一低偏射頻能 擊餘刻並同時 緣層具有一厚 二氧化層、氮 一反應氣體 漿而沉積一 量及一全偏 沉積一第二 度使該第一 化層及基底 射頻能量形成絕緣層時， 夠耐觉爾後所進行之減擊V. Description of the invention (2) Figure 1; Poly ^ chemical vapor rhenium deposition method First, and the volume of silicate gas, at this time, 50 A thick silicon, and then a layer of rhenium below 1 500 watts. Finally, the low groove is filled up instead. However, at one time, only when the splatter strikes at low polarization, the chemical reaction of the oxidized phenol layer will occur and therefore the plasma will be performed; This base > frequency energy can be shaped. • It is impossible to perform the traditional push-in step 11 in a trench using a high-wafer isolation trench in a chamber. The reaction gas (argon in the furnace) Gas) to provide a source of about _ watts of RF energy to isolate the bottom and sidewalls of the trench to form an approx. In step 12, continue to provide the source frequency energy and add a low bias RF energy, and then deposit a thickness of about i50 Α Silicon glass takes a full-bias RF energy of about 30,000 watts and repeats this frequency to start the main deposition operation until the isolation trench. In the above-mentioned conventional HDP-CVD USG deposition method, it is formed due to the second-source energy. There are only 50 people in the silica glass layer. A frequency chirped or fully biased RF energy is provided and starting to enter the wafer will cause a semiconductor layer (such as a silicon substrate, a silicon nitride layer or a plasma) to generate a chemical reaction. In actual experience, this kind of stray particles with a size of about 5 to 6 / m hinder the defect of the deposition action. The reverse defect reduces the yield of the product by about 10%.… To solve the above problem, the present invention provides a The method of using the high density margin layer / child product includes the following steps. Provided A base j is put into a reactive gas. A source is irradiated with a plasma to provide a reactive gas and a first insulating layer is deposited on the substrate. 490763 V. Description of the invention (3) ^ Provide the plasma with a low-bias RF Energy and a fully biased RF energy, the insulating layer is sputter-etched and a second and a third insulating layer are simultaneously deposited.: The first insulating layer has a thickness such that the first insulating layer is still etched by the spatter. Keep the substrate isolated from the plasma. The power shortage Γ 'substrate is a Shixi substrate. The reaction gas system is a mixture of argon, oxygen, and ancient two isolated rolling bodies. The source RF energy is about 4,000 watts. Electricity The slurry is a 2-density plasma. 帛-, the second and third insulation layers are undoped silica glass. The thickness of the first insulation layer is greater than 200 A. The second insulation degree is about watts, and the low-frequency RF energy is about gigawatts. 'The full bias RF energy is about the order of the product on the bottom of the insulating layer. The purpose is to provide a substrate using high-density plasma. On the substrate. The nitride layer, the groove in the rest of the time In the concave layer, the nitrogen method will be included, including the following steps. Layer and a nitride layer deep and the substrate forms a second oxygen, the base forms a first oxide, the first oxide layer and the substrate to form a side wall in the substrate, and an upper groove is located in the substrate and the second layer. Provides first insulation The radio frequency energy and the third insulating layer are connected with the plasma v, the insulating layer, the second oxide layer, and the reaction layer. Then the edge layer is formed. Splash erosion is isolated. By the thickness of the layer and the groove The gas-source RF energy can sequentially provide the first insulating layer of the polycondensation. The first insulation layer is spattered, and at this moment, it is still maintained at the first increase in the bias, so that it can be placed in the bottom to form an electricity. A low-bias RF energy strikes for a while and the edge layer has a thick dioxide layer, nitrogen-reactive gas slurry to deposit a quantity and a fully-biased deposition for a second time to make the first chemical layer and the substrate RF energy form an insulating layer At the end of the day
490763 五、發明說明（4) 蝕刻，而將其下之基底、氮化層或氧化層與電漿保持隔 離、不反應，即免去了雜散粒子之產生而提高了良率。 以下’就圖式說明本發明之一種使用高密度電漿進行 絕緣層沉積之方法實施例。 圖式簡單說明 第1圖係傳統之高密度電漿化學氣相沉積法流程圖； 、 第2A至2(?圖顯示依本發明之高密度電漿化學氣相沉積 法一實施例之製造流程。 符號說明： 2 0〜基底； 201、202〜主動區； 2 1〜墊氧化層； 2 2氮化層； 23〜爐内氧化層； 24、25、26〜石夕玻璃層； 27〜凹槽。 實施例 首先，如第2A圖所示，提供一矽基底20。 如第2B圖所示，在矽基底2〇上形成一墊氧化矽層（pa(i 〇xide)21及一氮化矽層22。 如第2C圖所示，經由蝕刻形成一深及基底2〇中之凹槽 27。凹槽27係做為其兩側兩個主動區（active area)201、 2 0 2間絕緣之用。 如第2D圖所示，由於凹槽27之側壁使基底20暴露而產490763 V. Description of the invention (4) Etching, while keeping the underlying substrate, nitrided layer or oxide layer from the plasma to be non-reactive, that is, the generation of stray particles is avoided and the yield is improved. Hereinafter, an embodiment of a method for depositing an insulating layer using a high-density plasma according to the present invention will be described with reference to the drawings. The figure briefly illustrates that the first figure is a flowchart of a conventional high-density plasma chemical vapor deposition method; and 2A to 2 (? Shows a manufacturing process of an embodiment of the high-density plasma chemical vapor deposition method according to the present invention Symbol description: 2 0 ~ substrate; 201, 202 ~ active area; 2 1 ~ pad oxide layer; 2 2 nitride layer; 23 ~ furnace oxide layer; 24, 25, 26 ~ Shixi glass layer; 27 ~ concave First, as shown in FIG. 2A, a silicon substrate 20 is provided. As shown in FIG. 2B, a silicon oxide layer (pa (ioxide) 21 and a nitride) are formed on the silicon substrate 20. Silicon layer 22. As shown in FIG. 2C, a groove 27 deep in the substrate 20 is formed by etching. The groove 27 is used as an insulation between two active areas 201 and 202 on both sides thereof. As shown in FIG. 2D, the substrate 20 is exposed due to the side wall of the groove 27 and is produced.
0503-6142tw;tsmc2000-0827;vincent.ptd 第7頁 發明說明（5) JL· 生一爐内氧化矽層（furnace oxde 1 iner)23。 =E圖所示’在爐箱中充入氬氣、氧氣及矽酸鹽氣 Γ = ΐ 7 反應氣體並提供一約4000瓦之源射頻能量， 使反應氣體形成一高來声雷將 η。 而沉積-厚声兔二水時使晶圓與此電漿反應 、予又為20〇A以上之未摻雜矽玻璃層24。 ，第2F圖所不’持續提供源射頻能量並加入 ^之低偏射頻能量’使晶圓表面開子 =亍濺擊姓刻同時持續進行沉積而形】= 璃層25 ’其厚度約為15〇 A。 战另纟摻雜矽玻 射頻i^?i2G圖所示’持續提供源射頻能量並使低偏 耵頻此里加向為一約3〇〇〇瓦之全 旦 I使低偏 步驟，使凹样2 7 ☆入；μ 十頻月匕里以進行主沉積 本發= 填滿。 未摻雜矽玻璃層厚度提高至20。A V上^頻二置在時所產生之 低偏射頻能量及全偏射頻能量 At使传在開始提供 Π其下之基底、氮化層、氧化層之ί擊而 免產生雜散粒子之目的。 ，、電漿反應，達到避 雖然本發明已以一較佳實施 以限定本發明，任何熟習此項技蓺】路：上，然其並非用 精神和範圍内’當可作更動與潤飾 ：：離本發明之 圍當視後附之申請專利範圍所界定者本發明之保護範0503-6142tw; tsmc2000-0827; vincent.ptd page 7 Description of the invention (5) JL · Furnace oxde 1 iner 23 in a furnace. = E shown in the picture ′ Fill the furnace with argon, oxygen and silicate gas Γ = ΐ 7 reaction gas and provide a source RF energy of about 4000 watts, so that the reaction gas will form a high noise thunder η. The un-doped silica glass layer 24, which reacts the wafer with the plasma at the time of depositing-thick-sounding rabbit dihydrate, is more than 20A. , Figure 2F does not 'continuously provide source RF energy and add low-bias RF energy' to make the wafer surface opener = splattering and engraving while continuous deposition]] = glass layer 25 'its thickness is about 15 〇A. In addition, doped silicon glass radio frequency i ^? I2G picture shows' continuously provide the source radio frequency energy and make the low bias chirp frequency here to a full denier of about 3,000 watts I make the low bias step to make the concave sample 2 7 ☆ Enter; μ Ten-Frequency Moon Dagger for Main Deposition Hair = Fill up. The thickness of the undoped silica glass layer is increased to 20. The low-bias RF energy and the fully-biased RF energy At generated when the A and V frequencies are placed at the same time, so as to prevent the stray particles from being generated at the beginning of the substrate, the nitride layer, and the oxide layer. , Plasma reaction, to achieve avoidance Although the present invention has been implemented with a preferred method to limit the present invention, anyone familiar with this technique can be used: Road, but it is not used within the spirit and scope 'when it can be modified and retouched :: The scope of protection of the present invention is defined by the scope of patent applications attached to the present invention.