TW487978B - Method of fabricating a non-volatile memory device to eliminate charge loss - Google Patents
Method of fabricating a non-volatile memory device to eliminate charge loss Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 230000004888 barrier function Effects 0.000 claims abstract description 52
- 238000005247 gettering Methods 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 45
- 230000015654 memory Effects 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 58
- 125000004429 atom Chemical group 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000005496 tempering Methods 0.000 description 4
- AJSTXXYNEIHPMD-UHFFFAOYSA-N triethyl borate Chemical compound CCOB(OCC)OCC AJSTXXYNEIHPMD-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- WVLBCYQITXONBZ-UHFFFAOYSA-N trimethyl phosphate Chemical compound COP(=O)(OC)OC WVLBCYQITXONBZ-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101001047746 Homo sapiens Lamina-associated polypeptide 2, isoform alpha Proteins 0.000 description 1
- 101001047731 Homo sapiens Lamina-associated polypeptide 2, isoforms beta/gamma Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 102100023981 Lamina-associated polypeptide 2, isoform alpha Human genes 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- OXRMMGBHYZHRMG-UHFFFAOYSA-N [Si].[Ar] Chemical compound [Si].[Ar] OXRMMGBHYZHRMG-UHFFFAOYSA-N 0.000 description 1
- 229910001413 alkali metal ion Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006884 silylation reaction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
487978487978
發明之領域 本發明係關於一種具高數據維持能力(high data retention)之非揮發性記憶體(n〇n-volatile iiIlem〇ry)製 程方法’尤指一種有效防止移動性氫原子擴散的非揮發性 記憶體製程方法’以減少記憶體電荷儲存流失。 背景說明 在半$體‘私中’當金屬化(metaiiizati〇n)與平坦 化(planarizat ion)等後段(back —end)製程都完成之後, _ 半導體晶片上之積體電路的主要架構便呈現出來。而這些 剛元成主要製权的積體電路容易因不經意的碰撞或曝露於 含有水氣的環境下太久而受到損害,或者經由鹼金屬離子 的擴散而影響元件特性,因此半導體晶片的表面上在進行 封裝(package}之前都會再覆蓋一吸氣層(gettering layer)或保護層(passivation),以保護其下方的積體電 路。常見的吸氣層材料有磷矽玻璃(ph〇sph〇siHcate glass,PSG)以及爛碟矽破螭(b〇r〇ph〇sph〇silicate glass, BPSG)° 隨著積體電路積隼声& 多伴隨產生的問題也逐$突 (short channel e f f e〇 t) > 增加以及元件尺寸的縮小,許 顯出來,例如短通道效應 熱載子(hot carrier)現象以FIELD OF THE INVENTION The present invention relates to a non-volatile memory (non-volatile memory) process method with high data retention (especially a non-volatile memory that effectively prevents the diffusion of mobile hydrogen atoms). Sexual memory system approach 'to reduce memory charge storage drain. Background note After the back-end processes such as metalization (metaiiization) and planarization (planarizat ion) are completed, the main structure of the integrated circuit on the semiconductor wafer is presented. come out. And these integrated circuits whose main power is controlled are liable to be damaged by accidental collision or exposure to an environment containing water vapor for too long, or the element characteristics are affected by the diffusion of alkali metal ions, so the surface of the semiconductor wafer Before the package is packaged, a gettering layer or a passivation layer is covered to protect the integrated circuit underneath. The common gettering layer material is phosphosilicate glass (ph〇sph〇siHcate) glass (PSG) and rotten disc silicon break (b〇ρ〇ph〇sph〇silicate glass, BPSG) ° As the integrated circuit circuit sound & many accompanying problems also emerged (short channel effe〇t ) > Increasing and shrinking the component size may show up, such as the short channel effect hot carrier phenomenon
苐5頁 487978 五、發明說明(2) 及帶電雜質離子(charged impurity ion)或移動性離子 (m〇b i 1 e i ο η )的擴散現象。以非揮發性(η ο η - v ο 1 a t i 1 e )記 憶體為例,例如可抹除且可程式化唯讀記憶體(er asab i e and programmable read only memory, EPROM)、快閃記 憶體(f 1 a s h m e m o r y )以及可電抹除且可程式化唯讀記憶體 (electrically erasable programmable read only memory, EEPROM),就常發生記憶陣列中高溫數據維持能 力(high temperature data retention)下降的情幵)。一 般認為這是由於移動性氫原子穿透吸氣層,再擴散進入非 揮發記憶體的浮動閘極(f 1 〇 a t i n g g a t e )中,造成原先健 存於浮動閘極中的電荷流失(c h a r g e 1 o s s )。 雖然,或許在某些情況下,自由氫原子(f r e e h y d r o g e n a t o m )擴散可能帶來好處,例如氫原子可與問極 氧化層-石夕介面之間的懸鍵(d a n g 1 e b ο n d )產生石夕-氣 (S i - Η )共價鍵結或;δ夕-氫氧基(S i - 0 Η )鍵結,降低懸鍵可能 改變Μ0S元件啟始電壓(threshold voltage)的機率。然 而,在非揮發性記憶體元件中,矽—氫(S i -H )共價鍵結或 矽-氫氧基(Si-0H)卻容易被在進行寫入(programming)時 注入浮動閘極的高速電子打斷,產生熱載子現象,亦可^ 造成氫原子穿過閘極氧化層擴散進入浮動閘極中。 % 〇 為了避免移動性原子對M0S元件或記憶體單元的影 響,在美國專利第6 0 7 1 784號中,Mehta等人提供τ α苐 Page 5 487978 V. Description of the invention (2) and the diffusion phenomenon of charged impurity ions or mobile ions (m0b i 1 e i ο η). Take non-volatile (η ο η-v ο 1 ati 1 e) memory as examples, such as er asab ie and programmable read only memory (EPROM), flash memory (F 1 ashmemory) and electrically erasable programmable read only memory (EEPROM), it often happens that the high temperature data retention in the memory array decreases.) . It is generally believed that this is because the mobile hydrogen atoms penetrated the getter layer and then diffused into the floating gate (f 1 〇atinggate) of the non-volatile memory, causing the charge 1 oss originally stored in the floating gate to be lost. ). Although, in some cases, the diffusion of free hydrogen atoms (freehydrogenatom) may bring benefits, for example, the dangling bond (dang 1 eb ο nd) between the hydrogen atom and the interfacial oxide layer-Shi Xi interface produces Shi Xi- Gas (S i-Η) covalent bonding or δ Xi-hydroxyl (S i-0 Η) bonding, reducing the probability that dangling bonds may change the threshold voltage of the MOS device. However, in non-volatile memory devices, silicon-hydrogen (S i -H) covalent bonding or silicon-hydrogen (Si-0H) are easily injected into the floating gate during programming. The high-speed electron interruption generates hot carrier phenomenon, which can also cause hydrogen atoms to diffuse through the gate oxide layer and diffuse into the floating gate. % 〇 In order to avoid the influence of the mobile atom on the MOS element or the memory unit, in US Patent No. 6 0 1 784, Mehta et al. Provide τ α
487978 五、發明說明(3) 用高溫回火(a η n e a 1 i n g )氮化石夕以及氮氧化石夕層以降低非 揮發性記憶體電荷流失的方法。Mehta等人在MOS元件上覆 蓋一阻障層(barrier layer)或I虫刻停止層(etch stop 1 ay e r ),隨後進行一 7 5 0°C左右的高溫回火製程,以將阻 障層或餘刻停止層中的移動性氫原子趕出來,然後再於阻 障層或钱刻停止層上形成一介電層。然而此製程的缺點是 需要進行一額外的高溫熱製程,對於進行至後段製程的半 導體產品較為不利,這是由於高溫熱製程容易造成元件性 質的改變。此外,Mehta等人亦忽略了移動性氫原子可能 經由接觸洞(c ο n t a c t h ο 1 e )擴散進入半導體元件中的可 能。 因此,本發明之主要目的在於提供一種不需要利用高 溫回火處理阻障層的半導體製程方法,以降低非揮發性記 憶體電荷流失,維持記憶體的數據維持能力。 本發明之另一目的在於提供一種非揮發性記憶體製程 方法,以有效隔絕移動性氫原子擴散進入半導體元件中。 發明之詳細說明 請參閱圖一至圖六,圖一至圖六為本發明較佳實施例 之示意圖。首先,如圖一所示,圖一顯示一非揮發性記憶 體之部份區域1 0的剖面放大圖,區域1 0係由一場氧化487978 V. Description of the invention (3) A method of tempering (a η n a a i n g) nitride nitride and oxynitride layers at high temperature to reduce charge loss of non-volatile memory. Mehta et al. Covered a barrier layer or etch stop 1 ay er on the MOS device, and then carried out a high temperature tempering process at about 7500 ° C to remove the barrier layer. Or, the mobile hydrogen atoms in the stop layer are driven out in a short time, and then a dielectric layer is formed on the barrier layer or the stop layer. However, the disadvantage of this process is that an additional high-temperature thermal process is required, which is disadvantageous for semiconductor products that go to the later stages. This is because the high-temperature thermal process easily causes changes in component properties. In addition, Mehta et al. Also ignored the possibility that mobile hydrogen atoms may diffuse into the semiconductor element through the contact hole (c ο n t a c t h ο 1 e). Therefore, the main object of the present invention is to provide a semiconductor manufacturing method that does not require high temperature tempering treatment of the barrier layer, so as to reduce the charge loss of the non-volatile memory and maintain the data maintaining ability of the memory. Another object of the present invention is to provide a non-volatile memory system method for effectively isolating the diffusion of mobile hydrogen atoms into a semiconductor device. Detailed description of the invention Please refer to Fig. 1 to Fig. 6, which are schematic diagrams of a preferred embodiment of the present invention. First, as shown in FIG. 1, FIG. 1 shows an enlarged cross-sectional view of part 10 of a nonvolatile memory. The area 10 is oxidized by a field.
第7頁 487978 五、發明說明(4) (f i e 1 d ο X i d e )層區域1 4以及1 6所隔離。為方便說明本發 明之技術特徵,非揮發性記憶體之其它區域,例如週邊電 路區域以及其它記憶陣列單元,則不顯示在圖一以及隨後 之其它圖示中。此外,區域1 0亦可以利用其它電性隔離 (electrical isolation )技術隔離,例如淺溝隔離 (shallow trench isolation,STI)技術。 本發明首先於區域1 〇之矽基底1 2上形成一堆疊記憶體 閘極結構1 1,包括有一浮動閘極1 8、一 〇 N 〇介電層2 〇形成 於浮動閘極1 8之上以及一控制閘極2 8堆疊於0N0介電層2 0 之上。浮動閘極1 8係藉由一閘極氧化層3 2與矽基底1 2隔Page 7 487978 V. Description of the invention (4) (f i e 1 d ο X i d e) layer areas 14 and 16 are isolated. In order to facilitate the description of the technical features of the present invention, other areas of the non-volatile memory, such as peripheral circuit areas and other memory array units, are not shown in Figure 1 and other subsequent figures. In addition, the area 10 can also be isolated using other electrical isolation (electrical isolation) technologies, such as shallow trench isolation (STI) technology. The present invention first forms a stacked memory gate structure 11 on a silicon substrate 12 in a region 10, which includes a floating gate 18 and a 10N dielectric layer 20 formed on the floating gate 18. And a control gate 28 is stacked on the 0N0 dielectric layer 20. The floating gate 1 8 is separated from the silicon substrate 1 2 by a gate oxide layer 3 2
離,用來儲存電荷。一源極2 2以及一汲極2 4則形成於堆疊 記憶體閘極結構1 1兩側的矽基 體閘極結構1 1並非本發明之重 熟知之技術,因此不再贅述詳 發明以堆疊記憶體結構為較佳 揮發性記憶體結構,例如分離 用於本發明之範圍。 底12中。由於製作堆疊記憶 點,且為習知該項技藝者所 細製程步驟。此外,雖然本 實施例,然而其它類似之非 閘極快閃記憶體,亦同樣適 ,如·圖一所示,利用化學氣相沈積(c h e m i c a 1 二P〇[ deP〇s丨tlon,CVD)技術,形成一未換雜石夕玻璃 i閘極二構I上” ^…33, USG)薄膜40覆蓋於堆疊記憶 源極22與沒極24之上以及石夕基底12表 ’、'。接者於未摻雜矽破璃薄膜40上形成一吸Away, used to store charge. A source electrode 22 and a drain electrode 2 4 are formed on both sides of the stacked memory gate structure 1 1. The silicon-based gate structure 1 1 is not a well-known technology of the present invention, so the detailed invention will not be described in detail. The body structure is preferably a volatile memory structure, such as a separation used in the scope of the present invention. Bottom 12. Because the stack memory points are made, it is a detailed process for those skilled in the art. In addition, although this embodiment, other similar non-gate flash memories are also suitable, as shown in FIG. 1, using chemical vapor deposition (chemica 1 2 P0 [deP0tlon, CVD) Technology, to form a non-exchanged slab glass gate I structure "^ ... 33, USG) film 40 covers the stacked memory source 22 and the electrode 24, and the slab substrate 12 table ','. Forming a suction on the undoped silicon broken glass film 40
487978 五、發明說明(5) 氣層42。吸氣層42的厚度約為7 0 0 0至9 0 0 0埃(angstrom)之 間,其可以為P S G、B P S G或其它具有類似吸氣特性之介電 層,在本較佳實施例中,則建議使用PSG作為吸氣層42的 材質。未摻雜矽玻璃薄膜4 0可用來阻擋吸氣層4 2中的雜 質,主要為调原子以及磷原子,進一步擴散至堆疊記憶體 閘極結構1 1。 PSG吸氣層42以及BPSG吸氣層42皆可利用常壓氣相沈 積(atmospheric pressure CVD, APCVD)技術或電聚加強 氣相沈積(plasma-enhanced CVD, PECVD)技術形成,利用 反應氣體如 B2F6、TEB (tri-ethyl borate)、PH 3、Τ Μ P0 (tri-methyl phosphate)、臭氧以及 TEOS (tetra-ethyl ortho-silicate),在溫度 40 0 至 55 0°C 下進行沈積。TEB、 TMPO以及TEOS在室溫常壓下皆為液態,因此在使用時,可 利用一發泡室(bubbler)並利用氮氣或氦氣等惰性氣體作 為載氣(carrier gas),將 TEB、TMP0或 TE0S帶入 CVD反應 器(未顯示)中。 仍然如圖二所示,在沈積吸氣層4 2之後,接著進行一 平坦化製程,例如化學機械研磨(c h e m i c a 1 m e c h a n i c a 1 p 0 1 i s h i n g,C Μ P )製程,平坦化吸氣層4 2。經過c Μ P研磨後 之吸氣層4 2的厚度可降低至約為5 0 0 0至7 0 〇 〇埃之間,端視 不同產品而定。例如,在本發明之較佳實施例中,堆疊記 ^體閘極結構11之最高點距離CMP後吸氣層42表面之距離487978 V. Description of the invention (5) Gas layer 42. The thickness of the gettering layer 42 is between about 70000 and 90000 angstroms. It can be PSG, BPSG, or other dielectric layers having similar gettering characteristics. In this preferred embodiment, It is recommended to use PSG as the material of the gettering layer 42. The undoped silica glass film 40 can be used to block impurities in the gettering layer 42, mainly tuning atoms and phosphorus atoms, and further diffuse to the stacked memory gate structure 11. PSG gettering layer 42 and BPSG gettering layer 42 can both be formed using atmospheric pressure CVD (APCVD) technology or electro-enhanced plasma deposition (plasma-enhanced CVD, PECVD) technology. Reactive gases such as B2F6, TEB (tri-ethyl borate), PH 3, TM P0 (tri-methyl phosphate), ozone, and TEOS (tetra-ethyl ortho-silicate) are deposited at a temperature of 40 to 55 ° C. TEB, TMPO, and TEOS are all liquid at room temperature and normal pressure. Therefore, when in use, a foaming chamber (bubbler) and inert gas such as nitrogen or helium can be used as the carrier gas (TEB, TMP0). Or TEOS is brought into a CVD reactor (not shown). Still as shown in FIG. 2, after the gettering layer 42 is deposited, a planarization process, such as a chemical mechanical polishing (chemica 1 mechanica 1 p 0 1 ishing, CMP) process, is performed to planarize the gettering layer 4 2 . The thickness of the getter layer 42 after cMP grinding can be reduced to between about 5000 and 700 angstroms, depending on different products. For example, in a preferred embodiment of the present invention, the distance between the highest point of the stacked gate structure 11 and the surface of the getter layer 42 after CMP
第9頁 487978 五、發明說明(6) 約為2 0 0 0至4 0 0 0埃左右,較佳為3 0 0 0埃。利用本發明方 法,吸氣層4 2的厚度可以減至最低,其優點是可以減少後 繽形成的接觸洞高寬比(a s p e c t r a t i 〇 )。 接下來’於吸氣層4 2上依序沈積一氧化層4 3以及一阻 障層44。氧化層43係利用PECVD方法形成,其厚度約為 2 0 0 0埃,可用來填補CMP製程在吸氣層42表面所產生的刮 痕。阻P早層4 4可以為氮氧化石夕(silicon oxy-nitride)、 氮化碎或其它具有類似阻絕移動性原子擴散之特性的材料 所構成,在本發明之較佳實施例中,則建議使用氮氧化石夕 作為阻障層44的材質。 氮氧化矽阻障層44的沈積係利用LPCVD方法形成,反 應氣體有石夕甲烧(silane)、氧化亞氮(nitr〇us 〇xide, 1〇)以及氮氣,反應壓力係介於5至6托耳(1^〇1^)之間,反 應溫度係介於3 5 0至451TC之間。依據上述條件所形成之 氧化矽阻障層44折射率(ref ract i〇n index,RI )需介於2 至 2·4之間(@UV248nm),而介電常數(dielectric constant, 1〇則需介於〇· 4至0· 6之間。氮氧化矽阻障 的厚度約為3 0 0至1 0 0 0埃,較佳為5 〇 〇埃。 層 刻Page 9 487978 V. Description of the invention (6) It is about 2000 to 400 angstroms, preferably 300 angstroms. By using the method of the present invention, the thickness of the gettering layer 42 can be reduced to a minimum, which has the advantage of reducing the aspect ratio (a s p e c t r a t i) of the contact hole formed by the rear bin. Next, an oxide layer 43 and a barrier layer 44 are sequentially deposited on the gettering layer 42. The oxide layer 43 is formed by the PECVD method, and has a thickness of about 2000 angstroms, which can be used to fill the scratches generated on the surface of the gettering layer 42 in the CMP process. The early P-blocking layer 4 4 may be composed of silicon oxy-nitride, nitrided nitride, or other materials having similar characteristics to block the mobility of atomic diffusion. In a preferred embodiment of the present invention, it is suggested that As the material of the barrier layer 44, oxynitride is used. The deposition of the silicon oxynitride barrier layer 44 is formed by the LPCVD method. The reaction gases include silane, nitrous oxide (nitr0us oxide, 10), and nitrogen. The reaction pressure ranges from 5 to 6. The reaction temperature is between 3 to 451TC. The refractive index (ref ract in index, RI) of the silicon oxide barrier layer 44 formed according to the above conditions needs to be between 2 and 2.4 (@ UV248nm), and the dielectric constant (dielectric constant, 10) It must be between 0.4 and 0.6. The thickness of the silicon oxynitride barrier is about 300 to 100 angstroms, preferably 500 angstroms.
,著如圖三所示,進行一黃光及蝕刻製程,於阻障 44、乳化層43、吸氣層42以及未摻雜矽玻璃薄膜4〇中钱 出一寬約0.2微米(micrometer)之接觸洞(c〇ntactAs shown in Figure 3, a yellow light and etching process is performed. A thickness of about 0.2 micrometers (micrometer) is obtained from the barrier 44, the emulsified layer 43, the getter layer 42, and the undoped silica glass film 40. Contact hole
487978 五、發明說明(7) h ο 1 e ) 5 0,通達沒極2 4。1十丨rr。恤《 ^ |層42以及未摻雜矽破璃^膜11\層44、乳化層43、吸氣 變蝕刻氣體等參數,或:使用同-蝕刻機台’只改 |知該項技藝者所熟知5 ==刻機台二而此技術為習 因此不再贅述詳細步驟。 面、户3 ί阻二^ 所不,於阻障層44表面以及接觸洞50表 十么層f F且障層52可以為氮氧化石夕(sil ic〇n 丨二X:二1二二从氬化矽或其它具有類似阻絕移動性原子擴 ;;Γί^ =成,在本發明之較佳實施例[Μ Uί::;; °ΛΛ"""52 .., Λ " 万/ΖΓ形成,反應氣體有矽甲烷 化/氮U2〇)以及氮氣’反應壓力係介於5至 I 2. 2 :4; I, Ti U : lf;l\ ^Λ( R 1 ^ ^ '^aLi ^ ί ί '' # ^ 25 0^35〇ί °mV' 马3 0 0埃。需注意的是 失罕乂仏 |厚度10至50%左右。P卩早層44的厗度約超過阻障層52 |接著如圖五所示,進行一回蝕 直至汲極24表面,以於接觸洞5〇之二^蝕刻阻障層52 子53。阻障側壁子53之厚度需最少ς f形成一阻障側壁 六所示,隨後於阻障層44以及阻障側辟00埃以上。如圖 黏著層(adhesive Uyer)55,其可5 3表面上形成一 1 了从為氮化鈦(TlN)/鈦 1 第11頁 487978 五、發明說明(8) (T i )複合金屬或其它習知該項技藝者所常使用之黏著材 料。最後進行一接觸插塞製程,利用傳統的CVD或其它方 法將接觸洞5 0填滿金屬鎢,隨後回蝕刻金屬鎢,蝕刻停止 於黏著層5 5上,從而完成接觸插塞5 6。 相較於習知方法,本發明能有效阻絕移動性原子的擴 散進入堆疊記憶體閘極結構1 1中,避免移動性原子,例如 自由氫原子以及水氣,造成的浮動閘極電荷流失,這要歸 功於阻障層4 4隔絕了移動性原子由堆疊記憶體閘極結構1 1 正上方擴散進入吸氣層4 2的路徑,以及阻障側壁子5 3阻絕 了移動性原子經由接觸洞5 0或接觸插塞5 6橫向擴散進入堆 I 疊記憶體閘極結構1 1的路徑。 簡言之,本發明方法至少具有以下之優點: (1 )能有效消除移動性原子對於記憶體元件,尤其是浮動 閘極,的影響; (2 )不需要進行高溫的回火製程;以及 (3 )可降低吸氣層4 2的厚度,減少接觸洞高寬比。 以上所述僅為本發明之較佳實施例,凡依本發明申請 專利範圍所做之均等變化與修飾,皆應屬本發明專利之涵 || 蓋範圍。487978 V. Description of the invention (7) h ο 1 e) 5 0, reachable pole 2 4. 1 10 rr. Shirt "^ | layer 42 and undoped silicon break glass ^ film 11 \ layer 44, emulsified layer 43, getter changed etching gas and other parameters, or: use the same-etching machine 'only to change | Familiar with 5 == Engraving machine two and this technique is a practice so I will not repeat the detailed steps. Surface, household 3, resistance 2 ^ No, on the surface of the barrier layer 44 and the contact hole 50, the surface layer F F and the barrier layer 52 may be oxynitride (sil icon 丨 II X: 2 1 22) From argon silicon or other atoms with similar resistance to mobility; Γί ^ = 成, in a preferred embodiment of the present invention [Μ Uί :: ;; ° ΛΛ " " " 52 .., Λ " / ZΓ formation, the reaction gas is silylation / nitrogen U2〇) and nitrogen 'reaction pressure is between 5 to I 2.2: 4; I, Ti U: lf; l \ ^ Λ (R 1 ^ ^' ^ aLi ^ ί ί '' # ^ 25 0 ^ 35〇ί ° mV 'Horse 3 0 0 Angstroms. It is important to note that the thickness is about 10 to 50%. The thickness of P 卩 early layer 44 is more than resistance. Barrier layer 52 | Next, as shown in FIG. 5, an etch-back is performed to the surface of the drain electrode 24 so that the contact hole 50 bis ^ etches the barrier layer 52 and the sub-layer 53. The thickness of the barrier side wall 53 needs to be formed at least f. A barrier sidewall 6 is shown, and then the barrier layer 44 and the barrier side are set at 00 angstroms or more. As shown in the adhesive layer 55 (adhesive Uyer) 55, it can form a 1 on the 3 surface from titanium nitride (TlN ) / Titanium 1 Page 11 487978 V. Description of the invention (8) (T i) compound Metal or other adhesive materials commonly used by those skilled in the art. Finally, a contact plug process is performed. The contact hole 50 is filled with metal tungsten by traditional CVD or other methods, and then the metal tungsten is etched back. The etching stops at The adhesive layer 5 5 is completed to complete the contact plug 56. Compared with the conventional method, the present invention can effectively prevent the diffusion of mobile atoms into the stacked memory gate structure 11 and avoid mobile atoms, such as free hydrogen. Atoms and water vapor cause floating gate charge loss, which is due to the barrier layer 4 4 blocking the path of mobile atoms diffused from the stacked memory gate structure 1 1 into the getter layer 4 2 and the barrier The barrier side wall 5 3 blocks the path of the mobile atom's lateral diffusion through the contact hole 50 or the contact plug 5 6 into the stack I of the stacked gate structure 1 1. In short, the method of the present invention has at least the following advantages: (1) Can effectively remove the influence of mobile atoms on memory elements, especially floating gates; (2) Does not require high temperature tempering process; and (3) Can reduce the thickness of the getter layer 4 2 Aspect ratio contact holes. The foregoing is only preferred embodiments of the present invention, where under this patent disclosure range of modifications and alterations made, also belong to the present invention patent || culvert cover range.
1 第12頁 487978 圖式簡單說明 圖示之簡單說明 圖一至圖六為本發明較佳實施例之方法示意圖。 圖示之符號說明 10 區域 11 堆疊記憶體閘極結構 12 矽 基 底 14、16 場 氧 化 層區 18 浮 動 閘 極 20 ΟΝΟ介電層 22 源 極 24 汲 極 28 控 制 閘 極 32 問 極 氧 化層 40 未 摻 雜 矽玻璃薄膜 42 吸 氣 層 43 氧 化 層 44、5 2 阻 障 層 50 接 觸 洞 53 阻 障 側 壁子 55 黏 著 層 56 接 觸 插 塞1 Page 12 487978 Simple description of the diagrams Simple explanation of the diagrams Figures 1 to 6 are schematic diagrams of the method according to the preferred embodiment of the present invention. Explanation of symbols in the figure 10 Region 11 Stacked memory gate structure 12 Silicon substrate 14, 16 Field oxide region 18 Floating gate 20 〇ΝΟ Dielectric layer 22 Source 24 Drain 28 Control gate 32 Interrogation oxide layer 40 Not Doped silica glass film 42 getter layer 43 oxide layer 44 5 barrier layer 50 contact hole 53 barrier sidewall 55 adhesive layer 56 contact plug
第13頁Page 13
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US10068912B1 (en) | 2017-06-05 | 2018-09-04 | Cypress Semiconductor Corporation | Method of reducing charge loss in non-volatile memories |
CN111785683B (en) * | 2020-07-17 | 2024-05-03 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
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US5874359A (en) * | 1995-04-27 | 1999-02-23 | Industrial Technology Research Institute | Small contacts for ultra large scale integration semiconductor devices without separation ground rule |
US5631179A (en) * | 1995-08-03 | 1997-05-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing metallic source line, self-aligned contact for flash memory devices |
-
2001
- 2001-06-28 TW TW090115840A patent/TW487978B/en not_active IP Right Cessation
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2002
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7936003B2 (en) | 2005-02-03 | 2011-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device having transistor with vertical gate electrode and method of fabricating the same |
TWI397111B (en) * | 2007-01-25 | 2013-05-21 | Au Optronics Corp | Layered structure with silicon nanocrystals, solar cell, nonvolatile memory element, photo sensitive element and fabrications thereof, and method for forming silicon nanocrystals |
US7902640B2 (en) | 2007-06-12 | 2011-03-08 | Au Optronics Corporation | Dielectric layer and thin film transistor |
Also Published As
Publication number | Publication date |
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US6713388B2 (en) | 2004-03-30 |
US20030003658A1 (en) | 2003-01-02 |
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