TW487975B - Active CMOS pixel device and method for making the same - Google Patents

Abstract

An active CMOS pixel device comprises: a substrate; a floating gate layer; and a control gate layer; in which the substrate comprises a well region and a first and second doped regions in the well region. The well region and the first and second doped regions are all exposed on the surface of the substrate, and the first and the second doped regions are separated from each other. The well region has a first polarity and the first and the second doped regions have a second polarity. The floating gate layer is installed on the well region and the boundary of the second doped region on the surface of the substrate, and is insulated from the well region and the second doped region and in electrical contact with the first doped region. The control gate layer is installed on the floating gate layer and is insulated from the floating gate layer.

Description

487971_ jl No. 90110259 "Year of the Year" Month $ _ Revision Self-Administration Feng Feng Yue Yue Japanese invention is related to an active complementary CMOS pixel device and its manufacturing method, and in particular to a method using a gate electrode The induced drain leakage current (GIDL) is used to sense the pixel attack of light. It has an excellent sensing effect on objects in strong light or weak light. Complementary metal-oxide-semiconductor (CMOS) image sensing elements are a new generation of image sensing technology. The active pixel sensing device of CMOS has the functional performance comparable to CCD (Charge Coupled Device), and it is in line with the trend of electronic products gradually becoming single-chip, low power consumption, low cost and small size. In E. Fossum, ’’ Image capture circuits in CMOS ,, paper # Bl, Proceedings of international conference5 on VLSI-technology, system and applications,

Taipei, p.52-57, 1997 discloses a conventional active pixel device of CMOS. Figure 1 shows the device. The pixel device includes a photodiode 11 and two CMOS transistors 12, 13, and 14. The gate of the transistor 12 receives a reset signal RS for resetting the potential of the diode π floating terminal (f 1〇ating node) A to Vcc. The transistor 13 is used as a source follower, and its gate is connected to the floating terminal A. In this way, the conductivity of the transistor 13 will be determined by the potential of the floating terminal A of the photodiode 11. After the reset action is performed, the photodiode U will start to accumulate electricity due to the photon's injection, which gradually changes the potential of the net terminal A, and also changes the potential of the source terminal of the transistor i3. When the transistor 14 receives the column read signal and starts to read the light, the electric body 14 is turned on, and the potential of the source 3 of the transistor 3 is turned on.

$ 4 pages 487975 V. Description of the invention (2) It is regarded as a light signal and sent through the output terminal V 〇. In addition, in addition to CMOS active pixel devices, there are also bipolar active pixel devices that use dual-electron solar cells. U.S. Patent No. 5,260,592 and M. Chi, T. Delbruck, N.

Mascarenhas, A · Bergemont, and C · Mead, '丨 A high resolution CMOS imager with active pixel using capacitively coupled bipolar operation ", paper # B2, Proceedings of International conference on VLSI-technology, system and applications, Taipei, Jun / 1 In 9 97, an active image device of a pair of carriers is disclosed. Figure 2 shows the device. The bi-carrier active pixel device 2 includes a bi-carrier junction body (BJT) 21, the base of which is connected to a capacitor 22 for controlling the bias of the base and / or emitter junctions. The base junction of the transistor 21 (base junction) is used to receive light and generate electric charges. When the transistor 2 丨 the base electrode 4 reversely biases the base emitter contact mask, the charges generated by the two light beams are accumulated in the base junction; when the transistor 21 base When the potential causes the base-emitter to be forward-biased, these charges can flow out through the emitter to generate a current signal and be amplified by the transistor 2. f Among the two types of active pixels, the CMOS active pixel It has lighter problems such as blooming and image-lag. The second line is about five times larger than the active pixel area of the double-carrier; the double-carrier main is smaller than ΓΜης. Area, but its brightness saturation and image delay issues have a lot of moving pixels, which is only suitable for processing static images.

487975% V Description of the invention (3) — Therefore, the present invention combines the advantages of the above two types of active pixels to provide a c ^ -type pixel with a small area and small brightness saturation and image delay problems. One of Wang Dong's inventions is to provide a pixel device, including: one of them, one of W & milk dry conductors. In the middle, λ bottom JL has a 2 r sub-connected gate layer and a control gate layer d I bottom has a -well area and the second __2 located in the well area; the area = the wide and the second doped area all expose the substrate Surface; Section :: A second polarity. The floating gate layer is located above the junction between the well area and the second :: = ί: and is in electrical contact with the well area and the second doped area: 2 :::: doped area. Above and insulated from the floating gate layer.卞 Pressing the polar layer ❹ΐ 明: Another purpose is to provide a kind of active complementary metal oxide pixel array device, including the shape of the breast semiconducting © 吴 — 你 &# to form a matrix with multiple rows and columns This system asks the polar layer. The substrate has a well region with an if, -inter-electrode layer, and a -doped region. , Area, -43 = The first and second i well areas in the well area have -polarity and -polarity. The floating gate layer is provided at the boundary between the i-th heterodyne region on the substrate surface of the well area plate and the first doped insulation layer and is electrically connected to the first-doped area and the top-dwelled area and the second doped area layer. It is insulated from the floating gate layer; the gate electrode layer is located in the insulation gap with the adjacent pixel device, the pixel electrode layer of the parent column is connected across the first doped bus:-control of the column pixel device ~ Doped & and insulated from the first doped region.

487975 V. Description of the invention (4) Yet another object of the present invention is to provide a method for manufacturing a conductive pixel array device, which is a $ -type complementary metal oxide semiconductor. A substrate having a first polarity, a donor substrate, and a second polarity separated from each other and having a second polarity is formed in the substrate. A first conductive layer is deposited. For the first insulating reed belt: the doped region is engraved to form a -floating gate, the floating gate: the upper part of the junction of the etching surface, and the first conductive layer / electrical edge layer and the second conductive layer . For the second insulating layer and the first conductive etch, a control gate is formed, and the control gate is located at the floating gate. In the present invention, only one photodiode and one output diode are used, making the area more traditional than CM0S pixels are small, and the brightness saturation and image delay problems of ^ CMOS pixels are lighter. At the same time, 'Because it uses the floating gate and source (second doped region) as the sensing current, it makes the exponentia relationship between the sensing luminosity and the sensing current, which is very suitable for strong light Photographing, tracking, or sensing of dynamic objects in low light. In the following, an embodiment of an active complementary metal-oxide semiconductor pixel device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. Brief description of the drawings FIG. 1 is a tradition Circuit diagram of a CMOS active pixel device; ^ 2 is a circuit diagram of a conventional dual-carrier active pixel device; Figures 3A to 3D show a CMOS active pixel according to an embodiment of the present invention

0503-6153TW; TSMC2000-0969; Vincent.ptd page 7 487975 V. Description of the invention (5) Device manufacturing method; Figure 4A is a CMOS active pixel plan view according to an embodiment of the present invention;

Figures 4B and 4C are cross-sectional views of a CMOS active image device according to an embodiment of the present invention; I Figure 5 is a timing chart of a CMOS active pixel device according to an embodiment of the present invention. [Symbol description] 11 ~ photodiode; 2 ~ bipolar active pixel 2 2 ~ capacitor; 31 ~ substrate; 33 ~ N type well area; 35, 36 ~ P type doped area; 3 9 ~ control gate 43 ~ contact hole; 1 ~ traditional CMOS active pixel; 12, 13, 14 ~ CMOS transistor 21-BJT; 3 ~ pixel area; 3 2 ~ shallow trench isolation oxide layer; 34, 38, 42 ~ silicon oxide layer ; 3 7 ~ floating gate; 4 Bu tungsten silicide layer; 44 ~ conductive layer. EXAMPLES Figures 3A to 3D show a method for manufacturing a CMOS active pixel device according to an example of the present invention. Figures 3A to 3F include a plan view and cross-sectional views cut on the two sides of the plan view along section lines AA 'and BB. Firstly, as shown in FIG. 3A, a stone evening substrate 31 is provided, and a shallow trench isolation (Shal 10w Trench Isolation) oxide layer 32 is formed on the stone evening substrate 31 to isolate the pixel regions 3 in different columns. Ion implantation method

0503-6153TW; TSMC2000-0969; Vincent.ptd Page 8 487975 V. Description of the invention (6)

Implantation) forms an n-type "silicon oxide layer 34" in the substrate 31, so that a p-type doped substrate will be formed later, and the "etched bottom" medium shape: =: implant. In this way, the doped regions 35 and 36 with different sizes are cut off at the base. Blending # ^ 35, 36 constitutes a pixel region 3. Doping & Then, as shown in FIG. 3B, a N-type doped polysilicon layer and a silicon oxide layer 34 are deposited to make an N-type floating gate: "formed in the P-type doped region 36 and The 1 ^ -type well region 33 is on the sixth surface of the substrate M, and one of the protruding sides 371 of the floating gate 37 and the doping region is in turn, and the connecting gate 37 is in electrical contact with the doped region 35 ... From time to time, as shown in Fig. 3G, the right ρΛ is sequentially re-deposited-an oxygen-cutting layer,-a polycrystalline silicon layer doped with erbium ions, and a tungsten silicide layer. Among them, the redundant crane layer: The photomask prevents Shi Xihua Crane from depositing in the doped region 35: square. Then, the oxide layer and the polycrystalline silicon layer are etched on the control gate 39 of the Shi Xihua Crane layer 41, a ^ Xi crystalline stone layer) 39 and the underlying insulating layer (oxidized stone layer) 38. Control 1 In addition, the doped region 35 and floating gate 37 in the outer ΔΤ Λ 3 In addition, the leakage & In the case, a tungsten silicide layer 41 can also be deposited on the doped region 36 to block light from entering the doped region 36. Finally, as shown in the figure, an inter-layer dielectric is deposited, and the oxide is doped on the oxide. Contact hole 43 in the miscellaneous area 36. A 、 日 # > into a storm circuit electrical layer, such as copper, and form a connection with 4: Xin 3 Ba Er sedimentary paleo-conductor as usual. 3 of the straight bar-shaped conductive 4 ^ 1SZi ：. |: L? JLm 90110259 4 repeated Niu rlt) month correction, 44: the conductive layer 44 fills the contact hole 43 and is connected to the doped region 36, so that all pixels of the same lamp The doped regions 36 of the region 3 are in electrical contact with each other. ^^ The same dielectric layer and conductive layer are also used on the tungsten silicide layer 41 covering the control gate 39, and the Shi Xihua town layer η does not pass through the -contact a port. The time is not shown in the figure. The cross-sectional view. For the line AA in Figure 4A, cut and cut the same series: one one ^^ ^; ί t ^ ^ p # # .j CM The cold, cold, and hot plate 丨 Fu Fengmu's pixel area 3 includes the right and left L 3, 36, 36, floating gate 37, crane layer 41, contact hole 43 and conductive layer 44. # 制 梯 极 39 , Shi Xihua /, the 'shallow trench isolation oxide layer 3 2' is used to describe the pixel region 3 type doped regions 35, 36 divided into two adjacent columns: ί ^ -3; ν ;: Γ / Sexual contact. In addition, the floating gate 3: 1: oxygen-doped region 35 is connected and Region 36, well region 33 insulated control gate electrode 3 ": Xi dagger stone layer 34 and the doped region of the pixel 3, which has an underlying silicon oxide stripe acoustic Κ same column and across the floating electrode 37 and closing. The control gate 39 is insulated on the doped region 35 and the gate 37 by theta oxidation. The control gate 39 is ^ f and the doped region 35 is two adjacent doped regions 35 0503-61537W1; TSMC2000-0969; Vincent. Ptc Page 10 V. Description of the invention (8) 4, ii = = ,; Parasitie transistQr) 4G. The Shi Xihua crane layer is placed on the control gate 37 above the doped region 36 fr of the same product 5 and can also be added to cover the fill gate (the layer 44 is not shown below) to cover the doped region 36. The oxidized stone layer 42 is used as the interlayer in the region V of the prime region 3. All the doped regions 36 in the same-row like contact domain are mutually electrically via 43 through the contact hole 43 and the conductive layer 44. K = The chemical layer 41 can also be formed with the conductive layer and contact, μ. ,,, σ冓 'in order to facilitate the application of voltage to the control gate 3.9, because of the conventional metal interconnection structure in 2 for the simplicity of illustration and description, + is shown in the figure and detailed. 、 In the above pixel array device In the pixel region, the size of the coupling coefficient γ between the “mx gate 39 and the floating gate 37 may be approximately to obtain the maximum signal range (dynamic range), and the size of the contact hole is 0 · 3 / zmx 〇 · 3 // m. The minimum width of the tungsten silicide layer 41 is 0.4. The operation of the above-mentioned pixel array placement will be described with reference to Figures 4A to 4C and Figure 5. 5 As shown in Figure 5, the above The pixel device has three operating states, namely reset, image accumulation and reading. Vcg, Vnw and Vfg represent the potentials of the control gate 39, the N-well region 33 and the floating gate 37, respectively, and Vcc represents greater than Threshold voltage of the parasitic transistor 40. First, when resetting In one column, set the potential of one of the doping regions 3 5 to -Vcc, and at the same time reduce the potential of the control gate 39 of the column to -Vcc. In this way, each parasitic transistor 40 is in an on state,- The potential of Vcc is transmitted to each doped region by the parasitic transistor 40 which is turned on

487975

The potential of the doped region 35 in the 35-type well is reset to -VCC. At this time, N private potential is set to Vce, and performing the same operation on each column of pixels can reset all doped regions 35. ^ Following the image accumulation time, f of the control gate 39 and the N-type well region 33 is pulled up to 0V, so that the parasitic transistor 40 is turned off, and the doped region 35 is illuminated by light. Electron pairs are generated, in which the neutrons / ;, L enter the N-type well region 3 3 and leave holes in the doped regions 3 5 to gradually increase their potential, so each doped region 35 and its electrical contact with it The potential of the floating electrode 37 will be determined by the amount of light received by the doped region 35. If not, it will be equal to -VCC. In addition, when the light received by the doped region 35 is too strong, the potential of the dopant is too high and a forward-bias is generated in the interface between the doped region and the N-type well region 33, and excess current will be introduced. The N-type well area will not be used as a signal output, which eliminates the problem of brightness saturation. At the last time when the tense is read, the potential of the N-type well area 33 is raised to ^ (:, then (about 1 / zs) The voltage of the control gate 39 is also increased to Vcc. The reason why the voltage of the control gate 39 is increased later than that of the N-type well region 33 is to prevent the positive interface between the doped region μ and the N-type well region 33 from generating The bias voltage causes the image potential to remain in the doped region 36. In addition, a sensing amplifier sa is also provided with the doped voltage Vref to the doped region 36. At this time, the floating gate 37 is controlled The coupling of the gate 39 causes its potential to jump by 7 · Vcc (y can be 0.5), and its potential range is between 0 and r · Vcc. Furthermore, because the potential of the floating gate ς 37 jumps, The magnitude of the electric field generated on the surface of the overlapping portion of the doped region 36 and the floating gate electrode 37 is sufficient to generate a DL current flowing into the sense amplifier sA. G I DL current image to be read. In this case arising

0503-6153TW; TSMC2000-0969; Vincent.ptd Page 12 487975 V. Description of the invention (ίο) G &I; DL current will have an exponential relationship with the electric field on the surface of the doped region 36, and also the potential of the gate 37 Into an exponential relationship, the functional formula is:

LidfAx Esexp (-b / Es), where Es two (Vfg-Vref) / 3T0X In the above function formula, igidi is the current flowing into SA iGIDL, & is the electric field on the surface of the doped region 36, A, B are constant coefficients, τ〇χ is the thickness of the oxide layer between the floating gate 37 and the doped region 36. In particular, in the above-mentioned CMOS active pixel device and its manufacturing method, all type dopings are replaced with p-type doping and p-type doping at the same time.

The same effect can be produced when the impurity is replaced with N-type doping, which is not described here. In summary, the CMOS active pixel device of the present invention uses the gIDI current to sense an image and has an exponentiai response to the photometric characteristics. In addition, since it has only two diodes for output and light sensing, its area is smaller than that of a conventional CMOS active pixel using three transistors. Therefore, the present invention not only maintains the advantages of light saturation and light delay in the traditional medium, but also has a smaller surface suitable for detecting, photographing, and tracking dynamic objects in strong light or low light. Brother The present invention has been defined by a better practice. Anyone who is familiar with this technique and scope can make a few changes. The scope of the attached patent application is disclosed as examples, but it is not intended to be used. The spirit and retouching of the present invention are defined by the protection of the present invention.

Claims (1)

A. The scope of patent application for active complementary metal-oxide-semiconductor pixels includes: a soil bottom, a well area, and a doped area located on the well area. It is separated from the B well region, the first and the first-doped regions, and the first and the first-doped regions; erAr ~, ^ 7 out of the substrate surface M ^ the first-doped region is separated from each other, where the well 14 And =-and the second doped region has a second pole with a -th-pole plane, the gate layer is provided in the well region and the second doped region is first on the substrate surface; The well region and the second doped region are insulated to be in electrical contact with the impurity region; and a control gate layer is provided above the floating gate layer and is insulated from the floating gate layer. + 2 · The device according to item 1 of the scope of patent application, further comprising a cover, a metal compound layer of the control gate layer, and the metal compound layer covering the control gate above the first doped region Floor. The metallization, the metallization, the floating gate, the control gate, and the floating gate 3. The seismic compound layer as described in item 2 of the patent application scope also covers the second doped region. 4. The device described in item 2 of the scope of the patent application is a tungsten silicide layer. 5 · The attack layer as described in item 1 of the scope of patent application is doped with the ion of the first polarity. 6 · As described in the device described in item 1 of the scope of the patent application. The device pole is doped with the ion of the second polarity. 7 · As the first layer of the patent scope is provided with a first insulation layer between the electrode layer and the substrate. 'Isolate the floating gate layer from the well area and the second doping area. 0503-6153TW; TSMC2000-0969; Vincent.ptd Scope of patent application 8. The device according to item 7 of the scope of patent application, wherein the first insulating layer is a silicon oxide layer. 9. The device according to item 丨 in the scope of the patent application, wherein a second insulating layer is provided between the control gate layer and the floating gate layer, so that the control gate layer and the floating gate layer insulation. 10 The device according to item 9 of the scope of the patent application, wherein the second insulating layer is an oxide; the ε evening layer. 1 1 The device according to item 1 of the patent application scope, further comprising a first conductive layer in electrical contact with the second doped region. 12 The device according to item η of the patent application, wherein the first conductive layer is in electrical contact with the second doped region through a first contact hole in contact with the second doped region. 13. The device according to item 2 of the patent application scope, further comprising a second conductive layer in electrical contact with the metal compound layer. 14. The device according to item 3 of the scope of patent application, wherein the second conductive layer is in electrical contact with the delta metal compound layer through a second contact hole in contact with the metal compound layer. 15 · The device according to item 1 of the scope of patent application, wherein the substrate is a silicon substrate. 16 · The device according to item 1 of the scope of the patent application, wherein the first polarity is an n-type and the second polarity is a p-type. 1 7 The device according to item 1 of the scope of patent application, wherein the first polarity is of the p-type and the second polarity is of the n-type. 1 8 · The device according to item 1 of the scope of patent application, wherein the floating gate 0503-6153TW; TSMC2000-0969; Vincent.ptd Page 15 487975 6. Scope of patent application The electrode layer and the control gate layer are polycrystalline fragments. 19. An active complementary metal-oxide-semiconductor pixel device, comprising: a plurality of pixel devices forming a matrix having a plurality of rows and columns, each pixel device comprising: a substrate having a well area and one of the well areas located in the well area; A first and second doped region, the well region, the first and second doped regions all expose the substrate surface and the first and second doped regions are separated from each other, wherein the well region has a first polarity and the first And the second doped region has a second polarity; a floating gate layer is provided above the interface between the well region and the second doped region on the surface of the substrate, and is in contact with the well region and the second doped region; Insulated and in electrical contact with the first doped region; and a control gate layer disposed above the floating gate layer and insulated from the floating gate layer; wherein the pixel devices in each column are in contact with The pixel devices in adjacent columns are insulated and isolated, and the control gate layers of the pixel devices in each column are connected to move across the first doped regions and are insulated from the first doped regions. 2 0. A method for manufacturing an active complementary metal-oxide semiconductor pixel includes the following steps: providing a substrate; forming a well region having a first polarity in the substrate; depositing a first insulating layer; etching the first An insulating layer and using the first insulating layer as a cover; a first and a second doping which are separated from each other and have a second polarity are formed in the substrate; 0503-6153TW; TSMC2000-0969; Vincent.ptd page 16 deposits a first conductive layer; the first insulating layer and the first conductive layer are etched to form a floating gate; the floating gate is located there The well region and the second doped region are above an interface of the substrate surface and are in electrical contact with the first doped region; a second insulating layer and a second conductive layer are formed; The layer and the second conductive electrode are left for a while to form a control gate, which is located above the floating gate. 21. The method according to item 20 of the patent application park, further comprising: doping the first conductive layer with an ion having the first polarity. 2 2. The method as described in claim 20 of the scope of patent application, wherein the second conductive layer is further doped with ions having the second polarity. 23. The method described in item 20 of the patent application, which further includes depositing a second compound layer after depositing the second insulating layer and the second conductive layer, and depositing the second metallization layer. , Preventing the metal compound from being deposited over the first doped region. 24. The method according to item 23 of the scope of patent application, wherein the method further comprises depositing the metal compound layer over the second doped region. A method, wherein the metal includes:-々 quot ϋ ϋ r 贝 2 5 · The compound layer is a tungsten silicide layer as described in item 23 of the patent application scope. 0503-6153TW1; TSMC2000-0969; Vincent 17th tribute 487975 6. Scope of patent application 2 6. The method described in item 20 of the scope of patent application, wherein the substrate is a chopped substrate. 27. The method of claim 20, wherein the first polarity is n-type and the second polarity is p-type. 2 8. The method according to item 20 of the scope of patent application, wherein the first polarity is a p-type and the second polarity is an n-type. 2 9. The method as described in item 20 of the scope of patent application, wherein the first, second and third insulating layers are oxide second layers. 30. The method according to item 20 of the scope of the patent application, wherein the first and second conductive layers are polycrystalline silicon layers. _ 3 1. The method according to item 20 of the patent application scope, further comprising: depositing a third insulating layer and forming a first contact hole in the third insulating layer which exposes one of the second doped regions And depositing a third conductive layer to fill the first contact hole. 3 2. The method according to item 23 of the patent application scope, further comprising: depositing a fourth insulating layer and forming a second contact hole in the fourth insulating layer exposing one of the metal compound layers; and depositing a A fourth conductive layer fills the second contact hole. _ 0503-6153TW; TSMC2000-0969; Vincent.ptd page 18