TW486781B - A method to improve DRAM contact etch aspect ratio - Google Patents

Abstract

A new method of improving the contact etch aspect ratio without using a nitride stop layer is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with a first oxide layer. A photoresist mask is formed overlying the first oxide layer. The first oxide layer not covered by the photoresist mask is partially etched into to form a partial contact opening having a first width. A second oxide layer is deposited overlying the photoresist mask and within the partial contact opening. The second oxide layer is anisotropically etched back to leave oxide spacers within the partial contact opening wherein the partial contact opening not covered by the oxide spacers has a second width smaller than the first width. A contact opening is etched through the portion of the partial contact opening in the first oxide layer not covered by the oxide spacers to the semiconductor substrate whereby the photoresist mask protects the first oxide layer from damage during etching and wherein the contact opening has the second width. Thereafter, the photoresist mask is removed. A metal layer is deposited within the contact opening to complete the contact in the fabrication of an integrated circuit device.

Description

486781 V. Description of the invention (1) (1) The field of invention is related to the manufacture of integrated circuit components, and more specifically methods. ; A method to improve the aspect ratio of the contact window in the manufacture of integrated circuits (2) Description of the known art ΜΑΜί Ϊ: In the manufacture of circuits' especially dynamic random access memory (, sometimes it must form a The micron feature size and the depth / height of the deep contact window of M; that is, a contact window opening, where the width of the ratio ^ is greater than 1 in many places 'for example' 0. m is 4, and the size of the mound is wide. · 26 # m and depth 1 # m, with a depth-to-width ratio, f is composed of two parts. First, the width of the small contact window must be set at second and second, and the trench with large depth-to-width ratio must be etched. (SAC) In the art, a self-aligned contact window with an oxidation partition is used for the oxidation window II: 1. The contact window and the aspect ratio are interrogated. This method is a ratio of width to width. In addition, soil can reduce contact The window width, however, is increased by this limit. This SAC process involves the use of an additional silicon nitride barrier layer due to the nitrogen I::? Making a small contact W with a high depth-to-width ratio. f /, high residual selectivity between emulsions, however, this system is more complicated Because of the need for different polycrystalline silicon, and for a hammer stone I, shop / /. Mugang Hung to stratum is located at Xi Yue 1 contact ® to a source / drain, due to silicon nitride ^ 彳Yu Xiri said on Shi Xi, but not on the source / drain, a second series needs to be used for the contact window to a source / drain. Some patents have tried to solve the problem of small contact window / high aspect ratio. 5, 444, 02 1 (Chung et al.) Teaches part of contact window etching, 486781

The formation of the barrier ribs and the etching of the contact window when the oxide is not covered by the barrier ribs. U.S. Patent No. 5,7 119,0 8 9 (fhe: 弋) discloses a polymer shape on the partition wall of the opening of the contact window. 29. The period of time during which the contact window is narrowed. U.S. Patent No. 5, 31 Γ !: m) discloses forming a gap wall in a contact window opening, so that U.S. Patent No. 5,677,242 (Ais〇u) discloses forming a photoresist cover curtain: flat contact window @ 'Then deposit an oxide layer to cover the etched mask opening of the smaller contact window. US Patent No. 5,580,811 discloses another sac process. Summary of the invention:

It is to provide an efficient and integrated circuit manufacturing improvement. Therefore, a main object of the present invention and a very manufacturable method is to etch the aspect ratio of the contact window. Zhao-Li t: Another objective is to provide a process for improving the contact window erosion rate without using a nitride barrier layer. Root = The purpose of the present invention is to obtain a method for improving the etching aspect ratio of a contact window without using a silicon nitride barrier layer. The semiconductor element structure is provided in and on the semiconductor substrate and is covered with a first oxide. Floor

The light-shielding system is formed to cover the first oxide layer, and the vaporization layer that is not covered by the light-resistance cover is partially engraved to form a first width = local contact window opening π, a first The second oxide layer is deposited and covered in the photoresist and is in the local contact window opening. The second oxide layer is anisotropically etched to leave an oxidized interstitial wall in the local contact window opening. The wall-covered partial contact window opening has a width smaller than the second width

5. The second width of the description of the invention (3) j The part of the opening system of the contact window j is damaged during the engraving of the semiconductor substrate 5 which is not oxidized by the photoresist mask 5 and the contact, light The mask screen is removed with a metal to complete the brief description of the drawing number in the fabrication of integrated circuits: 10 semiconductor substrate 12 field oxidation 14 source and drain regions 16 polycrystalline silicon gate electrode 20 inner dielectric layer 24 light Mask screen 26 Opening 30 Silicon oxide layer 32 Spacer wall 36 Metal layer 38 Description of a preferred embodiment of a passivation protective layer • The process of the present invention provides a deep-to-width ratio contact with the contact window system having an improved aspect ratio. Window 5 In the present invention, it is particularly expected to form an etching having two simple shapes; the aspect ratio of the process should be 4 or greater, and a depth and width greater than 5 The engraved protective layer of the first window opening is partially connected by the contact window to the first oxide layer oxide layer to have a second wide deposit on the contact window opening to prevent corrosion, and then a contact is formed in the window opening. The window is a method that can be used in a ratio of contact and reasonable light. It has a higher window opening for any application, resistance to etching 486781. V. Obtained from the invention (4), the invention will be particularly beneficial. It has an aspect ratio of 4 or more for manufacturing DRAMs. τ 8. Now refer to FIG. 1 'shows a semiconductor substrate 10, forming a semiconductor element structure, which may include a polycrystalline interstitial electrode 16 and a source and drain region 14, the active region may be a field oxidation region 12 It is separated, and the inner dielectric layer 20 is completely deposited and covered on the semiconductor device structure. This layer includes silicon dioxide, borophospho-tetrachloroethyl silicon (Bp — TE0s), and borophosphosilicate glass (BPSG). , Phosphosilicate glass (PSG), or a combination of BPSG and silicon dioxide, etc., and may be one or more layers. The total thickness of the inner dielectric layer 20 is about one micrometer; that is, between about 8000 and 10,000 angstroms or more, the top of the inner dielectric layer 20 may be planarized, For example, by reflow of a dielectric material, etch back or chemical mechanical polishing (CMP), or the like. 〆 A layer of photoresist is coated on polycrystalline silicon. The photoresist layer is exposed, deposited, and patterned to form a photoresist mask 24, and defines a contact window opening such as opening 26. As shown in Figure 2, the dielectric layer 20 is partially etched to a place not covered by the mask 24, and the dielectric layer is etched to a depth A between 1000 and Angstroms. In the art, typically a thicker dielectric layer system of about 2 micrometers is used, and the local etching system is deeper than that of the present invention (about 50,000 to 10,000 Angstroms). Shallow etch allows high controllability of key pattern sizes. In the present invention, a patterned photoresist will stay on the dielectric layer, ^ unexposed area during the etching of the etch stop layer, and thus increase the aspect ratio ' Residency also allows for a thinner dielectric layer (about 1 micron), compared to 2 micron for conventional techniques. ) Relative to

486781 V. Description of the invention (5) Now refer to Fig. 3 'The oxide oxide layer 30 is fully deposited and covered on the photoresist mask 24 and the opening of the local contact window, which is a low-temperature oxidative deposition' Yu Zai For temperatures between 150 and 200 ° C, low temperature systems are needed so that the bottom photoresist will not be sintered. This step is similar to a three-layer photoresist process. It is deposited on two layers in a low temperature oxidation system. Photoresist, although the purpose is different. Here, the controllability of the etching is required, and the oxide layer 30 is deposited to achieve a thickness between about 100 and 100 angstroms. Referring now to FIG. 4, the oxide layer 30 is anisotropically etched away to leave the gap wall 32 in the partial contact window opening. The final contact window width b, or key pattern dimension (CD), is formed by the gap wall. By definition, CD can be as small as 0 · 10 to 0 · 30 microns. Then, as shown in FIG. 5, the inner dielectric layer 20 is completely etched through to the bottom semiconductor element structure to be connected, such as the source and drain regions of the semiconductor structure 14 and the spacer 3 2 Is etched locally, but stays enough to allow a narrow contact window opening with a narrow width B to be etched through to the substrate 'at the contact f-etching time' photoresist layer 24 stays on the inner dielectric layer 20 so that = Etching period 2 Protects the oxide layer, which is expected to become thinner in the conventional manufacturing process. Where the oxide layer can be etched and after the window is etched, the photoresist mask 24 is removed, ΠΐΓ or wet type, as shown in FIG. 6. ϋ ^ S is used to fill the opening of the contact window. For example, a metal layer [6 series is deposited in the opening of the contact window. The metal layer 36 may include the right side. Covered with a picture of aluminum or A1SiCu

Page 10 486781 V. Description of the invention (6) The tungsten plug of the case layer, the passive protective layer 38 covers a patterned metal layer. The process of the present invention improves the aspect ratio of the contact window in the manufacture of integrated circuits, which is particularly important for the manufacture of DRAM devices, and has a contact window aspect ratio of 4 or greater. Although the present invention has been particularly shown and described with reference to its preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Under category

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Claims (1)

486781 VI. Application Patent Scope 1 · A method for forming a contact window in the manufacture of integrated circuits, comprising: providing a semiconductor element structure in and on a semiconductor substrate; covering a dielectric layer on the semiconductor element structure Forming a photoresist mask covering the dielectric layer; partially touching the dielectric layer not covered by the photoresist mask to form a local contact window, wherein the local contact window has a first A wide-deposited oxide layer covers the photoresist mask and the local contact window; the opposite layer is engraved with the oxide layer to leave an oxidizing spacer in the local contact window, which is not the oxidizing spacer The covered partial contact window has a second width that is smaller than the first width. 1 A portion of a contact window opening that passes through the partial contact window opening is formed in the dielectric not covered by the gasification gap. Layer to reach the semiconductor substrate, to protect the dielectric by the photoresist mask to prevent damage during the remaining period, and wherein the contact window opening has the second width; and In addition to the photoresist mask; the contact hole and depositing a metal layer in the contact holes to complete the integrated circuit made in $. The method according to item 1 of the patent application scope, wherein the semiconductor device structure includes a gate electrode, a source electrode, and a drain electrode region. The method as described in item 1 of the scope of patent application, wherein the dielectric layer package Page 13 486781 6. The scope of patent application includes one or more groups containing silicon dioxide, borophospho-tetrakis-ethylsilicon, borophosphosilicate glass, and phosphosilicate glass. 4. The method according to item 1 of the scope of the patent application, wherein the dielectric layer has a thickness between about 100 and 100,000. 5. The method according to item 1 of the scope of the patent application, wherein the step of locally etching the dielectric layer is completed to a depth of between about 100 and 500 angstroms. 6. The method according to item 1 of the scope of patent application, wherein the first width is 0.2 to 0.4 micron. 7. The method according to item 1 of the scope of patent application, wherein the oxide layer is deposited at a temperature of about 150 to 200 ° C to achieve a temperature of about 100 to 100 Angstrom thickness. 8. The method according to item 1 of the scope of patent application, wherein the second width is from 0.10 to 0.30 microns. 9. The method as described in item 1 of the scope of patent application, wherein the opening of the contact window has an aspect ratio greater than 1. 10 The method as described in item 1 of the scope of patent application, wherein the opening of the contact window has an aspect ratio greater than 4. 11. A method for forming a contact window in the manufacture of integrated circuits, comprising: providing a semiconductor element structure in and on a semiconductor substrate; covering a first oxide layer on the semiconductor element structure; forming a photoresist The mask is covered on the first oxide layer; the first oxide layer that is not covered by the photoresist mask is partially carved into, Page 14 486781 6. Apply for a patent to reach a depth, which is a depth between 1/5 and 1/2 of the first oxide layer to form a local contact window, wherein the local contact window has a first Width; depositing a second oxide layer to cover the photoresist mask and the local contact window; Anisotropically etch back the second oxide layer to leave an oxidation spacer in the local contact window, wherein the local contact window not covered by the oxidation spacer has a second width smaller than the first width; A portion of a contact window opening passing through the partial contact window opening is etched to reach the semiconductor substrate in the first oxide layer that is not covered by the oxidation gap wall, thereby protecting the first oxide layer by the photoresist mask. To prevent damage during the etching, and wherein the contact window opening has the second width; thereafter, removing the photoresist mask; and depositing a metal layer in the contact window opening to complete the integration. The contact window in circuit manufacturing. 1 2. The method according to item 11 of the scope of patent application, wherein the semiconductor device structure includes a gate electrode, a source electrode and a drain electrode region. 1 3. The method according to item 11 of the scope of patent application, wherein the first oxide layer has a thickness between about 100 and 500 angstroms. 1 4. The method according to item 11 of the scope of patent application, wherein the first width is from 0.20 to 0.40 angstroms. 15 · The method according to item 11 of the scope of patent application, wherein the second oxide layer is deposited at a temperature of about 150 to 200 ° C to achieve a Page 15 486781 6. The thickness of the patent application ranges from about 100 to 100 angstroms. 16 · The method according to item 11 of the scope of patent application, wherein the first series is 0 · 10 to 0 · 30 angstroms. Ren Yiliang 1 7 · According to the method described in item 11 of the scope of patent application, the middle contact is not complicated *, and the contact window opening has an aspect ratio greater than 1. 18. The method according to item 11 of the scope of patent application, wherein the contact window has an aspect ratio greater than 4. $ 19 · A method for forming a contact window in the manufacture of integrated circuits, including: Provide a semiconductor device structure in and on a semiconductor substrate, wherein the ancient semiconductor device structure includes a gate electrode, a source electrode and a drain electrode = covering a first oxide layer on the semiconductor device structure; forming a photoresist mask Covered on the first oxide layer; locally etched into the first oxide layer not covered by the photoresist mask to reach a depth, between i / 5 and i / 2 of the first oxide layer To form a local contact window, wherein the local contact window has a first width; a second oxide layer is deposited to cover the photoresist mask and in the local contact window; anisotropically etch back the A second oxide layer to leave an oxidized spacer in the local contact window of the 5H, wherein the local contact window not covered by the oxidized spacer has a second width smaller than the first width; The window opening passes through the part that touches the window opening, in Page 16 486781 6. The scope of the patent application is not in the first oxide layer that is not covered by the oxidation spacer to reach the semiconductor substrate. The photoresist mask is used to protect the first oxide layer to prevent the etching during the etching. Damaged, and wherein the contact window opening has the second width, and wherein the contact window opening has an aspect ratio greater than 4; thereafter, removing the photoresist mask; and depositing a metal layer on the contact window opening To complete the contact window in the fabrication of the integrated circuit. 2 0. The method according to item 19 of the scope of patent application, wherein the first oxide layer has a thickness between about 100 and 500 angstroms. 2 1 · The method as described in item 19 of the scope of patent application, wherein the first width is 0.20 to 0.40 angstroms. 2 2 · The method as described in item 19 of the scope of patent application, wherein the second oxide layer is deposited at a temperature between about 150 to 200 ° C to achieve a temperature between about 100 to 1 0 0 0 Angstrom thickness. 2 3 · The method as described in item 19 of the scope of patent application, wherein the second width is from 0.10 to 0.30 angstroms. Page 17