486619 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（1 ) 本發明通常與內藏電腦系統.有關，且尤其是與一種具 雙監視計時器之內藏電腦系統及方法有關。 美國專利5 7 4 2 8 4 4發表一種內藏電腦模組，包 裝成一積體電路大小，其具一桌上型電腦功能。這模組包 含一英特爾（INTEL ) X 8 6處理器，串列與並列介面， 驅動控制器，一鍵盤介面，一 D R A Μ介面與快閃記憶體 〇 一更最近所開發之系統在一單晶片上包含一完整處理 器與周邊子系統，並具僅有之外部組件爲一時鐘， S D R A Μ與一含系統啓動碼（Β I 0 S )及/或應用程 式之一快閃記憶體。 這種系統一向包含一監視計時器，該監視計時器檢查 系統作業中之問題並在錯誤狀況時產生一訊號。計時器朝 零倒數且如系統運作適當時則週期性地重置至一預定位階 。如發生一問題時未重置計時器，且當計數到零時，計時 器即遞送一可用以啓始動作加以恢復系統之輸出訊號。以 一傳統之監視計時器，只有一輸出訊號及一次機會加以恢 復系統。 通常本發明之一項目的在提供用於一內藏電腦系統之 一種新式與改良式之監視計時器及方法。 本發明另一項目的在提供具以上特徵之一種監視計時 器及方法，其克服迄今所提供之監視計時器之不利之處。 根據本發明提供一種雙監視計時器與方法可達成這些 及其它目的，在該方法中，使第一計時器從一初値朝一終 --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- 經濟部智慧財產局員工消費合作社印製 486619 A7 B7 五、發明說明（2 ) 値前進，且如果達到終値時則遞送第一恢復訊號。如果系 統運作適當，則將第一計時器週期性地重置至初値，故將 不會遞送第一恢復訊號。使一第二計數器回應第一恢復訊 號，從一初値朝一第二値前進，且如達到第二値時，即遞 送一第二恢復訊號。如果在達到第二計數前恢復系統之適 當作業，則第二計數器將不會達到第二値而遞送第二恢復 訊號。利用恢復訊號作爲一軟體中斷及/或作爲一硬體重 置訊號。 第1圖爲一具有結合本發明一監視計時器之一內藏電 腦系統實施例之方塊圖。 第2圖爲第1圖實施例中監視計時器之方塊圖。 元件對照表 1 0 :單晶片 11:處理器核心 1 2，1 3 :橋接控制器 1 4 :邏輯模組 16;唯讀記憶體 17:快閃記憶體裝置 2 1，2 3 :計數器 2 2 :反多工器 第1圖中所說明之內藏電腦系統是構築在包裝爲3 5 m m，3 8 8接腳球網陣列（未示出）之單晶片1 〇上。 系統包含一處理器核心1 1 ，該處理器核心在一實施例中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5- --------訂---------線 (請先閱讀背面之注意事項再填寫本頁)486619 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the Invention (1) The present invention is generally related to a built-in computer system, and in particular to a built-in computer system and method with dual watch timers. U.S. Patent No. 5 7 4 2 8 4 4 discloses a built-in computer module packaged in the size of an integrated circuit, which has the function of a desktop computer. This module includes an Intel (INTEL) X 8 6 processor, a serial and parallel interface, a drive controller, a keyboard interface, a DRA M interface and flash memory. A more recently developed system is on a single chip. It includes a complete processor and peripheral subsystems, and has the only external components as a clock, SDRA M and a flash memory containing system startup code (B I 0 S) and / or applications. Such systems have always included a watchdog timer which checks for problems in system operation and generates a signal in the event of an error condition. The timer counts down to zero and periodically resets to a predetermined level if the system is operating properly. If a timer is not reset when a problem occurs, and when the count reaches zero, the timer will deliver an output signal that can be used to initiate actions to restore the system. With a traditional watchdog timer, there is only one output signal and one chance to restore the system. Generally, one of the items of the present invention is to provide a new and improved monitoring timer and method for a built-in computer system. Another aspect of the present invention is to provide a monitoring timer and method with the above features, which overcome the disadvantages of the monitoring timers provided so far. These and other objects can be achieved by providing a dual-monitoring timer and method in accordance with the present invention, in which the first timer is made from the beginning to the end -------- ordering -------- -Line (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -4- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 486619 A7 B7 V. Description of the invention (2) 値 forward, and if the end time is reached, the first recovery signal is delivered. If the system works properly, the first timer is reset to the initial state periodically, so the first recovery signal will not be delivered. A second counter is made to respond to the first recovery signal, and it advances from an initial frame to a second frame, and if it reaches the second frame, it sends a second recovery signal. If the proper operation of the recovery system is reached before the second count is reached, the second counter will not reach the second frame and a second recovery signal will be delivered. Use the resume signal as a software interrupt and / or as a hard reset signal. Figure 1 is a block diagram of an embodiment of a built-in computer system incorporating a watchdog timer of the present invention. Fig. 2 is a block diagram of the watchdog timer in the embodiment of Fig. 1. Component comparison table 1 0: single chip 11: processor core 1 2, 1 3: bridge controller 1 4: logic module 16; read-only memory 17: flash memory device 2 1, 2 3: counter 2 2 : The built-in computer system illustrated in the first figure of the inverse multiplexer is constructed on a single chip 10 packaged in a 35 mm, 3 8 8 pin ball net array (not shown). The system includes a processor core 1 1. In one embodiment, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). -5 --------- Order- -------- Line (Please read the notes on the back before filling this page)
486619 五、發明說明（3 ) 包含一具有一積體浮點輔助處理.器與8 K位元組之四寫式 桌1階快取之標準X 8 6處理器（如英特爾3 8 6 )。 這系統亦包含一具有一前面P C I介面與一 S D R A Μ介面之北橋接系統控制器丨2 ，及一具有一連 接至北橋接控制器之前面P C I介面與一背面p c丨系統 介面之南橋接控制器1 3。南橋接控制器亦具一在一單通 道上支援兩裝置之加強式I C E控制器，一具有兩集線器 太阜之U S B控制器，一即時時鐘，一軟碟機控制器，串歹 ί阜’ 一存取匯流排，一鍵盤與滑鼠控制器，一並列淳，通 用式可程式化I /〇及計數器，P C / Α 丁系統組件，與 電源管理。P C / A T系統組件包含D Μ A控制器，中斷 控制器，一系統計時器，及一 I S A匯流排介面。 邏輯模組1 4在內部連接至I S A匯流排並在單晶片 上使用外部墊加以控制外接裝置。這模組含通用與特定晶 片選取，一監視計時器，及一快閃控制器。 晶片上之BIOS更新ROM (BUR) 16包含要 將資料讀進晶片並更新一外接快閃記憶體裝置1 7之最小 必要碼。晶片與快閃記憶體裝置間之連結可經由一串列埠 或藉多工處理軟碟機與快閃記憶體裝置間之軟碟機介面加 以完成。串列連結利用一內嵌在晶片內之標準U A R T 1 ，並允許具特殊主機軟體或存取快閃裝置之遠程p C實施 更新。這種方法只能使用在串列埠非以永久性電氣連接至 一外部裝置與存取串列埠實際上爲可能之申請案。快閃記 憶體所使用之軟碟機介面詳細公開在同一日期所申請之序 --------訂---------線-1^· C請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印制π 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -6 - 486619 A7 __ ______ B7 五、發明說明（4 ) 號_。 (請先閱讀背面之注意事項再填寫本頁) 如第2圖中之說明，監視計時器包含一從一預置値倒 數並當計數到零時遞送一輸出訊號之第一計數器2 1。當 系統正常運作時，計數器週期性地收到一重置計數器至預 置値之輸入訊號W b I並由此防止產生輸出訊號。將輸出 訊號施加至一反多工器2 2並利用它作爲一軟體中斷（如 ，NMI ，SCI或SMI)或作爲一硬體RESET訊 號。 來自第一計數器之輸出訊號亦被施加至一第二計數器 2 3之E NAB L E輸入。這計數器自其本身之預置値倒 數且當數到零時即遞送一輸出訊號。如果在計數器2 3中 之計數達到零前即修正使輸出訊號由計數器2 1產生之問 題’則計數器2 1將被重置至預置値，並將使計數器2 3 失能而不會遞送其輸出訊號。 雖然計數器2 1最好爲一較大之計數器並被預置至一 高於計數器2 3之計數，兩計數中之計數回應系統所供應 之時鐘訊號以相同速率遞減。例如在一本實施例中，以 經濟部智慧財產局員工消費合作社印製 3 2 Κ Η z之速率供應時鐘脈衝，計數器2 1爲一 1 6 k 元暫存器，且計數器2 3爲一 8位元暫存器。在這實施例 中，計數器2 1具一爲6 4秒之最大週期，而計數器2 3 具一爲2 9毫秒之最大週期。 設定計數器21逾時之暫存器（WD1)之構造如下 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486619 A7 B7 五、發明說明（5 ) f 立 %__ . . _ . 名稱 15-〇 .............. wdc 11 WD1計數器値 說明 設定計數器2 3逾時之暫存器（WD 2 )之構造如下 經濟部智慧財產局員工消費合作社印製 if? it -------------- ——-------—" 名稱 說明 IJLjL / ^_________ 7-0 wdc t2 WD2計數器値 ㉗IS目計時器之控制暫存器構造如下： --- 位元 名稱 說明 7 wdl NMI WD1產生NMI 6 wdl SCI WD1產生SCI 5 wdl SMI WD1產生SMI 4 wd 1 RES WD1產生RES 3 wdl En WD1有效 2 wd2 En WD2有效 1 wdl Ext WD1 Ext負載有效 0 wdl Exp WD1負載訊號極性 位元7 - 4選取當計數器2 1達到零時所採取之動作 。位元3或2使計數監視器有效。位元1使外部負載訊號 有效，且位元0選取外部負載訊號極性。 控制兩計數器從其計數暫存器載入之暫存器構造如下 --------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） -8- 486619 A7 B7 經濟部智慧財產局員工消費合作社印制农 五、發明說明（6 ) 位元 名稱 說明 7-2 保留 1 w d 1 LD WD1計數器重載 2 wd2 LD WD2計數器重載 狀態位元將監視計時器之歷史保存在構造如下之一暫 存器中： 位元 名稱 說明 7 wdl GNMI WD1產生NMI 6 wdl GSCI WD1產生SCI 5 wdl GSMI WD1產生SMI 4 wdl GRES WD1產生RES 3 wd2 GRES WD2產生RES 2 wdl Ext WD1外部負載腳位 狀態暫存器未被POWER — ON — RESET ( D〇R )訊號重置，但可藉寫入任何値至暫存器加以重置 位元。 雙監視計時器之運作與使用及本發明之方法如下。計 數器2 1回應所施加給它之時鐘訊號而連續倒數，且在系 統之正常運作中，在計數器達到零之前，它會週期性地加 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -9- 衣--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 486619 五、發明說明（ 以重置。在出問題時未重置計數器2 1 ，並當計數達到零 時，它產生一可被當作軟體中斷或硬體重置之輸出訊號。 來自計數器之輸出訊號亦啓動計數器2 3 ，自其預置 値朝零倒數。如計數達到零，計數器2 3亦產生一作爲硬 體重置用之輸出訊號，硬體重置應總是可恢復系統。如果 在計數達到零前即修正問題，即重置計數器2 1並使計數 器2 3失能，故未產生第二輸出訊號。 本發明具許多重要特性與優勢。它檢查使系統變得無 法控制之可能硬體故障及程式毛病並產生訊號，啓始修正 動作。以兩計數器或計時器，這可產生兩輸出訊號，在軟 體無法修正問題時，可使用其中之一輸出訊號作爲一軟體 中斷，並使用另一訊號爲一硬體重置。 明顯地從前述中已經提供一種新式與改良式之監視計 時器與方法。雖然已經詳述某些目前之優選實施例，對於 那些熟悉技術者，只要不偏離如以下申請專利項目所定義 之本發明範圍，皆可做某些變更與修飾。 請 先 閱 讀 背 s 意 事 項 再 填 寫 本 頁 I I I I 訂 線 經濟部智慧財產局員工消費合作社印製486619 V. Description of the invention (3) Contains a standard X 8 6 processor (such as Intel 3 8 6) with a quadruple writing table with an integrated floating-point auxiliary processor and 8 K bytes. This system also includes a north bridge system controller with a front PCI interface and an SDRA M interface, and a south bridge controller with a front PCI interface and a back pc system interface connected to the north bridge controller. 1 3. The South Bridge controller also has an enhanced ICE controller that supports two devices on a single channel, a USB controller with two hubs, a real-time clock, a floppy disk drive controller, and a string of 歹 fu ' Access bus, a keyboard and mouse controller, side by side, universal programmable I / O and counter, PC / Α system components, and power management. The PC / AT system components include a D M A controller, an interrupt controller, a system timer, and an I S A bus interface. The logic module 14 is internally connected to the ISA bus and uses external pads on a single chip to control external devices. This module contains general and specific chip selection, a watchdog timer, and a flash controller. The BIOS update ROM (BUR) 16 on the chip contains the minimum necessary code to read data into the chip and update an external flash memory device 17. The connection between the chip and the flash memory device can be completed through a serial port or by multiplexing the floppy disk drive interface between the floppy disk drive and the flash memory device. The serial link utilizes a standard U A R T 1 embedded in the chip and allows remote PC implementations with special host software or access to flash devices to implement updates. This method can only be used in applications where the serial port is not permanently electrically connected to an external device and access to the serial port is actually possible. The interface of the floppy disk drive used by the flash memory is disclosed in detail on the same date. The order applied -------- Order --------- line-1 ^ · C Please read the note on the back first Please fill in this page again} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs π This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -6-486619 A7 __ ______ B7 V. Description of the invention (4 ) number_. (Please read the precautions on the back before filling this page.) As shown in Figure 2, the watchdog timer includes a first counter 21 which counts down from a preset value and delivers an output signal when the count reaches zero. When the system is operating normally, the counter periodically receives an input signal W b I that resets the counter to a preset value and thereby prevents an output signal from being generated. Apply the output signal to an inverse multiplexer 22 and use it as a software interrupt (eg, NMI, SCI or SMI) or as a hardware RESET signal. The output signal from the first counter is also applied to the E NAB L E input of a second counter 2 3. This counter counts down from its own preset and delivers an output signal when it reaches zero. If the problem caused by the output signal from the counter 2 1 is corrected before the count in the counter 2 3 reaches zero, the counter 2 1 will be reset to the preset value, and the counter 2 3 will be disabled without delivering it. Output signal. Although the counter 21 is preferably a larger counter and is preset to a count higher than the counter 23, the count of the two counts decreases in response to the clock signal supplied by the system at the same rate. For example, in this embodiment, a clock pulse is supplied at a rate of 3 2 Η Η z printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The counter 2 1 is a 16 k yuan register, and the counter 2 3 is 8 Bit register. In this embodiment, the counter 21 has a maximum period of 64 seconds, and the counter 23 has a maximum period of 29 ms. The structure of the time-out register (WD1) for setting the counter 21 is as follows. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 486619 A7 B7 V. Description of the invention (5) f Li% __. _. Name 15-〇 .............. wdc 11 WD1 counter 値 Description Set the counter 2 3 Timeout register (WD 2) The structure is as follows Printed by the consumer cooperative if? It -------------- ——--------- " Name Description IJLjL / ^ _________ 7-0 wdc t2 WD2 counter 値 ㉗ IS eye timing The structure of the control register is as follows: --- Bit name description 7 wdl NMI WD1 generates NMI 6 wdl SCI WD1 generates SCI 5 wdl SMI WD1 generates SMI 4 wd 1 RES WD1 generates RES 3 wdl En WD1 is valid 2 wd2 En WD2 Valid 1 wdl Ext WD1 Ext load valid 0 wdl Exp WD1 load signal polarity bits 7-4 Select the action to be taken when counter 2 1 reaches zero. Bit 3 or 2 enables the count monitor. Bit 1 enables the external load signal, and bit 0 selects the polarity of the external load signal. The register that controls the loading of the two counters from their counting register is structured as follows: -------- Order --------- line (please read the precautions on the back before filling this page) Paper size applies Chinese National Standard (CNS) A4 specification (210 χ 297 mm) -8-486619 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Agricultural description (6) Bit name description 7-2 Reserved 1 wd 1 LD WD1 counter reload 2 wd2 LD WD2 counter reload status bit saves the history of the watchdog timer in one of the following structures: Bit name description 7 wdl GNMI WD1 generated NMI 6 wdl GSCI WD1 generated SCI 5 wdl GSMI WD1 generates SMI 4 wdl GRES WD1 generates RES 3 wd2 GRES WD2 generates RES 2 wdl Ext WD1 external load pin status register is not POWER — ON — RESET (D〇R) signal reset, but can be borrowed Write any bit to the register to reset the bit. The operation and use of the dual watchdog timer and the method of the present invention are as follows. Counter 2 1 counts down continuously in response to the clock signal applied to it, and in the normal operation of the system, before the counter reaches zero, it will periodically add the paper size to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -9- clothing -------- order --------- line (please read the precautions on the back before filling in this page) 486619 5. Description of the invention (to reset. The counter 2 1 is not reset when a problem occurs, and when the count reaches zero, it generates an output signal that can be used as a software interrupt or hardware reset. The output signal from the counter also activates the counter 2 3 from its preset. Count down towards zero. If the count reaches zero, the counter 2 3 also generates an output signal for hardware reset. The hardware reset should always restore the system. If the problem is corrected before the count reaches zero, the counter 2 is reset 1 and disable the counter 2 3, so the second output signal is not generated. The invention has many important features and advantages. It checks for possible hardware failures and program faults that make the system uncontrollable and generates signals to initiate corrective actions ... with two counters Timer, which can generate two output signals. When the software cannot fix the problem, one of the output signals can be used as a software interrupt, and the other signal can be used to reset the hardware. Obviously from the foregoing, a new type and Improved monitoring timer and method. Although some current preferred embodiments have been described in detail, for those skilled in the art, certain changes and modifications can be made as long as they do not depart from the scope of the present invention as defined by the following patent applications. Please read the notices before filling in this page. IIII Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives of Employees.
β 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -10-β This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -10-