TW484210B - Manufacturing method of oxide-nitride-oxide layer - Google Patents

Abstract

This invention provides a manufacturing method of oxide-nitride-oxide (ONO) layer. A first oxide layer is formed on a given substrate and a rapid thermal nitridation (RTN) process is performed to anneal the first oxide layer and simultaneously nitrify the surface of the first oxide layer. Subsequently, a low pressure chemical vapor deposition (LPCVD) process is carried out to form a silicon nitride layer onto the first oxide layer. Finally, a second oxide layer is formed on the nitride layer to create ONO layer from the second oxide layer, the nitride layer and the first oxide layer.

Description

484210 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing a 0N0 layer of a nitride read-only memory. Background Description A read only memory (ROM) device is a semiconductor device used to store data. It is composed of multiple memory cells (memory cei 1). Nowadays, it is widely used in data storage of computers and other products. And memory. According to the data storage method, the read-only memory can be divided into Qin curtain read-only memory (mask R 0 Μ), programmable ROM (programmable ROM, PROM), erasable and programmable ROM Erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPR0M), and several other types. Unlike other read-only memories that use polycrystalline silicon or metal floating gates to store charge, the main feature of nitride read-only memory (nitrideread ο η 1 ymemory, NR 0 M) is the use of an insulating dielectric layer of silicon nitride as the charge Storage medium (charge trapping medium). Due to the high density of the nitride stone layer, hot electrons tunneled into the silicon nitride layer through the MOS transistor can be trapped therein, thereby forming a non-uniform concentration distribution to speed up Read data speed

484210 V. Description of the invention (2) and avoid leakage current.凊 Refer to Figure 1. Figure 1 is a schematic diagram of the standard and quasi-structure of a conventional nitride read-only memory. The semiconductor wafer 10 includes a P-type silicon substrate 12, two N-type ion-doped regions 14, 16 are located on the surface of the silicon substrate 12, and a 0N0 dielectric composed of a bottom oxide layer 18, a silicon nitride layer 20, and an upper oxide layer 22. The electrical structure 24 is located on the surface of the silicon substrate 12, and a gate conductive layer 26 is disposed on the ON0 dielectric structure 24. Please refer to FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are schematic diagrams of the conventional method of nitride read-only memory using the standard structure of FIG. As shown in Figure 2, the conventional method for making nitride read-only memory gates is to first provide a semiconductor wafer 30 including a P-type silicon base 32, and then use a high temperature oxidation to An oxide layer of 50 to 150 angstroms (A) is formed on the surface of the Shixi substrate 32, and is used as a bottom oxide layer 34. A low-pressure chemical vapor deposition (LPCVD) process is subsequently performed to deposit a silicon nitride layer 3 6 having a thickness of 50 to 150 Å (A) on the surface of the bottom oxide layer 34. Finally, in a high temperature environment of 950 ton, a tempering process is performed for 30 minutes to repair the structure of the nitrided layer 36, and water vapor is passed in for wet oxidation to form a surface of the nitrided layer 36. A silicon oxy-nitride layer having a thickness of 50 to 150 angstroms (A) is used as the upper oxide layer 38. Among them, the bottom oxide layer 34, the nitride nitride layer 36, and the upper oxide layer 38 formed on the surface of the Shi Xi substrate 32 are collectively referred to as a 0 N 0 dielectric structure 40. Next, a yellow light process and an etching process are performed for the upper oxide layer 3 8

484210 V. Description of the invention (3) and a gate pattern is formed in the silicon nitride layer 36. Subsequently, an ion implantation process is performed to form a plurality of doped regions 42 in the silicon substrate 32 as the anode and source of the MOS transistor. Then, a thermal oxidation method (t h e r m a 1, 0 x i d a t i ο n) is used to form a field oxide layer 4 4 on the upper surface of the source / non-electrode as an isolation between the silicon nitride layers 36. Finally, a doped polycrystalline silicon layer 46 is deposited as the gate conductive layer, as shown in FIG. The conventional manufacturing method for forming the upper oxide layer requires a higher temperature thermal budget for the formation of an oxide layer on the surface of the nitride, which may lead to the decomposition of the gate oxide layer and affect the quality reliability of N R 0 Μ. In addition, due to the discontinuity of the interface between the Shixi substrate and the bottom oxide layer and the unsaturated bonding on the interface, part of the interface of the it is trapped in the bottom oxide layer, which affects the initiation. The distribution of voltage (threshold voltage). SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a 0 N 0 layer manufacturing method for improving the electrical properties of the bottom oxide layer, so as to improve the write and erase efficiency, endurance, and reliability of nitride read-only memory. Reliability 〇 In the preferred embodiment of the present invention, a first oxide layer is formed on the surface of the silicon substrate of the semiconductor wafer first, and then a rapid heating nitridation is performed.

484210 V. Description of the invention (4) (rapid thermal nitridation (RTN)) process, to perform an annealing process on the first oxide layer, and simultaneously nitride the surface of the first emulsion layer. A low-pressure chemical vapor deposition (LPCVD) is subsequently performed to form a nitride layer on the surface of the first oxide layer. Finally, a second oxide layer is formed on the surface of the nitride layer, so that the second oxide layer, the nitride layer, and the first oxide layer constitute the ON0 layer. I g B t 1 iin Oxygen S δ Fast 11 base laη a a & ad with nn base ni bond (a base ha suspension is rational silicon ec. Ming is in (m interstitial pyrotechnical product of the product back to the reaction The ground power is transmitted through the mechanism of silicon through the mechanism, which is chemically related to the layers.

The 彳 table releases oxygen and oxygen, and the bottom guides y, / layers / 善 善, and the good energy is changing to the existence of oxygen, the base and the process are nitrogen-saturated, and the system is combined} Huasi noodle, 11 ( 1 3 Nitrogen} b Γ S For a detailed description of the invention, please refer to FIGS. 4 to 6, which are schematic diagrams of a method for fabricating a 0 N 0 layer of a nitride read-only memory according to the present invention. As shown in FIG. 4, the present invention The 0N0 layer is fabricated on the surface of a silicon substrate 52 or a silicon-on-insulator (SOI) substrate (not shown) of a semiconductor wafer 50. First, a silicon oxide surface of the substrate 52 is oxidized by a thermal oxidation process to form A bottom oxide layer 54 having a thickness between 40 angstroms and 100 angstroms (angstrom) is used as a communication channel for a nitride read only memory (NR0M).

484210 V. Description of the invention (5) Tunneling oxide layer. The thermal oxidation process uses oxygen (02) and T-LC (C12) as the precursor gas (precursor), and then in an environment containing nitrogen and oxygen (N2 / 02) at a temperature of 800 degrees Celsius (.0 ° C). Next, a rapid thermal nitridation (RTN) process is performed on the bottom oxide layer 54. This process is performed by passing nitrous oxide (N20) between 800 ° C and 1050 ° C. Or nitric oxide (NO) as a reaction gas, the process lasts about 60 seconds to perform an annealing treatment on the bottom oxide layer 54 and simultaneously nitride the surface of the bottom oxide layer 54. For example, at 9 Pass nitrous oxide (N20) or nitric oxide (NO) as the reaction gas at a temperature of 0 0 ° C, or pass nitrous oxide (N2O) or nitric oxide (NO) at a temperature of 95 ° C ) As a reaction gas, which lasts about 60 seconds. In addition to the rapid heating nitriding process and tempering treatment, a nitrogen plasma process, a nitrogen ion cloth value process, or a nitrogen-containing solution soaking process can be used for nitrogen. Surface of the bottom oxide layer 54. Then, as shown in FIG. A low-pressure chemical vapor deposition (LPCVD) process is used to form a nitride layer 56 on the surface of the oxide layer 54. The temperature and pressure conditions of the process are 700 ° C and 0.6 Torr respectively. (Torr), and dichlorosilane (SiCl2H2, DCS), ammonia (ammonia, NM, and nitrogen (I)) as a reaction gas to form a thickness of 110 angstroms on the surface of the bottom oxide layer 54 Nitriding up to 150 angstroms

484210 V. Description of the invention (6) Layer 5 6 〇 Finally, as shown in Figure 6, another thermal oxidation process is performed in an environment containing steam and a temperature of 100 ° C (° C). The surface of the nitride layer 56 is oxidized to form an upper oxide layer 58 having a thickness of about 90 angstroms, so that the upper oxide layer 58, the nitride layer 56, and the bottom oxide layer 54 constitute a nitride read-only memory. N 0 layer 6 0. The invention uses a rapid heating nitriding process to perform an E7 annealing on the underlying oxide layer and nitride the surface of the underlying oxide layer. Therefore, the quality of the oxide layer can be improved, and the electron trapping effect of the underlying oxide layer can be reduced. Reduce the initial voltage distribution and improve the dielectric properties of the bottom oxide layer. Compared with the conventional method of manufacturing a 0N layer of conventional nitride read-only memory, the Ming system = using a rapid heating nitriding process to improve the quality of the bottom oxide layer ^ Xiaoping flat band voltage shift and reduction Fushi Han. The change in the right voltage (Fowier — Nordheim voltage) further increases the write and erase efficiency, durability, and feasibility of the gaseous read-only memory. In addition, the method of the present invention can also be applied to a procedure for preparing a 0N0 layer of a general capacitor and the like. The specific reference ^ ΐ = is only a preferred embodiment of the present invention, and the scope of application is covered according to the present invention. < Fluorescence and modification of spoon 4 should be covered by the patent of the present invention

$ 9 pages 484210 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a schematic diagram of the standard structure of a conventional nitride read-only memory. Figures 2 and 3 are schematic diagrams of conventional methods for making nitride read-only memory. FIG. 4 to FIG. 6 are schematic diagrams of a method for fabricating a 0 N 0 layer of a nitride read-only memory according to the present invention. Symbols shown in the figure: 1 0 ^ 30 channels, 3 spheres, 22 ^ 38, upper oxide layer 1 2 '32, silicon substrate 24, 40 0 N 0 dielectric structure 14, 16, 42 doped regions 26, 46 gate Conductive layer 1 8 '34 bottom oxide layer 44 field oxide layer 9 0 > 36 silicon nitride layer 50 semiconductor wafer 52 silicon substrate 54 bottom oxide layer 56 nitride layer 58 upper oxide layer 60 ONO layer

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Claims (1)

484210 VI. Scope of patent application 1. A method for manufacturing an 0N0 (oxide-nitride-oxide) layer, the method includes the following steps: providing a substrate; forming a first oxide layer on the surface of the substrate; performing a rapid force A rapid thermal nitridation (RTN) process is performed to perform an annealing process on the first oxide layer and simultaneously nitride the surface of the first oxide layer; forming on the surface of the first oxide layer A nitride layer; and forming a second oxide layer on the surface of the nitride layer, so that the second oxide layer, the nitride layer, and the first oxide layer constitute the 0 iN 0 layer. 2. The manufacturing method according to item 1 of the patent application scope, wherein the substrate is a stone-on-insulator or silicon-on-insulator (SOI) substrate. 3. The manufacturing method of item 2 in the scope of patent application, wherein the first oxide layer is formed by oxidizing the silicon surface of the substrate using a first thermal oxidation process, and the thickness of the first oxide layer is between 4 0 angstrom to 100 angstrom (angstrom) 04. For example, the manufacturing method of item 3 of the patent application scope, wherein the first thermal oxidation process is performed in a nitrogen and oxygen (N2 / 02) containing temperature between In an environment of 800 degrees Celsius (r). 484210 (1) Application scope of patent 5. For the method of making the patent application No. 4, the precursor of the first thermal oxidation process is oxygen (02) and T-LC (C12). 6. If the manufacturing method of item 1 of the scope of patent application, the rapid heating nitriding (RTN) process lasts about 60 seconds, and the process temperature is between 80 ° C to 105 ° C, and the The reaction gas for the rapid heating nitriding (RT N) process is nitrous oxide (N20) or nitric oxide (NO) ° 7. The manufacturing method according to item 1 of the scope of patent application, wherein the thickness of the nitrided layer is between 110 angstroms and 150 angstroms. 8. The manufacturing method of item 1 in the scope of the patent application, wherein the method for forming the nitrided layer is a low pressure chemical vapor deposition (100 w-p r e s s u r e chemical vapor deposition, LPCVD). 9. For example, the manufacturing method of item 8 in the scope of patent application, wherein the process temperature and pressure of the low pressure chemical vapor deposition (LPCVD) are 700 ° C. and 0.6 Torr, respectively, and the low pressure chemical vapor phase The reaction gas for deposition (LPCVD) includes dichlorosilane (SiCl2H2, DCS), oxygen (ammon ia, N H3), and nitrogen (N2). l〇. The manufacturing method of item 1 in the scope of patent application, wherein the second oxidation Page 12 484210 VI. Scope of patent application The layer is formed by oxidizing the surface of the nitrided layer by a second thermal oxidation process, and the thickness of the second oxide layer is about 90 angstroms. 11. The manufacturing method of item 10 in the scope of patent application, wherein the second thermal oxidation process is performed in an environment containing steam and a temperature of 1000 degrees Celsius (° C). 12. The manufacturing method according to item 1 of the application, wherein the first oxide layer is used as a tunneling oxide layer of nitride read only memory (n 1 y meniory, N ROM). . 13. A method of manufacturing a ΟΝΟ (oxide-nitride-oxide) layer, the manufacturing method includes the following steps: providing a substrate; forming a first oxide layer on the surface of the substrate; and subjecting the first oxide layer to a surface treatment Forming a nitride layer on the surface of the first oxide layer; and forming a second oxide layer on the surface of the nitride layer so that the second oxide layer, the nitride layer, and the first oxide layer constitute the 0 N 0 layer. 14. The manufacturing method according to item 13 of the scope of patent application, wherein the substrate is a silicon substrate or a silicon-on-insulator (SOI) substrate. 15. The manufacturing method according to item 14 of the scope of patent application, wherein the first oxidation Page 13 484210 VI. The scope of the patent application layer is formed by using a thermal oxidation process to oxidize the broken surface of the substrate, which is used as a tunneling oxide layer of nitride read-only memory (NR0M). The thickness of the first oxide layer is between 40 angstroms and 100 angstroms. 16. The production method according to item 15 of the scope of the patent application, wherein the thermal oxidation process is performed in an environment containing nitrogen and oxygen (N2 / 〇2) and the temperature is between 800 degrees Celsius (° C), and the heat The precursor gases of the oxidation process are oxygen (〇2) and T " ~ LC (C12). 17. If you apply for the production method of item 13 of the scope, where the surface treatment includes an annealing treatment (annealing) ), A nitrogen plasma process, a nitrogen ion value process, or a nitrogen-containing solution soak process. 18. For the manufacturing method of item 1 in the scope of patent application, the tempering process is a process using nitrous oxide ( N20) or nitric oxide (NO) as a reactive gas, and a rapid heating and nitriding (RTN) process at a temperature between 800 ° C to 105 ° C and a duration of about 60 seconds. 19 · If applying for a patent The manufacturing method of the item 13 in the range, wherein the nitrided layer is formed by a low pressure chemical vapor deposition (LPCVD), and the thickness of the nitrided layer is between 110 angstroms and 150 angstroms (angstr. 〇m). 20. If the manufacturing method of item 19 in the scope of patent application, The low-pressure chemical Page 14 484210 VI. Patent application scope The process temperature and pressure of LPCVD are 700 ° C and 600 millitorr (mTorr) respectively, and the low pressure chemical vapor deposition (LPCVD) The reaction gas includes digas silane (SiCl2H2), ammonia (NH3), and nitrogen (N2). 2 1. The production method according to item 13 of the scope of patent application, wherein the thickness of the second oxide layer is about 90 angstroms, and the second oxide layer is formed of a steam containing steam at a temperature of about 90 angstroms. It is formed by oxidizing the surface of the nitrided layer in an environment of 100 degrees Celsius (° C). Page 15