TW483090B - Manufacturing method of high-density stacked metal capacitor device - Google Patents

Abstract

The present invention provides a manufacturing method of high-density stacked metal capacitor device, which includes the steps of: (a) providing a semiconductor substrate embedded with a first metal block, partial surface of the substrate exposing the upper surface of the first metal block; (b) globally forming a first dielectric layer on the semiconductor substrate; (c) selectively removing the first dielectric layer to form a first opening for exposing the first metal block, so as to define the range of a second metal block; (d) filling the second metal block into the first opening to make the first and second metal blocks as the bottom electrode of the metal capacitor device; (e) globally forming a second dielectric layer on the bottom electrode of the metal capacitor device; (f) selectively removing the second dielectric layer, thereby forming a second opening for exposing the bottom electrode surface of the metal capacitor device; (g) adaptively forming a third dielectric layer at the bottom and sidewall of the second opening for use as a dielectric layer of the capacitor device; and (h) filling a third metal block into the second opening for use as the top electrode of the capacitor device.

Description

^ 3090 V. Description of the invention (1) The present invention relates to a method for manufacturing a high-density stacked MIM capacitor element, and more particularly to a method for manufacturing a high-density stacked MIM copper capacitor element that can increase the electrode area. [Description of the conventional technology] Please refer to FIG. 1, which shows a schematic diagram of a scraped surface of a flat plate M 丨 M copper capacitor of the conventional technology. First, please refer to Figure 1. Symbol 10 indicates the steel embedded in the semiconductor substrate. The bottom is used as the lower electrode of the capacitor element. The symbol 丨 丨 indicates the copper block used as the upper electrode of the capacitor 70. The symbol 丨2 indicates upper and lower electrode fields = dielectric layer. Although "copper" is currently the best material for capacitor electrodes, copper metal can only be removed by chemical mechanical polishing (CMp), and helmets, but traditional chemical dry etching or wet etching is used to remove it, so it is difficult to use. Stacked capacitor steel electrodes. Therefore, it is common / difficult to produce flat-type MIM copper capacitors (as shown in the figure!). ， 1 is still used. But as the size of the capacitor element shrinks, but it needs to be increased. Two research directions can be considered. One is to improve the area of the capacitor electrode when the dielectric material = 篁. In view of this, the present invention states that "the nature" is a grinding method and a traditional deposition and lithography process: ^ under the chemical mechanical? Under the material 'to produce a high-density stack to the conventional volume in the same volume space , Than the conventional flat electrical components; that is, the area of the capacitor electrode can have a larger capacitance;

0503-5930TWF; TSMC2000-0602; Jacky.ptd Page 5 483090 5. Description of the invention (2) [Summary of the invention] In order to achieve the above purpose, the present invention uses chemical mechanical polishing method and traditional deposition and lithography etching process to produce Each high-density MIM metal-electric component has the following manufacturing steps: (a) providing a semiconductor substrate inlaid with a first gold f block; and a surface of the base portion is exposed from an upper surface of the first metal block. (B) A first dielectric layer is formed over the semiconductor substrate comprehensively. (C) Selectively removing the first dielectric layer to form a first opening exposing the first metal block to define a second metal region. (D) Fill the second metal block into the first opening, so that the first metal block and the second metal block are used as power-off of the metal capacitor element. (E) Comprehensively forming a second dielectric layer on the lower electrode of the metal capacitor element. (F) selectively removing the second dielectric layer, and forming a second opening on the surface of the lower electrode of the metal valley device. (8) A third dielectric layer is formed on the bottom and side walls of the second opening to conform to the dielectric layer of the I element, and (h) is filled in the second opening-Tian Di Er The metal block is used as the electrode above the capacitor. Before performing step (b) in step 2, it further includes forming a full stop layer over the half substrate. Before performing step (e), 'f 白 乜 少 #' conforms to the surface of the lower electrode for a while to form a stop / stop layer on the semiconductor substrate.

Cn, Pt, Pd, or RU ... etc. The second metal block is, for example, the first one in the above method — Shi Xi. And the first "electrical layer is, for example, dioxide

0503-5930TWF; TSMC2000-0602; Jacky.ptd Page 6 483090 V. Description of the invention (3) " One-eight of which the method described above is used as the dielectric layer of the capacitive element: " The layer is made of silicon nitride (SiN / Si3N4) or silicon oxynitride (SiON). Among them, the method of filling the second and third metal blocks includes the first step. The metal blocks are firstly formed by a deposition method (such as CVD), and then the chemical mechanical polishing method (CMp) is used. ) To flatten the gold blocks. Both are here, and the object of the present invention is to provide a method of removing deposition and lithography etching steps without the need to change the habit of electrical materials, plus the use of chemical polishing to remove the surface of excess metal blocks. And smoothing, and the manufacturing of MIM I Valley using the stacked of copper manufacturing process, can increase the capacitance, characteristics, and advantages of μ I Μ capacitors compared to conventional flat capacitors. In order to make the above and other objects of the present invention more comprehensible, the following detailed description is given in detail in conjunction with the accompanying drawings: [A brief description of the drawings] Figure 1 shows The cross-sectional schematic diagram of a conventional plate-shaped M! M copper capacitor is shown in the second figure, which shows the manufacturing process of the high-density stacked MIM copper capacitor of the present invention. The figure is a diagram showing the high-density stacked copper capacitor of the present invention.

483090

[Explanation of component symbols] 10, 20 ~ copper block lower electrode, 12, 22 ~ dielectric layer, 110 ~ first copper block, 130 ~ first dielectric layer, 150 ~ first opening, 180 ~ first Two dielectric layers, 210 ~ third copper block, 11, 2 1 ~ copper block upper electrode, 100 ~ semiconductor substrate, 1 2 0, 17 0 ~ remaining stop layer, 140, 190 ~ photoresist layer, 160 to the second copper block, 200 to the second opening, and 220 to the third dielectric layer. Example: The following is a schematic cross-sectional view of the manufacturing process of the high-density stacked MIM capacitor element shown in Figs. 3a to 3j to illustrate the preferred implementation of the present invention using a copper process as an example. First, please refer to Fig. 3a. The semiconductor substrate 100 of the metal block 110, a part of the surface of the substrate 100 is exposed with the first "upper surface of the block no" and the first-metal block 11 is used as an electrode below the electrical element. A explained, the first,-= metal block i1Q in this embodiment is, for example, a metal block such as Gu, Pt, pd ^ u, but this embodiment uses a copper block as an example. Then refer to FIG. 3b, It can be firstly formed on the East iL X-stop stop layer 120 '< column jt conductor substrate 100 comprehensively-for example & SiN or SiON. Then, comprehensiveness 2 is formed as the first layer of an emulsified stone layer A dielectric photoresist layer 140 has Danwen Futian after the first dielectric layer ηη μ. The photoresist layer is on U0, and the pattern is defined by lithography. The photoresist layer 14 is removed after that. ^

483090 V. Description of the invention (5) Next, referring to FIG. 3c, the first dielectric layer 130 and the etch stop layer 12 are selectively etched and removed to form a first portion exposing the first copper block 11 (). An opening 15 is defined to define a range of a second copper block 16 of the capacitor element. For the etching method, for example, photoresist 140 is used as a mask, and anisotropic etching is performed by a reactive ion etching method (RIE). Next, referring to FIG. 3d, a second copper block 160 is formed in the first opening 150. For example, copper is deposited by CVD. Next, chemical mechanical polishing (CMP) is used to remove part of the second copper block 160 so that the upper surface of the second copper block 160 is the same as the surface of the first dielectric layer 13. On the plane, as shown in FIG. 0 //, at this time, the first copper block 110 and the second copper block 160 are jointly defined to form an electrode under the capacitor element. Next, the first dielectric layer 130 and the etch stop layer 12 are removed by using an etching method, and as shown in FIG. 3 丨 See the FIG. 3g, the compliance of the lower electrodes 110 and 160 may be first = The etch stop layer 170 is, for example, Si “tSiON. Then, a second dielectric layer 190 is formed on the second dielectric layer, such as a stone dioxide layer, in a comprehensive manner. 18 () μ ^ MH and the pattern is defined by lithography. Next, referring to the 3h figure, write a liIt ^ t 1 β η ^ ^ t 1 ^ 1 ^ selectively remove the second dielectric layer 180 and the etch stop layer 17. ^ ^ .Pa n9nn P; w ^ b to form a first opening 2 0 0 that exposes the lower electrodes ll 0 and l 60 to define the third copper area of the thunder ^ m plus mountain ^ i. 1 Λ valley 70 The range of block 210. For example, using a photoresist i 9 〇 eli and # 分 非 笪 a from al w dry screen, by reactive ion etching to form non-directional etching and forming # & 夂 成Or the second opening 2 00. Then remove

483090

The photoresist layer is 190. Then referring to FIG. 3i, using the prepared wind γ ^… three dielectric layers 220 on the second dielectric two-phase, the process is formed to form a surface of No. 〇Πη ^ _ ”, which extends to the second opening

SiON: ° and "wall", where the third dielectric layer 220 may be SiN or made of a two-tit coefficient material, and the third dielectric layer 220 is a dielectric layer between the lower electrodes. After that, 3 gens were deposited and filled into the first: opening 200 to form a third copper block 21o, which was used as the electrode 2100 on the metal capacitor. Finally, a chemical mechanical polishing of copper was performed on the capacitor. The remaining part of the electrode 21 is removed to form a coplanar surface with the third dielectric layer 220. As shown in the figure, a high-density stacked MIM copper capacitor element is completed. Therefore, comparing the conventional plate-type M 丨 M capacitor in Fig. 1 with the stacked MIM capacitor of the present invention in Fig. 2, it can be seen that the electrode area of the pile-type MIM capacitor in Fig. 2 is smaller than the conventional plate under the same volume. The electrode surface of the MIM capacitor has a large number of electrodes, and can have a large capacitance. Although the present invention has been disclosed in the preferred embodiment as above, it is not a limitation of the present invention. Any person skilled in the art can make changes and retouching without departing from the scope of the present invention. Therefore, the protection of the present invention # = Subject to the scope of the attached patent application. dry

Claims (1)

^ ό [) 90 6. Scope of patent application — 1. A method for manufacturing a high-density stacked metal capacitor element, the steps are as follows: ρ (a) Provide a semiconductor substrate inlaid with a first metal block, and the surface of the substrate portion is exposed The upper surface of the first metal block; (b) forming a first dielectric layer over the semiconductor substrate comprehensively; (c) selectively removing the first dielectric layer to form an exposed first metal region A first opening of the block to define a range of a second metal block; (d) filling the second metal block in the first opening so that the first metal block and the second metal block The block serves as the lower electrode of the metal capacitor element; (e) a dielectric layer is formed over the lower electrode of the metal capacitor element comprehensively; (f) the second dielectric layer is selectively removed to form A second opening exposing the surface of the lower electrode of the metal valley device, (g) conformingly forming a third dielectric layer at the bottom and sidewalls of the second opening to serve as the dielectric layer of the capacitor element; and ( h) filling a third metal in the second opening Block to serve as the electrode above the capacitive element. 2. The method according to item 1 of the scope of patent application, wherein before step (b) is performed, it further comprises forming an etch stop layer on the semiconductor substrate comprehensively. 3 · The method described in item 1 of the scope of patent application ', wherein 0503-5930TWF; TSMC2000-0602; Jacky.ptd 483090, patent application scope " Before the chicken (e), it further includes forming an etch stop layer on the semiconductor substrate to conform to the surface of the lower electrode. ^ 4. The method according to item 2 or 3 of the scope of patent application, wherein the etching stop layer is deposited silicon nitride or silicon oxynitride. 5. The method as described in item 1 of the scope of patent application, wherein the first, second or second metal block is deposited copper (Cu), platinum (pt), palladium (pd) or (Ru). The method as described in claim 1 of the patent scope 'The first, second or second metal block is deposited copper. 7. The method according to item 1 of the scope of patent application, wherein the first or second dielectric layer is deposited silicon dioxide. 8. The method according to item 1 of the scope of the patent application, wherein the third dielectric layer used as the dielectric layer of the capacitive element is deposited silicon nitride (SiN / Si3N4) or silicon oxynitride (Si. N). 9 The method of filling in the second and third metal blocks as described in item 1 of the scope of the patent application, and / or the method of filling in the second and third metal blocks, including the steps of forming the first by a deposition method (CVD) Equal gold f 2 J, chemical mechanical polishing method (CMP)