293900 A7 經濟部中央橾準局貞工消費合作社印製 __B7五、發明説明（(） 〔發明背景〕 1 .發明領域 本發明傜大致關偽於電阻器，其俱形成在半導體積體 電路基底之上及基底内。更明白地說，本發明僳闕傜於一 三度空間複矽電阻.其偽使用於有限空間之先進半導體積 體電路裝置單元之中《> 2 .相關前技說明 除了電阻器及二極體之於半導體積體電路中，使用作 為開闢元件及霉流整流装置外，於本技藝中亦是相當普僱 地，這些電輅具有電阻器併入其設計及製造中。通常，一 痼在積髏電路中之電阻器结構將提供一電路負載，其確保 電路在電路設計之電流及電醱參數下適當操作β 以下有幾個方法及材料，該諸霄阻器樣可以被設計與 製作進入一半導髏積體霄路之中β —種常用之傳統方法偽 製作電阻器於一積髏電路裝置中之矽半導體基底之内。可 變電阻值之電阻係可以在半導體基底之内被簡單地製作， 藉由經一離子佈植程序，摻雜該半導髅基底，該程序傜類 似於使用以形成其他主動半導體區域於相同半導體基底内 之離子佈植程序。藉由佈植摻雜離子至半導體基底以形成 電阻器之程序偽可行的技術，除非電阻器偽需要超過半導 體基底之電阻值，而電阻器像想要被製作於其中。 一另一方式，其提供大於或等於形成於半導體基底中 電阻中之霄阻值.傜為由一离阻性材料之分立部份形成電 -3- (請先M讀背面之注意事項再填寫本頁) .Γ·装. 訂 f 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央橾準局貝工消费合作社印製 A7 ______B7 _五、發明説明（、/) 阻器，其傺被沉積於該低電阻性半導體基底之表面上β — 常用高電阻性材料，其傜有用於形成較高電阻性電阻者， 係可以被不摻雜或輕摻雜複但是，於本技藝中像知道 該高摻雜複矽像為一優良導體，藉由該複矽在積體電路裝 置中之導體結構可以被製作，亦可以知的該未摻雜或輕摻 雜複矽偽可以為高電阻性材料。 當由一高阻性材料，例如，未摻雜或軽摻雜複矽材料 , 一電阻器之電阻性可以由直接考董β明白地說，複矽 電阻器之電阻值傷可以直接額定於該電阻器形成複矽層之 長度，以及，額定地反相有關於由霄阻所形成之電阻器之 該複矽層之截面區域。於積體電路中，對於藉由平面薄膜 複矽處理所形成在積體電路中之複矽電阻器，複矽電阻器 之電阻值傜於額定相反於相關之厚度及複矽«之寬度，該 電阻器偽形成於其寬度及厚度之間。 一典型形成於一積體電路中之複矽電阻器之截面圖偽 被示於圖式1〇在圖式1中，其中示出一半導體基底10 ，其上俗形成一絶緣層1 2。在該絶緣《1 2之上偽形成 一複矽層，其葆包含複矽Jll 4a, 14b及14C»内 佇於一有圖案之光阻層1 6下之複矽層1 4 b形成一複矽 電阻器。該複矽層1 4 a及1 4 cm典型地通常被順序地 重摻雜，藉由一離子佈植處理，以形成導體摻雜複矽端至 該複矽電阻器，其僳由複矽層14 'D所作成。 當半導髏技術已經進步時，對衝之趨勢已經加以涉及 本紙乐尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) X〆 裝_ 訂 Γ 經濟部中央揉準局貝工消费合作社印製 Α7 Β7 五、發明説明（>) •其需求霉阻器之電阻値之增加•同時提供減少之半導體 基底表面·以在運表面上遒些電阻器係可以加以製作。另 外，在積體電路裝霾中所形成高電阻值電阻之未摻雜或輕 摻雜複矽層之厚度係接近其極限•現行半導體裝霤可以有 效地與可再製地沉稹這些餍〇 因此•本發明所針對之問題是定義一更有效之高電阻 値未摻雜或輕摻雜之複矽霉阻結構及其製造成半導髏積體 霉路中之方法••所想想之高電阻値複矽電阻器結構將提供 一足夠有限表面區域之霉阻器•以讓該霉阻器可以有效地 使用半導艚基底表面區域。該高®阻値複矽電阻器所形成 之方法將不會被不當地變更已建立之半導«製作處理及處 理限制》 在本技藝中並未揭示的是•可以在半導體積體電路中 製作複矽電阻器之方法•該諸電阻器相較於相同大小之等 置電阻具有一實質增加之霉阻值》於本技藝中並未揭示一 種方法•一有限蓐度及表面區域之複矽電阻之電阻値可以 增加·而不會增加該電阻之長度及減少胲電阻之厚度。 〔發明概要〕 本發明之第一目的係提供一複矽霉阻器於一半導髓檟 體罨路之中•該罨阻器相較於一已知技S中之複矽鼋阻器 具有一高電阻値β 本發明之第二目的係依攄本發明之第一目的提供一複 矽霉阻•該複矽霉阻之尺寸區域及厚度係相符於本技藝中 -5- 本紙張尺度逋用中國國家標準（CNS ) A4現格（210X297公釐） . (請先《讀背面之注意事項45-.填寫本頁) -* 經濟部中央梂準局貝工消費合作社印裂 A7 B7五、發明説明（/) 之先進理矽電阻器者。 本發明之笫三目的像依據本發明之第一及第二目的提 供一複矽電阻器，該霉阻器傜可以以現行可用之半導體製 造設備加以迅速地製造。 依據本發明之這些目的，一新複矽電阻器及其製作方 法傜被加以描述。為了形成複矽電阻器，一絶緣層傜首先 形成於一半導髏基底之上β該绝緣層具有最少一孔徑形成 至少部份貫通其間。在該絶緣《被沉積上一複矽層時，該 複矽層僳形成重合於形成於該絶緣層中之孔徑中。該包含 複矽層之部份之複矽層之一部份偽形成本發明之三度空間 複矽電阻，其中，複矽層傑形成重合該孔徑中》 本發明之方法所形成複矽電阻展現之電阻值，俱實際 超出以一等效方法之電阻器之電阻值，該等效方法偽沒有 使用一下《孔徑進入本發明之複矽電阻器重合形成處者。 本發明之方法所形成之複矽電阻傜可以迅速地加以製 造。本發明之複矽電阻係可以藉由相同於習用複矽電阻之 方法，而加以製作，除了增加了幾個步驟之外，該諸步驟 係箱要以形成進入該絶緣層之孔徑，而該絶緣層偽在本發 明之複矽電阻器之下β於一些半導髏處理中，沒有其他之 步驟傺被加以用以形成孔徑進入該絶緣庙中，該絶緣層係 在本發明之複矽電阻器之下。雖然，當需要以形成孔徑時 ，其他之光學製販術及蝕刻處理将被增加製作上之複雜， 以用於形成本發明之複矽電阻器，但是，所增加之光學製 -6- (請先閲讀背面之注意事項再填寫本頁) i^i HI 1^1 t— - I —A ) 裝. 訂 " 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） 203950 a? B7 經濟部t央橾準局負工消費合作社印製 五、發明説明（jr.) 販術及蝕刻處理對於本技藝中之半導體製作而言偽為已知 的。 〔圖式之簡要說明〕 以下之圖式形成本發明之一部份，其偽為： 圖式1傑為先前技藝中之複矽電阻器之一剖面示意圖 〇 圖式2 a至2 d示出本發明之三度空間複矽霉阻之一 較佳實施例。 圖式3 a及3 b依據本發明之原則所形成之電阻器測 試結檐之示意圖。 〔較佳實施例之詳細說明〕 本發明傜大大地不同於習用之用於形成複矽電阻於積 髏電路裝置中之方法。本發明提供一三度空間複矽電阻器 ，其傜形成重合進入一於一絶緣層中之最少一孔徑，該絶 縐層係在該複矽電阻之下《該如此所形成之複矽霣阻具有 一較高之霣阻值相較於習用之相等厚度及尺寸大小區域之 複矽電阻器而言《本發明之複矽電阻器之較高電阻值位準 對於先進之半導體積體電路中而言傜想要的，該積體電路 只有提供有限之表面區域給電阻器。 在本發明之三度空間内之後矽電阻中，由霣阻所形成 之複矽層偽作成三度空間，藉由將裎矽屬形成重合於一最 少一形成在一絶緣層内之孔徑，該绝緣®偽在複矽層之下 。藉由此一方式，以形成一複矽電阻層，該複矽霣阻層之 -7- ;------I - II 1^ 卜 - - I —Jm - - - -1 - I- k— ^^1 n • - (請先閲讀背面之注意事項再填寫本頁) 訂293900 A7 Printed by the Zhengong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economics __B7 V. Description of the invention (() [Background of the invention] 1. Field of the invention The invention is roughly related to resistors, which are all formed on the semiconductor integrated circuit substrate Above and inside the substrate. More clearly, the invention is in a three-dimensional space complex silicon resistor. It is pseudo-used in advanced semiconductor integrated circuit device units with limited space "> 2. Related prior art description In addition to the use of resistors and diodes in semiconductor integrated circuits, as development components and mold flow rectifiers, it is also quite common in the art, these electric devices with resistors are incorporated into their design and manufacture In general, a resistor structure in Jaeger-LeCoultre circuit will provide a circuit load, which ensures proper operation of the circuit under the current and electrical parameters of the circuit design. There are several methods and materials below. It can be designed and fabricated into half of the guide skeleton integrated road β-a commonly used traditional method to pseudo-resistor within a silicon semiconductor substrate in a skeleton skeleton circuit device. Variable resistance value The resistors can be easily fabricated within the semiconductor substrate by doping the semiconducting skull substrate through an ion implantation process, which is similar to the ion distribution used to form other active semiconductor regions in the same semiconductor substrate Implantation process. The process of forming a resistor by implanting doped ions into a semiconductor substrate is a pseudo-feasible technique, unless the resistor needs to exceed the resistance value of the semiconductor substrate, and the resistor seems to be made in it. Method, which provides a resistance value greater than or equal to the resistance formed in the semiconductor substrate. 傜 is formed by a discrete part of a resistive material -3- (please read the precautions on the back before filling this page) .Γ · 装. The size of the f-line paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). A7 ______B7 _V. Invention description (, /) , Its Ye is deposited on the surface of the low-resistance semiconductor substrate β-commonly used high-resistance materials, its Ye is used to form a higher resistance resistance, can be undoped or light However, in this technology, it is known that the highly doped complex silicon image is an excellent conductor, and the conductor structure in the integrated circuit device can be manufactured by the complex silicon, and the undoped or light The doped complex silicon can be a highly resistive material. When a highly resistive material, for example, undoped or lightly doped complex silicon material, the resistance of a resistor can be clearly stated by The resistance value of the silicon resistor can be directly rated to the length of the complex silicon layer formed by the resistor, and the rated inversion is related to the cross-sectional area of the complex silicon layer of the resistor formed by the small resistance. In the case of a complex silicon resistor formed in an integrated circuit by planar thin-film complex silicon processing, the resistance value of the complex silicon resistor is equal to the rated thickness opposite to the relevant thickness and the width of the complex silicon «, the resistor is pseudo-formed Between its width and thickness. A typical cross-sectional view of a complex silicon resistor formed in an integrated circuit is shown in Figure 10. In Figure 1, a semiconductor substrate 10 is shown on which an insulating layer 12 is formed. A pseudo-silicon layer is pseudo-formed on the insulation «12, which contains the complex silicon Jll 4a, 14b and 14C» and the complex silicon layer 1 4 b under the patterned photoresist layer 16 forms a complex Silicon resistors. The complex silicon layers 14 a and 14 cm are typically heavily doped sequentially, and an ion implantation process is used to form a conductor-doped complex silicon terminal to the complex silicon resistor, which is composed of a complex silicon layer 14 'D made. When the semi-conducting skull technology has improved, the trend of hedging has been involved. This paper music standard applies to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) X〆 装 _ Order Γ Printed by the Ministry of Economic Affairs Central Bureau of Precision Industry Beigong Consumer Cooperatives Α7 Β7 V. Description of the invention (>) • The demand for the increase of the resistance value of the mold resistor • At the same time provide a reduced surface of the semiconductor substrate · to be on the transport surface These resistors can be made. In addition, the thickness of the undoped or lightly doped multi-silicon layer of high resistance value formed in the integrated circuit package is close to its limit. The current semiconductor package can effectively and reproducibly sink these materials. • The problem addressed by the present invention is to define a more efficient high-resistance undoped or lightly doped complex silicon mold resistance structure and the method of manufacturing it into a semiconducting skeleton integrated mold road The resistor-resistive silicon resistor structure will provide a mold resistor with a sufficiently limited surface area so that the mold resistor can effectively use the surface area of the semiconducting stern base. The method of forming this high-resistance complex silicon resistor will not be unduly changed. The established semiconductor «Manufacturing process and processing limitations» What is not disclosed in this technology is that it can be fabricated in semiconductor integrated circuits Method of complex silicon resistors • These resistors have a substantially increased mold resistance compared to equal-sized resistors of the same size. "A method is not disclosed in the art. • A complex silicon resistor with a limited degree and surface area The resistance value can be increased without increasing the length of the resistance and reducing the thickness of the resistance. [Summary of the Invention] The first object of the present invention is to provide a compound silicon mold resistor in the half of the medullary guidance body path. The resistor has a high level compared to the compound silicon resistor in a known technology. Resistance value β The second object of the present invention is to provide a compound silicoresistance according to the first object of the invention. The size area and thickness of the compound silicoresistance are consistent with this technology. -5- This paper size is used in China National Standard (CNS) A4 is now available (210X297mm). (Please first read "Notes on the back 45-. Fill in this page")-* The Central Bureau of Economic Affairs of the Ministry of Economic Affairs, Shell and Consumer Cooperative Printed A7 B7 V. Description of Invention (/) Advanced silicon resistors. The third object of the present invention is to provide a complex silicon resistor according to the first and second objects of the present invention. The mold resistor can be quickly manufactured with currently available semiconductor manufacturing equipment. According to these objects of the present invention, a new complex silicon resistor and its manufacturing method are described. In order to form a multi-silicon resistor, an insulating layer is first formed on half of the guide base. The insulating layer has at least one aperture formed at least partially through. When the insulating silicon layer is deposited with a complex silicon layer, the complex silicon layer is formed to coincide with the aperture formed in the insulating layer. A part of the multi-silicon layer including the part of the multi-silicon layer pseudo-forms the three-dimensional spatial multi-silicon resistor of the present invention, wherein the multi-silicon layer is formed to coincide with the aperture. The resistance value actually exceeds the resistance value of the resistor in an equivalent method. The equivalent method does not use the "Aperture into the complex silicon resistor of the present invention where the overlap is formed. The complex silicon resistors formed by the method of the present invention can be quickly manufactured. The complex silicon resistor of the present invention can be manufactured by the same method as the conventional complex silicon resistor. In addition to adding several steps, the steps are to form an aperture into the insulating layer, and the insulation The layer pseudo is under the complex silicon resistor of the present invention. In some semi-conductor processing, no other steps are used to form an aperture into the insulating temple. The insulating layer is the complex silicon resistor of the present invention. under. Although, when it is necessary to form an aperture, other optical manufacturing techniques and etching processes will be added to the manufacturing complexity to form the complex silicon resistor of the present invention, but the added optical system-6- (please first Read the precautions on the back and fill in this page) i ^ i HI 1 ^ 1 t—-I —A) Binding. Order " This paper size is applicable to the Chinese National Standard (CNS) A4 Washing (210X297mm) 203950 a? B7 Printed by the Ministry of Economic Affairs, the Central Bureau of Preparatory Work, and the Consumer Cooperative. V. Description of Invention (jr.) Vending and etching are pseudo-known to semiconductor manufacturing in this art. [Brief Description of the Drawings] The following drawings form part of the present invention, which is pseudo: Figure 1 is a schematic cross-sectional view of a complex silicon resistor in the prior art. Figures 2 a to 2 d show One of the preferred embodiments of the three-dimensional space compound silicoresistance of the present invention. Figures 3a and 3b are schematic diagrams of the resistor test eaves formed according to the principles of the present invention. [Detailed description of the preferred embodiment] The present invention is greatly different from the conventional method for forming a complex silicon resistor in an integrated circuit device. The present invention provides a three-dimensional spatial complex silicon resistor, which forms at least one aperture that overlaps into an insulating layer, and the insulating layer is below the complex silicon resistor. Compared with the conventional complex silicon resistors of equal thickness and size, the higher resistance value of the complex silicon resistor of the present invention is higher for advanced semiconductor integrated circuits. What Yan wants, the integrated circuit only provides a limited surface area for the resistor. In the silicon resistance after the three-degree space of the present invention, the complex silicon layer formed by the upper resistance is assumed to be a three-dimensional space. Insulation® Pseudo under the multi-layer silicon layer. In this way, a complex silicon resistive layer is formed, the complex silicon resistive layer of -7-; ------ I-II 1 ^ Bu--I —Jm----1-I- k— ^^ 1 n •-(Please read the precautions on the back before filling out this page)
X 線 本紙張尺度適用中國國家梂準（CNS ) A4规格（210X297公釐） 經濟部中央梂準局貝工消費合作社印製 A 7 __B7 ___ 五、發明説明（l) 片霄阻值偽被增加β該所增加之Η電阻值傣相較於相等大 小之習用複矽電阻器，提供一較高電阻值之複矽霣阻。 本發明之複矽電阻器可以被使用於積體霣路中，其中 像需要高電阻在有限之半導體基底區域中，這傜可由本發 明之後矽電阻完成β藉由本發明之方法所形成之霄阻可以 使用於積體霣路之中，但不限制於動態随機存取記億體（ DRAM)積體電路，動態隨機存取記億體（SRAM) 積體電路，雙極性電晶體積體電路及場效霄晶體積體電路 Ο 現參照圖式2 a至圖式2 c,其中示出一条列剖面示 意圖，其例示處理之步驟，藉由這些步驟本發明之三度空 間複矽電阻傜可以加以形成。圖式2 d示出一平面圖，例 示出本發明較佳實施例之三度空間複矽霣阻，在其最後步 揉之後。 參照圖式2a,其中示出一半導體基底之剖面圖，例 示出依據本發明之較佳實施例之第一處理步驟β於圖式2 a中，其中，示出一半導體基底1〇,其上偽已經被形成 場氣化绝緣區域1 2 a及1 2 ^雖然，本發明可以被以 各種之摻雜濃度，各種摻雜極性及各種定向結晶，來實行 於半導體基底上，本發明之半導體基底10之上將典型地 為一具（10 0)定向結晶之N —或P —矽半導體基底加 以實行。 可以用以形成場氣化絶緣區域在半導體基底上之程序 8 - 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 線 a? B7 經濟部t央梂準局貝工消費合作社印製 五、發明説明（y ) ，對於此技蕤中者偽為已知的。這些處理包含但不限制於 ,一半導體基底之部份傜被暴露經由一合適氣化罩，而被 作熱氣化，以形成場氣化绝緣匿域，以及，氣化材料傜被 沉積於一半導體基底之表面及作出圖案，以形成場氣化絶 綠區域之處理◊對於本發明之較佳實施例而言，場氣化絶 緣區域偽較佳地藉由一熱氣化處理加以形成，使得該半導 體基底10之部份經由一合適罩加以暴兹者傜被加以氯化 〇 在形成場氣化絶緣區域1 2 a及1 2 b之後，一覆蓋 後矽層係形成在半導匾基底10之表面上，並作出圖形， 以形成複矽1 1 4 a及1 4 be用以在半導體基底上形成 覆蓋後矽層之方法及材料有好幾種。覆蓋複矽層可以藉由 包含但不限制於處理加以形成，例如，化學氣相沉積（C VD)處理及霣漿加強化學氣相沉積（PECVD)處理 »這些處理可以使用作為矽初级粒子材料用於覆蓋複矽® 矽烷，二矽铳及氮化矽β另外，該覆蓋複矽層可以為導電 性，藉由加入摻雜原子，於形成覆蓋複矽層之處理中，或 藉由摻雜離子之擴散或離子佈植進入先前形成在一半導® 基底之覆蓋複矽S上·»最後，該覆蓋複矽層可以被作出圖 形，藉由包含但不限定之方法，如濕式及乾式霉漿拽刻技 術。 對於本發明之較佳實施例而言，該形成複矽層14a 及複矽1 1 4 b之覆蓋複矽層偽較佳地藉由一低壓化學氣 -9- (請先《讀背面之注意事項再填寫本頁)The X-ray paper size is applicable to China National Standard (CNS) A4 (210X297mm). Printed by the Ministry of Economic Affairs, Central Bureau of Economics and Technology, Beigong Consumer Cooperative A 7 __B7 ___ V. Description of Invention (l) The pseudo resistance of the film is increased β The increased ohmic resistance value Dai provides a higher resistance value of the complex silicon resistance compared to conventional complex silicon resistors of equal size. The complex silicon resistor of the present invention can be used in an integrated circuit, where high resistance is required in a limited semiconductor substrate area, which can be completed by the silicon resistor after the present invention. Β is formed by the method of the present invention. Can be used in integrated circuit, but not limited to dynamic random access memory (DRAM) integrated circuit, dynamic random access memory (SRAM) integrated circuit, bipolar transistor volume circuit And field effect small crystal volume circuit Ο Referring now to Figure 2a to Figure 2c, which shows a series of cross-sectional schematic diagrams, which illustrate the processing steps, by these steps of the present invention, the three-dimensional space complex silicon resistors can be To be formed. Figure 2d shows a plan view, illustrating the three-dimensional spatial complex silicon resistance of the preferred embodiment of the present invention, after its final step of kneading. Referring to FIG. 2a, which shows a cross-sectional view of a semiconductor substrate, illustrating the first processing step β according to the preferred embodiment of the present invention in FIG. 2a, which shows a semiconductor substrate 10, on which Pseudo-gasification insulating regions 1 2 a and 1 2 have been formed. Although, the present invention can be implemented on semiconductor substrates with various doping concentrations, various doping polarities, and various orientation crystals, the semiconductor of the present invention On the substrate 10, a N- or P-silicon semiconductor substrate with (10 0) directional crystallization is typically implemented. Can be used to form a field gasification insulation area on a semiconductor substrate 8-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) • Install . Line a? B7 Printed by the Ministry of Economic Affairs, Central Bureau of Economics and Technology Co., Ltd. Beigong Consumer Co., Ltd. Fifth, the description of invention (y), which is falsely known to those skilled in the art. These processes include, but are not limited to, a portion of a semiconductor substrate is exposed through a suitable vaporization mask and is thermally vaporized to form a field vaporization insulating region, and the vaporized material is deposited on a Treatment of the surface of the semiconductor substrate and the patterning to form the field gasification green area ◊ For the preferred embodiment of the present invention, the field gasification insulation region is preferably formed by a thermal gasification process so that the A portion of the semiconductor substrate 10 is chlorinated by a suitable mask. After forming the field gasification insulating regions 1 2 a and 1 2 b, a covered silicon layer is formed on the semiconducting plaque substrate 10 There are several methods and materials on the surface to make a pattern to form the complex silicon 1 1 4 a and 1 4 be to form the overlying silicon layer on the semiconductor substrate. The overlying silicon layer can be formed by including but not limited to treatments, such as chemical vapor deposition (C VD) treatment and PECVD treatment »These treatments can be used as silicon primary particle materials For covering multiple silicon® silanes, disilconium, and silicon nitride. In addition, the covering multiple silicon layer can be conductive, by adding doping atoms, in the process of forming the covering multiple silicon layer, or by doping ions Diffusion or ion implantation into the covering compound silicon S previously formed on the half-conductor® substrate. »Finally, the covering compound silicon layer can be patterned by methods including but not limited to wet and dry mildew pulp Drag engraving technology. For the preferred embodiment of the present invention, the formation of the multi-silicon layer 14a and the multi-silicon layer 1 1 4 b is preferably covered by a low-pressure chemical gas-9- (please read (Fill in this page again)
XI 裝. <11 線 本紙張尺度遴用中國國家橾牟（CNS ) A4规格（210X297公釐） 經濟部中央梂準局負工消費合作社印製 A7 _B7_ 五、發明説明（t) 相沉積（LPCVD)處理加以形成，使用矽烷作為矽源 材料。該覆蓋複矽層之較佳厚度偽大約1 〇 〇 〇至3 5 0 0埃。一旦，該覆蓋複矽層己經被形成於該半導醱基底1 0上，其偽較佳地使覆蓋複矽層導霄，籍由佈植該屬以磷 摻雜離子，以每平方公分劑量1 Ε 1 6至大約1 Ε 1 6離 子及大約7 0至1 0 OKeV離子佈植之能量《在離子佈 植該覆蓋複矽®之後，該覆蓋複矽層像被作出圖案成為複 矽層14a及14b,較佳地藉由將該覆蓋複矽層傜光罩 並以一反應離子蝕刻麄理，來蝕刻該經過該光罩暴赛之複 矽之部份，該處理偽使用氯及溴化氬作為蝕刻氣體合成物 Ο —旦該複矽層1 4 a及1 4 b已經被由覆蓋複矽層形 成，於本發明之較佳實施例中之下一步驟傜形成絶緣隔層 16a, 16b. 16c 及 16d 於該複矽 ®14a 及 1 4 b之邊緣β這些绝緣隔層傜以一類似於形成複矽層1 4 a及14b之方法加以形成。更明白地說，一覆蓋層之绝 緣材料偽形成在該半導體基底1〇及複矽層14a及14 b之表面^該覆蓋層之絶綠材料像然後被蝕刻，而没有光 罩之出現，以留下绝緣隔屬16a,16b,16c及1 6 d，接合該後矽層1 4a及1 4b之邊綠。 由覆蓋層以形成绝緣隔屬之幾種方法及材料可以加以 形成β這些覆蓋層可以由包含但並不限制於氣化矽及氮化 矽之材料形成。由這些材料形成覆蓋®之方法包含但不限 -10" 本紙張尺度遍用中國國家標準（CNS ) Α4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) 裝 、1Τ 線 A7 B7 經濟部中央橾準局負工消费合作社印製 五、發明説明（7) 制於化皋^相沉稹（c V D )方法及電漿加強化學氣相沉 積（PECVD)方法。這些方法偽典型地為各向異性反 應離子蝕刻（RIE)乾蝕刻方法，其使用一種適用於該 予以蝕刻絶緣材料之蝕刻氣體。 對於本發明之較佳實施例，該绝緣隔igl 6 a, 1 6 b , 1 6 c及1 6 d僳較佳由一氣化矽材料之覆蓋屬上形 成，該绝緣層傣形成於該半導體基底1 0及複矽層1 4 a 及14b之上，經由一低壓化學氣相沉積（LPCVD) 處理，使用原矽酸四乙酯（TEOS)作為矽濂材料。該 覆蓋絶緣1較佳係形成在半導體基底10之上，以大約1 0 0至2 5 0 0埃之厚度。在該覆蓋绝緣層形成之後，該 覆蓋絶緣層偽藉由一各向異性反應離子蝕刻i(RIE)乾 蝕刻處理而加以蝕刻，使用四氟化磺及三氟甲烷作為蝕刻 氣體成份，以形成該絶緣隔層16a, 16b, 1 6 c S 1 6 d 0 現參照圖式2b,其中，示出依據本發明之較佳實施 例之下一處理步驟之一剖面示意圖。示出於圖式2 b者是 絶緣層18a, 18b及18c之出現例示在圖式2a之 半導體基底1 0之表面上。類似於絶緣隔層1 6 a, 1 6 b, 1 6 c及1 6 d形成之方法，其懍被例示於圔式2 a 中，該绝緣屬1 8 a , 1 8 b及1 8 c係由絶縐材料之一 第二覆蓋«上，該材料層偽被沉積於半導醱基底10之表 面上，並被作出圖案及經由一光罩加以，以獲得絶緣層1 -11 - (請先閲讀背面之注意Ϋ項再填寫本頁)XI Pack. &11; Selection of the size of the paper in line format China National Moumou (CNS) A4 specification (210X297 mm) Printed by the Central Bureau of Economics of the Ministry of Economic Affairs A7 _B7_ V. Description of invention (t) Phase deposition ( LPCVD) process to form, using silane as the silicon source material. The preferred thickness of the overlying silicon layer is approximately 1000 to 3500 Angstroms. Once, the covering compound silicon layer has been formed on the semiconductor substrate 10, which preferably makes the covering compound silicon layer guide, by implanting the genus with phosphorus-doped ions, per square centimeter Dosage 1 Ε 16 to about 1 Ε 16 ions and about 70 to 10 OKeV ion implantation energy "After ion implantation of the overlying silicon®, the overlying silicon layer image is patterned to become the overlying silicon layer 14a and 14b, it is preferable to etch the part of the compound silicon that passes through the mask mask by etching the photoresist covered with the compound silicon layer and etching with a reactive ion, and the treatment pseudo uses chlorine and bromine Argon gas is used as an etching gas composition. Once the multiple silicon layers 14a and 14b have been formed by covering the multiple silicon layer, the insulating spacer 16a is formed in the next step in the preferred embodiment of the present invention. 16b. 16c and 16d. These insulating spacers at the edges β of the complex silicon® 14a and 14 b are formed in a similar manner to the formation of the complex silicon layers 14 a and 14 b. More specifically, the insulating material of a cover layer is pseudo-formed on the surface of the semiconductor substrate 10 and the complex silicon layers 14a and 14b. The green material image of the cover layer is then etched without the appearance of a photomask, In order to leave the insulating partitions 16a, 16b, 16c and 16d, the edges of the rear silicon layers 14a and 14b are joined green. Several methods and materials can be formed from the cover layer to form the insulation barrier. These cover layers can be formed from materials including but not limited to vaporized silicon and silicon nitride. The method of forming the cover® from these materials includes but is not limited to -10 " This paper standard is widely used in the Chinese National Standard (CNS) Α4 specification (210X297mm) (please read the precautions on the back before filling this page) Line A7 B7 Printed by the Ministry of Economic Affairs, Central Bureau of Preservation and Consumer Cooperative Fifth, the description of the invention (7) is made by the chemical vapor phase precipitation (c VD) method and the plasma enhanced chemical vapor deposition (PECVD) method. These methods are typically anisotropic reactive ion etching (RIE) dry etching methods that use an etching gas suitable for the insulating material to be etched. For the preferred embodiment of the present invention, the insulating spacers igl 6 a, 16 b, 16 c and 16 d are preferably formed by covering a vaporized silicon material, and the insulating layer is formed on the The semiconductor substrate 10 and the multiple silicon layers 14 a and 14 b are processed by a low-pressure chemical vapor deposition (LPCVD) process using tetraethyl orthosilicate (TEOS) as a silicon-based material. The cover insulation 1 is preferably formed on the semiconductor substrate 10 to a thickness of about 100 to 250 angstroms. After the cover insulating layer is formed, the cover insulating layer is etched by an anisotropic reactive ion etching (RIE) dry etching process, using sulfonated tetrafluoride and trifluoromethane as etching gas components to form The insulating spacers 16a, 16b, 16 c S 16 d 0 will now refer to FIG. 2b, which shows a schematic cross-sectional view of the next processing step according to the preferred embodiment of the present invention. What is shown in FIG. 2b is that the appearance of the insulating layers 18a, 18b, and 18c is exemplified on the surface of the semiconductor substrate 10 in FIG. 2a. Similar to the method of forming insulating barriers 1 6 a, 1 6 b, 1 6 c and 16 d, it is exemplified in 圔 式 2 a, the insulation is 1 8 a, 1 8 b and 1 8 c It is covered by a second cover of one of the crepe materials. This material layer is pseudo deposited on the surface of the semiconductor substrate 10 and is patterned and applied through a photomask to obtain an insulating layer 1 -11-(please (Read the note Ϋ on the back before filling this page)
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I 裝. 訂 線 本纸張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） 五、發明説明（p) A7 B7 經濟部中央橾準局貝工消費合作杜印製 8 a 1 8 b 及 1 8 C 〇 覆 蓋 m » 其 傜 亦 形 成 绝 缠 8 者 ο 典 型 材 料 包 含 氣 化 對 於 本 發 明 之 較 佳 實 b 及 1 8 C 之 第 二 覆 畚 絶 形 成 * 在 半 導 體 基 底 1 0 沉 積 ( L P C Y D ) 處 理 大 約 4 0 0 0 至 1 5 0 0 氣 化 矽 材 料 % 被 加 以 作 出 光 罩 » 較 佳 地 經 由 — 反 程 9 使 用 四 氟 化 硪 及 三 氰 刻 處 理 所 得 的 是 絶 緣 1 1 層 1 8 a ί 1 8 b 及 1 8 0 埃 之 厚 度 > 相 等 於 第 二 由 圖 式 2 b 中 可 以 看 孔 徑 較 深 於 於 绝 緣 層 1 8 徑 間 之 深 度 上 之 差 異 係 導 止 > 用 於 絶 緣 層 1 8 b 及 8 a 及 1 8 b 間 之 孔 徑 傜 傜 被 反 應 離 子 蝕 刻 ( R I 該 處 理 於 絶 緣 層 1 8 a 及 * 其 中 並 沒 有 有 效 之 姓 刻 及 1 8 b 間 之 孔 徑 〇 典 型 其中有幾種材料俗可以形成第二 層 18a, 18b, 18c 及 1 矽及氮化矽。 施例，形成绝緣層18a,18 緣層者偽較佳地由一氣化矽材料 之表面上，藉由一低壓化學氣相 β第二覆蓋絶緣層僳較佳地形成 0埃厚。形成第二覆蓋绝緣層之 圖形，使用適當之光狙剤作為一 應離子蝕刻（RIE)乾蝕刻流 甲烷作為蝕刻氣體成份》由這独 8 a , 18b及18ce這绝線 c具有大約4000至1500 覆蓋绝緣喵所形成之厚度。 見於絶緣磨1 8a及1 8b間之 b及1 8 c間之孔徑，這些在孔 源於複矽層1 4 b作為一蝕刻擋 1 8 c間之孔徑β該於絶綠層1 形成在場氣化區域1 2 a上，其 E)蝕刻處理所迅速蝕刻，藉由 1 8 b間之孔徑係被形成。因此 檔止，用於形成於絶綠層18 a 地，此一孔徑於深度上係會被過 -1 2- (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ο Α7 經济部中央標隼局員工消费合作社印製 ____ Β7五、發明説明（γ) 度蝕刻，進入場氣化绝緣區域12a,大約500至10 0 0埃。 於絶緣層18 a及18 b間之孔褪像為睡界孔徑，用 以形成本發明較佳實施例之三度空間之複矽霣阻。較佳地 ，此一孔徑將會是4000至1 6000埃深，包含任何 遇度蝕刻進入一在該第二覆蓋氣化矽絶緣層下之基底層， 該孔徑傜被形成於其中。雖然，該孔徑可以以好幾種剖面 幾何形狀加以形成，包含但是並不限制於矩形，方形及圓 形，該孔徑較佳地偽具有一矩形之剖面具有一最小之剖面 大小大約為6000埃，以允許適當之複矽層随後地形成 入該孔徑中。 現參照圖式2 C,其中示出一示惠圖，其例示出一依 據本發明之較佳實施例之下一處理步费I。示於圖式2 c者 係一第二複矽層之出現在該半導醱基底1 〇之上。該第二 複矽層傜由一第二覆蓋複矽層所形成，其已經被作出圖案 並蝕刻，以保留剩下者接合第二後矽層2 0 a, 2 Ob及 2 0 c。第二複矽屬2 0 b傜形成部份地重合人绝緣層1 8 a及1 8 b間之孔徑》第二複矽層2 0 b包含本發明之 三度空間複矽電阻β該第二複矽層2 0 b被形成重合入於 絶緣11 8a及1 8b間之孔徑，對本發明而言偽重要的 。假若該第二複矽層2 0 b完全填滿這孔徑，該想要之高 霄阻待性將不會被本發明之三度空間複矽電阻所展現β 在絶緣層1 8 b及绝緣層1 8 c間孔徑之底部，第二 -1 3- (請先閲讀背面之注意事項再填寫本頁)-—I ·. I pack. The paper size of the binding book is applicable to the Chinese National Standard (CNS) A4 (210X297mm). V. Description of Invention (p) A7 B7 Central Bureau of Standardization, Ministry of Economic Affairs, Peking Consumer Cooperation Cooperation Duin 8 a 1 8 b and 1 8 C 〇cover m »Qiong also forms an entanglement 8 ο Typical materials include gasification for the present invention is better and b 2 8 颚 弚 blanket formation * in semiconductor Substrate 1 0 deposition (LPCYD) treatment is about 4 0 0 0 to 1 5 0 0% of the vaporized silicon material is made into a photomask »Preferably through-reverse 9 using tetrafluoride and tricyanide etching process is obtained Insulation 1 1 layer 1 8 a ί 1 8 b and 1 8 0 Angstrom thickness> Equivalent to the second from Figure 2 b can be seen that the aperture is deeper than the depth difference between the insulation layer 1 8 diameter Guidance> For the insulating layer 1 8 b and the aperture between 8 a and 18 b is etched by reactive ion etching (RI This treatment is applied to the insulating layer 1 8 a and * which does not The effective surname and the aperture between 1 8 b are typical. There are several materials that can form the second layer 18a, 18b, 18c and 1 silicon and silicon nitride. Example, those who form the insulating layer 18a, 18 edge layer The pseudo is preferably formed on the surface of a vaporized silicon material by a low-pressure chemical vapor β second covering insulating layer. The thickness of the second covering insulating layer is preferably 0 angstroms. The pattern of the second covering insulating layer is formed using appropriate light "As an ion etching (RIE) dry etching flow methane as an etching gas composition" by the insulation 8a, 18b and 18ce this insulation c has a thickness of about 4000 to 1500 covering the insulating cat. See the insulating mill 1 8a And the aperture between 18b and 18c. These holes originate from the complex silicon layer 14b as an etch stop. The aperture β between 18c is formed in the green layer 1 in the field gasification area 1 2 On the a, it is etched quickly by the E) etching process, and is formed by the aperture between 18 b. Therefore, the stop is used to form the 18a ground of the green layer. The depth of this aperture will be -1 2- (please read the precautions on the back and then fill out this page). The size of this paper is suitable for China National Standard (CNS) A4 specification (210X297 mm) ο Α7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economics ____ Β7 Fifth, the invention description (γ) degree etching, enter the field gasification insulation area 12a, about 500 to 10 0 0 Angstroms. The aperture between the insulating layers 18 a and 18 b is the sleeping aperture, which is used to form the three-dimensional complex silicon resist of the preferred embodiment of the present invention. Preferably, this pore size will be 4000 to 16000 Angstroms deep, including any chance to etch into a base layer under the second covering vaporized silicon insulating layer, in which the pore size is formed. Although the aperture can be formed in several cross-sectional geometries, including but not limited to rectangular, square, and circular, the aperture preferably has a rectangular cross-section with a minimum cross-sectional size of approximately 6000 angstroms. In order to allow an appropriate complex silicon layer to be subsequently formed into the aperture. Referring now to FIG. 2C, there is shown a benefit diagram, which illustrates a processing step I according to a preferred embodiment of the present invention. As shown in Figure 2c, a second complex silicon layer appears on the semiconductor substrate 10. The second multi-layer silicon layer is formed by a second overlying multi-layer silicon layer, which has been patterned and etched to retain the remainder after joining the second silicon layer 20a, 2Ob and 20c. The second multi-silicon layer 2 0 b is formed to partially overlap the aperture between the insulating layer 18 a and 18 b. The second multi-layer silicon layer 2 0 b includes the three-dimensional spatial multi-silicon resistor β of the present invention. The double silicon layer 2 0 b is formed to have an aperture overlapping between the insulation 11 8a and 18 b, which is pseudo-important for the present invention. If the second complex silicon layer 20 b completely fills the aperture, the desired high resistance will not be exhibited by the three-dimensional spatial complex silicon resistor of the present invention. The bottom of the aperture between layers 18 c, second -1 3- (please read the precautions on the back before filling this page)
J 装_ ,ιτ 本紙張尺度適用中國國家揉準（CNS ) Α4规格（210X297公釐） A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明ο 4 複矽層2 0 c形成一堆叠接觸點與該後矽層1 4 b。第二 後矽層2 0 a形成一連接元件，藉由該元件第二禊矽層2 〇 b俗連接至形成在半導體基底1 〇之積體霣路之其他部 份。 形成第二複矽® 2 0 a, 2 Ob及2 0c之第二覆蓋 複矽層偽被由一類似於使用以形成覆蓋複矽層之處理加以 形成，該處理偽形成複矽層1 4 a及1 4 b ^明白地説， 該形成在第二複矽12 0 a, 2 Ob及2 0 c上之第二覆 蓋複矽層僳形成在半導體基底10之上，藉由一低壓化學 氣相沉積（LPCVD)鼷理，使用矽烷作為矽源材料。 該第二覆蓋複矽層之較佳厚度，其相當於第二複矽層20 a, 20b及20c之厚度，僳由大約300至大約1〇 〇〇埃。於此一厚度，該形成本發明之複矽電阻之第二複 矽層2 0 b將佔據不到於绝绨層1 8 a及1 8 b間孔徑寬 度之百分之三+,該第二複矽12 Ob僳形成於其中。可 選擇地，該由第二複矽120a, 20b及20c所形成 之第二覆蓋複矽層可以以輕徹地摻雜摻雜劑種類，包含但 不限制於砷原子，硼原子及磷原子。 在第二覆蓋複矽層形成在該半導體基底10之後，其 係被作出圖案，以只保留下複矽層20 a, 20 b及20 ce在該第二覆蓋複矽層之作出圖案後，另一覆έ光阻« 偽被形成在半導醱基底10之表面上並作出圖案，以保留 下光阻層2 2，其傜覆蓋第二複矽層2 0 be —旦該第二 -14- (請先閱讀背面之注意事項再填寫本頁) b 裝 、·ιτ. 本紙張尺度逋用中國國家揉準（CNS ) Α4規格（210X297公釐） 經濟部中央樣準局負工消費合作社印製 A7 B7 五、發明説明（\ \ 複矽雇20b被覆蓋上光阻《22，該第二後矽120a 及2 0 c倦較佳地被作成導電，藉由高劑董之佈植以摻雜 離子》 以佈植以离削曇之摻雜離子來作成該複矽導18之處理 對於本技藉中者係為已知的。複矽可以被佈植以摻雜離子 包含但不限制於砷離子，硼離子及磷離子。對於本發明之 較佳實施例，第二複矽層2 0 a及2〇c傜藉由離子佈植 作成導雷，其偽使用磷摻雜離子，以1 E 1 4至1 E 1 6 離子每一平方公分之劑量.及大約於25至大約40Ke V離子佈植能量β此一離子佈植處理之結果，第二複矽層 2 0 a及2 0c形成導電端至第二複矽層20 b,第二複 矽層2 0 b形成本發明之三度空間電阻。 現參照圖式2d,其中示出一相當於圖式2c之剖面 圖之平面示意圖，在該光阻® 2 2已經被由半導艟基底1 0之表面移開後β如在圖式2d中所示，本發明之三度空 間電阻由第二複矽® 2 0 b所形成。接合第二複矽層2 0 b的是第二複矽12 0 a ,其提供一連接元件給本發明之 電阻所連接霣路之其他部份，及第二複矽Ji2〇c提供一 連接至下複矽層14b„ 在第二複矽層2 0 b内之孔徑2 4 b形成本發明之電 阻之三度空間部份，該電阻相較於本技藝之習用者為高。 在第二複矽層2 0 c内之孔徑2 4 c提供於本發明之高霣 咀值複矽電阻及下1複矽層1 4 b間之接點《>複矽層1 4 -15- 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 訂 經濟部中央標準局員工消费合作社印製 203950 g 五、發明説明（’〆） a及14b之直徑其在第二複矽120a, 20b及20 c下者傜如在虛線14a及14b所示。 〔實例1〕 在一半導體基底晶圔傜被形成一厚度3 5 0 0埃之場 氣化層時《該場氣化物傜形成一厚度大約5 0 0 0埃之覆 蓋層β該覆蓋層傜形成在該場氣化層上，藉由一低壓化學 氣相沉積（LPCVD)處理，其係使用矽烷作為矽源氣 體。該覆蓋複矽層係隨後被作出圆案，以獲得一序列之複 矽線在該場氣化物之表面上，該複矽線係大約為1微米寬 及長度約為100撤米。該複矽線傜然後被摻雜，藉由離 子佈植以磷離子以每平方公分3 Ε 1 5離子之離子佈植剤 量及大約3 OKeV離子佈植能量。最後，該半導體基底 晶圚具有摻雜複矽線於其表面上者偽被鈍化以一氣化矽絶 緣層，該絶緣庙傜被經由一電漿加強化學氣相沉積（PE CVD)處理加以形成，其係使用原矽酸四乙酯（TEO S)作為矽源材料及一藉由一化學氣相沉積（CVD)處 理所形成之摻雜玻璃绝緣層，該處理偽使用原矽酸四乙酯 (TEOS)及適當之硼及磷摻雜劑。該鈍化層具有開口 蝕刻貫穿於其間至該摻雜複矽線之相反端。個別線之電阻 值偽被加以量測。該置測得之電阻值像被對該複矽線之寬 度及長度正規化。該如此計算得之正規化電阻值像被報告 於表I。 〔實施2〕 -16- 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 A7 B7 五、發明説明（/^r —第二半導臞基底晶圓傜被以一類似於實例1中所描 述之半導醱基底晶囫之方式加以準備。明白地說，一厚度 3 5 0 0埃之場氣化層係被形成在該半導體基底晶画之表 面上。該場氣化物偽然後被形成一測試结構，其剖面傜相 當於圖式3 a中之剖面圖。 在圖式3 a中，其中示出該半導體基底30，在其上 傜形成塲氣化層3 2。在該場氣化層3 2上傜形成分立複 矽塾34a及34b,其在其邊緣具有絶緣隔層36a, 3 6b, 36c及36d。該複矽墊34a及34b傜大 約3 0 0 0埃厚及其具有約1徹米之寬度及大約1微米之 長度。該後矽墊H3 4 a及3 4 b僳藉由作出圈案及蝕刻 一在該場氣化層3 2表面上之層覆蓋摻雜磷複矽層加以形 成，其係葙由一低壓化學氣相沉積（LPCVD)處理， 其傺使用矽烷作為矽源材料。绝線隔層3 6 a, 3 6 b , 3 6 c及3 6 dm藉由一處理類似於本發明之較隹實施例 中所描述之處理加以形成。明白地說，該絶縐隔13 6 a ,36b, 36c及36d傜以未遮罩一绝绨材料覆蓋層 經濟部中央樣孳局員工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 蝕刻而加以形成，該絶線材料偽形成在場氣化層3 2及後 矽墊3 4a及3 4 b之表面上。該覆蓋層之絶緣材料在其 上該絶緣隔層形成者係藉由一低壓化學氣相沉積（LPC VD)處理，其倦使用原矽酸四乙酯（TEOS)作為矽 源材料。該覆蓋層之绝線材料换形成於大約2 0 0 〇埃之 厚度。 -17- 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作杜印製 A7 B7 五、發明説明（以） 在該場氣化層32,絶緣隔層36a, 36b, 36 c及36d,及複矽墊34a及34b之表面上镍然後形 成一覆蓋氣化層，其偽被作出圖形，以形成氣化層3 8 a ,38b及38d,藉由一低壓化皋氣相沉積（LPCV D)處理，使用原矽酸四乙酯（TEOS)作為矽源材料 β該覆蓋氣化層傜大約為5 0 0 0埃厚。然後，孔徑傜被 蝕刻穿過覆蓋氣化層，同時到達複矽134a及34b, 以及，形成氣化® 38a, 38b及38ce該孔徑具有 大約0. 6微米乘以0. 6撤米之尺寸具有一步階深度大 約5000埃，相當於形成在氣化層38a, 38b及3 8c之覆蓋氣化屬之厚度。一覆蓋複矽層40厚度大約5 00埃偽然後被形成在绝緣層38a, 38b及38c之 表面上，並且，進人一於接合絶線層以與複矽墊3 4 a及 3 4 b接觸之絶線層之間之孔徑中。 類似於實例1，該覆蓋複矽140傜被作圖案，以形 成一序列之大約1微米寬度之複矽線。該複矽線偽對準於 複矽墊3 4a及3 4b上。類似於實例1中，該複矽層線 偽被離子佈植以磷離子以大約3 E 1 5每平方公分離子之 劑量大約於3 OKeV離子佈植能董β於此一處理之此點 之半導體基底之一平面圖僳示於圈式3 be示於圖式3 b 的是一形成在複矽墊3 4 a及3 4 b上之後矽線40 a。 接點像被完成於複矽線4 0 a及複矽塾3 4 a及3 4 b之 間，分別藉由孔徑42a及42be • 1 8 _ (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 B7 五、發明説明（^))J 装 _, ιτ This paper scale is suitable for China National Standard (CNS) Α4 specification (210X297 mm) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of invention ο 4 Multiple silicon layers 2 0 c form a stack Contact point with the back silicon layer 14b. The second rear silicon layer 20a forms a connecting element, by which the second silicon layer 20b is commonly connected to other parts of the integrated circuit formed on the semiconductor substrate 10. The second overlying silicon layer forming the second multiple silicon® 2 0 a, 2 Ob and 2 0c is formed by a process similar to that used to form the overlying silicon layer, which pseudo-forms the multiple silicon layer 1 4 a And 1 4 b ^ Clearly, the second overlying silicon layers formed on the second complex silicon 12 0 a, 2 Ob and 2 0 c are formed on the semiconductor substrate 10 by a low-pressure chemical vapor Deposition (LPCVD) method, using silane as the silicon source material. The preferred thickness of the second overlying silicon layer is equivalent to the thickness of the second overlying silicon layers 20a, 20b, and 20c, and it ranges from about 300 to about 100 angstroms. At this thickness, the second multi-silicon layer 2 0 b forming the multi-silicon resistor of the present invention will occupy less than three percent of the aperture width between the insulation layer 18 a and 18 b +, the second Fusi 12 Obsu is formed in it. Alternatively, the second cover silicon layer formed by the second compound silicon 120a, 20b, and 20c can be lightly doped with dopant species, including but not limited to arsenic atoms, boron atoms, and phosphorus atoms. After the second overlying silicon layer is formed on the semiconductor substrate 10, it is patterned to retain only the underlayers 20a, 20b, and 20ce after the second overlying silicon layer is patterned, another A covering photoresist is formed on the surface of the semiconductor substrate 10 and is patterned to retain the lower photoresist layer 22, which covers the second complex silicon layer 2 0 be-once the second -14- (Please read the precautions on the back before filling in this page) b Pack, · ιτ. The paper size is printed by China National Standard (CNS) Α4 specification (210X297mm) Printed by the Consumer Labor Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (\ \ Fu Si Xian 20b is covered with photoresist "22, the second rear silicon 120a and 20 c are preferably made conductive, doped by high-density Dong Zhi implantation "Ions" The process of making the complex silicon guide 18 by implanting the doped ions from the epidermis is known to those in the art. The complex silicon can be implanted with doped ions including but not limited to arsenic Ions, boron ions, and phosphorus ions. For the preferred embodiment of the present invention, the second multiple silicon layers 20a and 20c are implanted by ions Cheng Guilei, which uses phosphorus-doped ions pseudo, with a dose of 1 E 1 4 to 1 E 1 6 ions per square centimeter. And about 25 to about 40Ke V ion implantation energy β this ion implantation treatment As a result, the second multiple silicon layers 20a and 20c form conductive ends to the second multiple silicon layer 20b, and the second multiple silicon layer 20b forms the three-dimensional spatial resistance of the present invention. Referring now to FIG. 2d, which shows A schematic plan view equivalent to the cross-sectional view of FIG. 2c is shown. After the photoresist® 2 2 has been removed from the surface of the semiconducting base 10, β is as shown in FIG. 2d. The space resistor is formed by the second multi-silicon® 2 0 b. Joining the second multi-silicon layer 20 b is the second multi-silicon 12 0 a, which provides a connecting element for other parts of the circuit connected by the resistor of the present invention And the second multi-layer silicon Ji2〇c provides a connection to the lower multi-layer silicon layer 14b. The aperture 2 4 b in the second multi-layer silicon layer 20 b forms a three-dimensional space part of the resistor of the present invention. Compared with those skilled in the art, the aperture 2 4 c in the second complex silicon layer 20 c provides a connection between the high-tip complex silicon resistor of the present invention and the lower complex silicon layer 14 b Click "> Multi-silicon layer 1 4 -15- This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) (Please read the notes on the back before filling this page) Binding employees of the Central Standards Bureau of the Ministry of Economic Affairs 203950 g printed by the consumer cooperative. V. Description of the invention ('〆) The diameters of a and 14b are shown in the dotted lines 14a and 14b under the second compound silicon 120a, 20b and 20c. [Example 1] In a semiconductor When the base crystal is formed into a field vaporization layer with a thickness of 3500 angstroms, the field vaporization layer forms a cover layer with a thickness of approximately 50000 angstroms. The cover layer is formed on the field vaporization layer. , By a low pressure chemical vapor deposition (LPCVD) process, which uses silane as a silicon source gas. The covering compound silicon layer was then rounded to obtain a sequence of compound silicon wires on the surface of the field vaporizer. The compound silicon wire is about 1 micrometer wide and about 100 meters in length. The multi-silicon wire was then doped by ion implantation with phosphorus ions at an ion implantation amount of 3 Ε 15 ions per square centimeter and about 3 OKeV ion implantation energy. Finally, the semiconductor substrate crystal has a doped complex silicon wire on its surface and is pseudo-passivated with a vaporized silicon insulation layer, the insulation layer is formed by a plasma enhanced chemical vapor deposition (PE CVD) process, It uses tetraethyl orthosilicate (TEO S) as the silicon source material and a doped glass insulating layer formed by a chemical vapor deposition (CVD) process, which uses pseudo ethyl orthosilicate (TEOS) and appropriate boron and phosphorus dopants. The passivation layer has an opening etched therethrough to the opposite end of the doped multi-silicon line. The resistance value of individual wires is pseudo-measured. The measured resistance value is normalized to the width and length of the complex silicon line. The normalized resistance value image thus calculated is reported in Table I. 〔Implementation 2〕 -16- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling out this page) Binding · Order A7 B7 5. Description of the invention (/ ^ r — The second semiconductor substrate wafer was prepared in a similar manner to the semiconductor substrate substrate described in Example 1. Clearly, a field gasification layer with a thickness of 3 500 angstroms Is formed on the surface of the semiconductor substrate crystal. The field vaporization is then formed into a test structure whose cross-section is equivalent to the cross-sectional view in Figure 3 a. In Figure 3 a, the semiconductor is shown The substrate 30 has a gasification layer 32 formed thereon. On the field gasification layer 32 there are formed discrete complex silicon bases 34a and 34b, which have insulating barriers 36a, 36b, 36c and 36d on their edges The complex silicon pads 34a and 34b are about 3,000 angstroms thick and have a width of about 1 metre and a length of about 1 micrometer. The rear silicon pads H3 4 a and 3 4 b are made by making a circle and Etching a layer on the surface of the field vaporization layer 32 covered with a doped phosphorus complex silicon layer is formed by a low pressure chemical vapor deposition (L PCVD) treatment, which uses silane as the silicon source material. The insulation barriers 3 6 a, 3 6 b, 3 6 c and 3 6 dm are treated by a treatment similar to the treatment described in the comparative embodiment of the invention It is clearly formed that the insulating crepe is printed with an unmasked insulating material covering 13 6 a, 36 b, 36 c and 36 d. It is printed by the Employees ’Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs (please read the notes on the back first (Fill in this page again) It is formed by etching, the insulation material is pseudo-formed on the surface of the field vaporization layer 32 and the rear silicon pads 3 4a and 3 4 b. The insulating material of the cover layer is on the insulation barrier The former was processed by a low pressure chemical vapor deposition (LPC VD), which used tetraethyl orthosilicate (TEOS) as the silicon source material. The insulation material of the cover layer was formed at about 200 angstroms. The thickness of the paper. -17- This paper scale is applicable to the Chinese National Standardization (CNS) A4 specification (210X297 mm). The Central Standards Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperation Co., Ltd. printed the A7 B7. V. Description of invention (in) Layer 32, insulating interlayers 36a, 36b, 36c and 36d, and compound silicon pads 34a and 34b are then formed on the surface of nickel Covering the vaporization layer, which is pseudo-patterned to form vaporization layers 38a, 38b, and 38d, is treated by a low-pressure vaporization vapor deposition (LPCV D) process, using tetraethyl orthosilicate (TEOS) as the The silicon source material β The cover gasification layer is about 5000 angstroms thick. Then, the pore size is etched through the cover gasification layer and reaches the complex silicon 134a and 34b, and, forming gasification ® 38a, 38b and The pore size of 38ce has a size of about 0.6 micrometers times 0.6 meters and has a step depth of about 5000 angstroms, which is equivalent to the thickness of the covering gasification layer formed in the gasification layers 38a, 38b and 38c. A covering silicon layer 40 with a thickness of about 500 Angstroms is then formed on the surfaces of the insulating layers 38a, 38b and 38c, and the insulating layer is joined to the silicon pads 3 4 a and 3 4 b In the aperture between the contacting insulation layers. Similar to Example 1, the overlying silicon complex 140 was patterned to form a sequence of complex silicon lines with a width of approximately 1 micron. The multiple silicon wires are pseudo-aligned on the multiple silicon pads 34a and 34b. Similar to Example 1, the multi-silicon layer wire is pseudo-implanted with phosphorus ions at a dose of about 3 E 1 5 per square male separator about 3 OKeV ion implanted energy semiconductors at this point in this treatment A plan view of one of the substrates shown in the circle 3 be shown in the pattern 3 b is a silicon wire 40 a formed on the complex silicon pads 3 4 a and 3 4 b. The contact image is completed between the double silicon wire 4 0 a and the double silicon wire 3 4 a and 3 4 b, respectively through the aperture 42a and 42be • 1 8 _ (please read the precautions on the back before filling this page) The size of the paper for binding and binding is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) A7 B7 5. Description of invention (^))
在一最後處理步驟中，該複矽線4 0 a偽被鈍化以一 氣化矽絶緣層，其儀由一電漿加強化學氣相沉稹（PEC VD)處理所形成，其傺使原矽酸四乙酷（TEOS)作 為矽源材料及一摻雜玻瑰絶緣層藉田一化學氣相沉積（C VD)處理加以形成，其傜使用原矽酸四乙醏（TEOS )作為矽源材料及適當之硼及磷摻雜劑。該諸鈍化《具有 被蝕刻之開孔貫穿於其間，以通過該摻雜複矽線4 Oat 相反端及接合摻雜複矽線其形成進入該三度空間测試結構 中。這些後矽線之罨阻價偽然後被藉由量測値別線之電阻 值及正規化對於個別線之長及寬之觀察II阻值而加以決定 β這些電阻值係被以此一方式計算者，俗被列於表Ιβ 表 I 實例 處理情況 電阻值 1 平面複矽靥 每平方206歐姆 2 三度空間複矽層 每平方1650歐姆 由表I之資料中，可以看見在幾乎等效處理條件下， 經濟部中央梯準局負工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 一依據於實例2中所描述之方法所形成之三度空間複矽轚 阻具有一實際上相較於一由實例1中之方法所形成之相當 大小尺寸之平面複矽電阻具有一較大之電狙值β此一較高 霣阻值係有用於半導體基底上，提供有限之表面區域給霄 阻結構。此一霣阻器亦提供一新頴方法，以改變在積饈霣 路内之電阻器之®阻值〇 -19- 本紙張尺度適用中困國家標準（CNS ) Α4規格（21〇X 297公釐）In a final processing step, the complex silicon wire 40 a is pseudo-passivated with a vaporized silicon insulating layer, the instrument is formed by a plasma enhanced chemical vapor deposition (PEC VD) treatment, and its original orthosilicate TEOS is used as a silicon source material and a doped glass rose insulation layer is formed by Tian-Chemical Vapor Deposition (C VD) treatment. Its TEOS uses tetraethyl orthosilicate (TEOS) as a silicon source material and Suitable boron and phosphorus dopants. The passivations "have etched openings penetrating therebetween to pass through the opposite end of the doped complex silicon wire 4 Oat and bond the doped complex silicon wire which is formed into the three-dimensional space test structure. The pseudo resistance value of these post-silicon wires is then determined by measuring the resistance value of the value line and normalizing the observed II resistance value for the length and width of the individual lines. These resistance values are calculated in this way In addition, the vulgarity is listed in Table Ιβ Table I Examples of processing conditions Resistance value 1 Plane complex silicon compound 206 ohms per square 2 Three-dimensional space complex silicon layer 1650 ohms per square From the data in Table I, it can be seen that in almost equivalent processing conditions Printed by the Ministry of Economic Affairs, Central Ladder and Accreditation Bureau Cooperative Consumer Cooperative (please read the precautions on the back before filling out this page). The three-dimensional space complex silicon block resistance formed according to the method described in Example 2 has a practical Compared with a planar complex silicon resistor of a relatively large size formed by the method in Example 1, the above has a larger electrical resistance value β. This higher resistance value is used on a semiconductor substrate to provide a limited surface area Give a small resistance structure. This resistor also provides a new method to change the resistance value of the resistor in the product road. The paper size is applicable to the national standard (CNS) Α4 specification (21〇X 297 Centigrade)