TW480740B - Light-emitting semiconductor device with reflective layer structure and method for making the same - Google Patents

Light-emitting semiconductor device with reflective layer structure and method for making the same Download PDF

Info

Publication number
TW480740B
TW480740B TW88117814A TW88117814A TW480740B TW 480740 B TW480740 B TW 480740B TW 88117814 A TW88117814 A TW 88117814A TW 88117814 A TW88117814 A TW 88117814A TW 480740 B TW480740 B TW 480740B
Authority
TW
Taiwan
Prior art keywords
layer
patent application
substrate
light
cladding layer
Prior art date
Application number
TW88117814A
Other languages
Chinese (zh)
Inventor
Shiang-Jiun Hung
Feng-Ren Jian
Mu-Ren Lai
Original Assignee
Uni Light Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Uni Light Technology Inc filed Critical Uni Light Technology Inc
Priority to TW88117814A priority Critical patent/TW480740B/en
Application granted granted Critical
Publication of TW480740B publication Critical patent/TW480740B/en

Links

Landscapes

  • Led Devices (AREA)

Abstract

The present invention mainly comprises producing a reflective layer on a light-emitting semiconductor stack structure; combining a second substrate on the reflective layer; removing the original substrate of the stack structure by a conventional method and using the second substrate as the substrate for the whole device. Since the reflective layer can effectively reflect all the light emitted from the semiconductor toward the substrate, the illumination efficiency of the surface-emitting type light-emitting semiconductor device can be increased. The present invention also modifies a light-emitting semiconductor device made from an insulative substrate into a vertical electrode structure, thereby effectively reducing the unit area in die production, and making it more convenient for the back end process of a conventional bonding encapsulation.

Description

480740 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(1 ) 發明領域: 本發明係關於發光半導體裝置及其製作方法,特別是關 於具有反射層結構之發光半導體裝置及其製作方法。 發明背景: 傳統使用會吸光之基板所製作的面射型發光二極體的结 構如圖1所示,首先在會吸光之基板20上成長一下披覆層 (cladding layer)21,接著在其上成長一活性層(active layer)22,然後在活性層上再成長一上披覆層 layer)23 ,如此便形成雙異質結構(d〇uble heterostriicture)。此一發光二極體之發光波長由活性層中 成份比例決定,披覆層能隙較活性層高,故一方面可以提 高載子的注入效率,另一方面由活性層所發出的光亦不會 被披覆層吸收,最後,在發光二極體的發光面上鍍上正面 金屬電極24,同時在基板20無成長磊晶層的一面上鍍上背 面金屬電極25。此種垂直式發光二極體因為使用了吸光基 板砷化鎵(GaAs),此基板可吸收波長介於57〇11111到65〇11111 的可見光,進而降低了發光效率。故如何降低吸光基板之 吸收效應為決定其發光效率的重要因素之一。 為了改善使用吸光基板所造成吸收可見光的缺點及增進 發光效率,習知技術發展出另一種結構如圖2所示,乃是增 加了電流阻隔區34及布拉格反射層33。在上披覆層23上成 長一同於披覆層但不同摻雜型的半導體電流阻隔區34,如 此可使電流散開的面積增加而改進發光效率;再者於吸光 基板20與下披覆層21之間加入布拉格反射層33使得往吸光 (請先閱讀背面之注意事項再填寫本頁) --------訂------- !華480740 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (1) Field of the invention: The present invention relates to a light-emitting semiconductor device and a manufacturing method thereof, and particularly to a light-emitting semiconductor device having a reflective layer structure and a manufacturing method thereof. Background of the Invention: The structure of a surface-emitting light-emitting diode traditionally made of a substrate that absorbs light is shown in FIG. An active layer 22 is grown, and then a cladding layer 23 is grown on the active layer, so as to form a dual heterostructure. The light-emitting wavelength of this light-emitting diode is determined by the proportion of components in the active layer. The energy gap of the coating layer is higher than that of the active layer. Therefore, on the one hand, the efficiency of carrier injection can be improved, and on the other hand, the light emitted by the active layer is not. It will be absorbed by the coating layer. Finally, the front metal electrode 24 is plated on the light emitting surface of the light emitting diode, and the back metal electrode 25 is plated on the side of the substrate 20 without the epitaxial layer. This type of vertical light-emitting diode uses gallium arsenide (GaAs), a light-absorbing substrate. This substrate can absorb visible light with a wavelength between 57101111 and 6501111, which reduces the luminous efficiency. Therefore, how to reduce the absorption effect of the light-absorbing substrate is one of the important factors determining its luminous efficiency. In order to improve the shortcomings of absorbing visible light caused by the use of a light-absorbing substrate and increase the luminous efficiency, another structure developed by the conventional technology is shown in FIG. Semiconductor current blocking regions 34 of different doping types are grown on the upper cladding layer 23 together with the cladding layer, so that the area where the current spreads can be increased and the luminous efficiency is improved; further, the light absorbing substrate 20 and the lower cladding layer 21 Add a Bragg reflective layer 33 between them to absorb light (please read the precautions on the back before filling this page) -------- Order -------!

480740 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(2) 基板入射的光能在此布拉格反射層3 3内被反射回來以提高 發光效率。然而,此種習知結構,一則需界定出電流阻隔 區的區域且使用兩次MOCVD磊晶,其具有製程複雜及時間 長的缺點;再則其布拉格反射層乃由兩個不同折射係數的 材料為一對(pair)重複交疊製作而成,此布拉格反射層反射 角頻寬乃由此對之折射係數差所決定,然而受限於組成材 料為化合物半導體’兩組成材料之間的折射係數差有限, 故只能對幾乎垂直入射的光才有反射的效果,其餘的光仍 通過此布拉格反射層而被基板吸收,所以其降低基板吸收 光的功效極為有限。 習知技術發展出另一種結構如圖3所示,其乃是先將發光 一極體異質結構36暴晶成長於暫時性的吸光基板2〇上,並 維持晶格相匹配(lattice match),完成後再將吸光基板2〇 去除’接下來使用晶片熱結合(Wafer bonding)的技術將 另一透光導電基板35與發光二極體異質結構36相結合,此 透光導電基板3 5不僅可增加電流散開的面積同時亦不吸收 自活性層所發出的光,故能增加其發光效率。此習知技術 中’使用晶片熱結合(Wafer bonding)的技術係將另一透 光導電基板35與發光二極體異質結構36相結合,此技術的 原理乃是利用不同材料之間的熱膨脹係數差,經由熱處理 而產生單軸壓力的推擠而使得透光導電基板35與發光二極 體異質結構36結合面之間產生原子與原子的凡德瓦力而键 結;故為了達到大面積的均勻性,需產生均勻的大面積單 軸壓力,如此不僅需特別設計熱結合機具且又需保持透光 J-----τ---i-----------1 訂-------竣 (i閱讀背面之注咅?事項再填寫本頁)480740 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (2) The light energy incident on the substrate is reflected back in this Bragg reflector 3 3 to improve the luminous efficiency. However, with this conventional structure, one needs to define the area of the current blocking area and use two MOCVD epitaxy, which has the disadvantages of complicated process and long time; and the Bragg reflector is made of two materials with different refractive indexes. It is made by repeatedly overlapping a pair of pairs. The reflection angle bandwidth of this Bragg reflector is determined by the difference of its refractive index. However, it is limited by the refractive index between the two materials. The difference is limited, so it can only reflect the light that is almost perpendicularly incident, and the remaining light is still absorbed by the substrate through this Bragg reflection layer, so its effect of reducing the light absorption by the substrate is extremely limited. As shown in FIG. 3, the conventional technology develops another structure, which is to first grow a light-emitting polar heterostructure 36 on a temporary light-absorbing substrate 20 and maintain a lattice match. After completion, the light-absorbing substrate 20 is removed. Next, another light-transmitting conductive substrate 35 and a light-emitting diode heterostructure 36 are combined using a wafer bonding technology. The light-transmitting conductive substrate 35 can not only Increasing the area where the current spreads out does not absorb light emitted from the active layer, so it can increase its luminous efficiency. In this conventional technique, the technique of “wafer bonding” is used to combine another transparent conductive substrate 35 with a light-emitting diode heterostructure 36. The principle of this technology is to use the coefficient of thermal expansion between different materials. Poorly, the uniaxial pressure is generated by heat treatment, which causes the atom-to-atom van der Waals force to be generated between the light-transmitting conductive substrate 35 and the light-emitting diode heterostructure 36 bonding surface; therefore, in order to achieve a large area Uniformity, it is necessary to generate uniform large-area uniaxial pressure, so not only need to specially design thermal bonding equipment, but also need to maintain light transmission J ----- τ --- i ----------- 1 Order ------- End (i read the note on the back? Matters and then fill out this page)

、發明說明( 經濟部智慧財產局員工消費合作社印製 導電基板3 5與發光二極體異質結構3 6之間的表面晶格方向 一致才能得到足夠強度的鍵結力及低阻抗的結合界面,故 此法在製作技術上較為複雜且困難度高,因此製作良率 易提高。 、 再者,習知技術中使用藍寶石(Sapphire)基板所製成之 氮化鎵系列之發光二極體,由於此基板係絕緣無法導電, 故須製成橫向電極的結構如圖4所示,包含一藍寶石絕緣基 板40,其上依序羞晶成長一緩衝層41,一 n型下披覆層ο ,一活化層43,一ρ型上披覆層44及一ρ型歐姆接觸層45, 接下製作正面電極46及橫向背面電極47。此外,習知技術 亦有使用碳化矽(Slllcon Carblde)當成氮化鎵系列之發光 —極體(基板,雖然碳化矽可以導電,可製作成垂直式電 極,但是此基板不易製作且成本亦相當高;故目前主要使 用絕緣基板來製成氮化物發光二極體裝置。由於使用絕緣 基板’無法製作成傳統式垂直電極結構,而須製成橫向電 極結構’如此不僅須特殊打線機構及封裝技術且晶粒之製 作面積相對地增加,導致製程複雜且每單位元件所需成本 亦增加。 综上可知,習知技術具有下列缺點·· 1.加電流阻隔區需兩次M0CVD磊晶之複雜製程,以 及布拉格反射層只能反射特定入射角的光。 2 ·晶片熱結合技術為了達到键結均勾性及低阻抗結合界 面所須之製程複雜及不易。 3·使用藍寶石(Sapphire)基板所製成之氮化鎵系列之發 if T ;-----------I訂 -------- (請先閲-tt背面之注意事項再填寫本頁)、、 Explanation of the invention (The consumer electronics cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the conductive substrate 35 and the light-emitting diode heterostructure 36 with the same surface lattice direction to obtain a sufficient strength of the bonding force and a low-resistance bonding interface. Therefore, this method is relatively complicated and difficult to manufacture, so it is easy to improve the production yield. Furthermore, the conventional technology uses a gallium nitride series light-emitting diode made of a sapphire (Sapphire) substrate. The substrate is not electrically conductive, so the structure of the lateral electrode must be made as shown in Figure 4. It includes a sapphire insulating substrate 40 on which a buffer layer 41, an n-type lower cladding layer are sequentially grown, and an activation layer. Layer 43, a p-type upper cladding layer 44 and a p-type ohmic contact layer 45, and then the front electrode 46 and the lateral back electrode 47 are made. In addition, the conventional technology also uses silicon carbide (Slllcon Carblde) as gallium nitride Series of light-emitting body (substrate, although silicon carbide can be conductive and can be made into vertical electrodes, but this substrate is not easy to make and the cost is also quite high; therefore, it is mainly made of insulating substrates. A nitride light-emitting diode device. Because the use of an insulating substrate 'cannot be made into a traditional vertical electrode structure, but must be made into a lateral electrode structure', so not only the special wiring mechanism and packaging technology, but also the relative increase in the production area of the die, As a result, the manufacturing process is complicated and the required cost per unit element is also increased. In summary, the conventional technology has the following disadvantages: 1. The complex process that requires two M0CVD epitaxies for the current blocking area, and the Bragg reflective layer can only reflect specific incidents. Corner light. 2 · Wafer thermal bonding technology is complex and difficult to achieve uniform bonding and low-resistance bonding interface. 3 · Sapphire substrate made of gallium nitride series if T ; ----------- I order -------- (Please read the notes on the back of -tt before filling in this page),

480740 A7480740 A7

五、發明說明(4 ) 經濟部智慧財產局員工消費合作社印製 光一極體,無法製作成垂直式電極的結構,而使得單位元 件成本增加。 發明概: 本發明之一目的在於克服使用吸光基板所造成降低發光 效率之缺點。 本發明之另一目的在於提供一種易於將一基板與一發光 半導體結構相結合之製程,以降低製程之複雜度及困難度 並大幅提昇反率。 本發明之又一目的在於簡化電流阻隔區之製程,以克服 習知製程複雜且時間長之缺點,並能有效提供分散電流之 功能以增進發光效率。 本發明之再一目的在於提供一種易於將具有橫向電極結 構之發光半導體裝置改製成具有垂直式電極結構之製程, 以便有效地降低晶粒製作之單位面積,並利於傳統的打線 封裝後段製程。 依據本發明之一種發光羊導體裝置,包括 一半導體堆疊結構,用以回應電流之導通而產生光; 一反射層,位於該半導體堆疊結構之一主要表面上,用 以反射產生自該堆疊結構且射向該反射層的光; 一厚層’位於該反射層之表面上,作用為一基板;以及 電極結構,用以施加電流至該半導體堆疊結構。 其中該反射層中可至少具有一個導電性較其他部分為差 之區域,作用為電流阻隔區。 此外,依據本發明之一種製造發光半導體裝置之方法, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 丨,-----τ —一—--------1 訂 i=-------線 (請先閱讀背面之注意事項再填寫本頁) 480740 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 包括下列步驟: 形成第一導電型之下披覆層於一第一基板上; 形成第二導電型之上披覆層鄰接於該下披覆層; 形成一歐姆接觸層於該上披覆層之上; 形成一反射層於該歐姆接觸層上; 將一第二基板結合於該反射層上; 移去該第一基板;以及 製作可分別導通至該上披覆層及該下披覆層之電極結構。 依據本發明之發光半導體裝置,其原本之吸光基板已於 製程中被去除,因此完全克服了因使用吸光基板所造成降 低發光效率之問題。此外,依據本發明之發光半導體裝置 具有一反射層,其可將發光半導體射向基板方向之光有效 地反射’故能提高面射型發光半導體裝置之發光效率。本 發明之反射層可包括單層或多層之金屬結構,該金屬層可 作為第二基板與發光半導體結構結合之介質,不僅可解決 習知 < 晶片直接熱結合之困難,且可大幅放寬對第二基板 材質之選擇。再者,依據本發明之發光半導體裝置可於製 作反射層時同時製作電流阻隔區,因此大幅簡化電流阻隔 區之製程。 此外,本發明所揭示之方法,可直接適用於將原本使用 絕緣基板之發光半導體裝置(如氮化物發光二極體)製作成具 有垂直電極之發光半導體裝置,不僅可有效地降低晶粒製 作之單位面積、利於傳統的打線封裝後段製程,並能以劈 裂(cleavage)方式分割,利於製作雷射二極體裝置。 J-----r —一—--------1 訂 i·-------竣 (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (4) The photodiode printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs cannot be made into a vertical electrode structure, which increases the unit element cost. Summary of the Invention: An object of the present invention is to overcome the disadvantage of reducing light emission efficiency caused by using a light-absorbing substrate. Another object of the present invention is to provide a manufacturing process that is easy to combine a substrate with a light-emitting semiconductor structure, so as to reduce the complexity and difficulty of the manufacturing process and greatly improve the reflectivity. Another object of the present invention is to simplify the manufacturing process of the current blocking area, so as to overcome the disadvantages of the complicated and long process of the conventional manufacturing process, and to effectively provide the function of dispersing current to improve the luminous efficiency. Another object of the present invention is to provide a process for easily transforming a light-emitting semiconductor device having a lateral electrode structure into a vertical electrode structure, so as to effectively reduce the unit area for die fabrication, and to facilitate the traditional post-package packaging process. A light-emitting sheep conductor device according to the present invention includes a semiconductor stacked structure for generating light in response to the conduction of current; a reflective layer on a major surface of the semiconductor stacked structure for reflecting generated from the stacked structure and The light directed toward the reflective layer; a thick layer 'on the surface of the reflective layer and acting as a substrate; and an electrode structure for applying a current to the semiconductor stack structure. The reflective layer may have at least one region having a lower conductivity than the other portions, and functions as a current blocking region. In addition, according to a method for manufacturing a light-emitting semiconductor device according to the present invention, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 丨, ----- τ-一 --------- --1 Order i = ------- line (please read the precautions on the back before filling this page) 480740 A7 B7 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (including the following steps: formation Forming a lower conductive layer of a first conductivity type on a first substrate; forming an upper coating layer of a second conductivity type adjacent to the lower coating layer; forming an ohmic contact layer on the upper coating layer; forming a A reflective layer is on the ohmic contact layer; a second substrate is bonded to the reflective layer; the first substrate is removed; and an electrode structure that can be respectively connected to the upper cladding layer and the lower cladding layer is made. In the light-emitting semiconductor device of the present invention, the original light-absorbing substrate has been removed in the manufacturing process, so the problem of reducing the light-emitting efficiency caused by the use of the light-absorbing substrate is completely overcome. In addition, the light-emitting semiconductor device according to the present invention has a reflective layer. Can light up half The light emitted from the body in the direction of the substrate is effectively reflected, so the light-emitting efficiency of the surface-emitting light-emitting semiconductor device can be improved. The reflective layer of the present invention may include a single-layer or multi-layer metal structure, and the metal layer can be used as the second substrate and the light-emitting semiconductor. The structure-bound medium can not only solve the conventional < difficulty in direct thermal bonding of the wafer, but also greatly relax the choice of the material of the second substrate. Furthermore, the light-emitting semiconductor device according to the present invention can simultaneously produce current when producing the reflective layer. The barrier region greatly simplifies the manufacturing process of the current barrier region. In addition, the method disclosed in the present invention can be directly applied to making a light-emitting semiconductor device (such as a nitride light-emitting diode) that originally uses an insulating substrate into a light-emitting device having a vertical electrode. The semiconductor device can not only effectively reduce the unit area of die production, facilitate the traditional post-wiring packaging back-end process, but also can be divided in a cleavage manner, which is conducive to the fabrication of laser diode devices. J ----- r — 一 —-------- 1 Order i · ------- End (Please read the precautions on the back before filling this page)

經濟部智慧財產局員工消費合作社印製 4 下披覆層 6 上披覆層 8 金屬反射層 1 1正面電極 480740 A7 B7 _ 五、發明說明(6 ) 本發明之技術内容及特點,可藉由下列之較佳實施例說 明配合圖式作更詳細的闡述。 圖式簡單說明: 圖1係習知的一種面射型發光二極體結構的剖面圖; 圖2係習知的另一種面射型發光二極體結構的剖面圖; 圖3係習知的又一種面射型發光二極體結構的剖面圖; 圖4係^知之使用絕緣基板製作之一種面射型發光二極體 結構的剖面圖; 圖5係實施本發明之一種面射型發光二極體結構的剖面圖; 圖6 a- 6g係實施本發明之一種面射型發光二極體製作流程 的示意圖; 圖7a-7d係實施本發明之另一種面射型發光二極體製作流 程的示意圖; 圖8a-8d係實施本發明之又一種面射型發光二極體製作流 程的示意圖; 圖9a-9e係實施本發明之一種使用絕緣基板製作發光二極 體製作流程的示意圖; 圖l〇a-10c係實施本發明的另一種使用絕緣基板製作發光 二極體製作流程的示意圖; E式代表符號.曰 1導電基板 5 活性層 7 歐姆接觸層 1 〇背面電極 本紙張尺度過用中國國家標準(CNS;W規格⑽x 297公爱)-----〜S一 — I- ^----τ — --------------- (請先閱讀背面之注意事項再填寫本頁) 480740 A7 _B7 五、發明說明(7 ) 經濟部智慧財產局員工消費合作社印製 20吸光基板 21下披覆層 22活性層 23上披覆層 24正面電極 25背面電極 33布拉格反射層 34電流阻隔區 35透光導電基板 36發光二極體異質結構 4 0絕緣基板 41緩衝層 42下披覆層 43活化層 44上披覆層 45歐姆接觸層 4 6正面電極 47背面電極 120 基板 12 1 下披覆層 122 活性層 123 上披覆層 124 歐姆接觸層 125 金屬反射層 126 導電基板 127 背面電極 128 正面電極 130 基板 131 下披覆層 132 活性層 133 上披覆層 134 歐姆接觸層 135 金屬反射層 136 導電基板 137 背面電極 13 8 正面電極 140 基板 141 下披覆層 142 活性層 143 上披覆層 14 4 歐姆接觸層 145 金屬反射層 146 導電基板 147 背面電極 148 正面電極 150 絕緣基板 151 緩衝層 152 下披覆層 -10 - I;-----Γ---,---衣--------訂 i=-------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 Lower coating layer 6 Upper coating layer 8 Metal reflective layer 1 1 Front electrode 480740 A7 B7 _ V. Description of the invention (6) The technical content and characteristics of the present invention can be obtained by The following description of the preferred embodiment is described in more detail with reference to the drawings. Brief description of the drawings: FIG. 1 is a cross-sectional view of a conventional surface-emitting light-emitting diode structure; FIG. 2 is a cross-sectional view of another conventional surface-emitting light-emitting diode structure; Another cross-sectional view of a surface-emitting light-emitting diode structure; FIG. 4 is a cross-sectional view of a surface-emitting light-emitting diode structure made of an insulating substrate; FIG. 5 is a surface-emitting light-emitting diode that implements the present invention Sectional view of the polar structure; Figures 6a-6g are schematic diagrams of the manufacturing process of a surface-emitting light-emitting diode implementing the present invention; Figures 7a-7d are the manufacturing process of another surface-emitting light-emitting diode implementing the present invention 8a-8d are schematic diagrams of a manufacturing process for implementing another surface-emitting light-emitting diode of the present invention; FIGS. 9a-9e are schematic diagrams of a manufacturing process for manufacturing a light-emitting diode using an insulating substrate according to the present invention; l〇a-10c is a schematic diagram of another embodiment of the light-emitting diode manufacturing process using an insulating substrate; the E-type representative symbol. 1 conductive substrate 5 active layer 7 ohmic contact layer 1 〇 back electrode This paper is over-scale China Home Standard (CNS; W size ⑽ x 297 public love) ----- ~ S- — I- ^ ---- τ — --------------- (Please read the back first Please pay attention to this page and fill in this page again) 480740 A7 _B7 V. Description of the invention (7) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy 20 Light absorbing substrate 21 Lower coating layer 22 Active layer 23 Upper coating layer 24 Front electrode 25 Back electrode 33 Bragg reflection layer 34 Current blocking area 35 Light-transmitting conductive substrate 36 Light-emitting diode heterostructure 4 0 Insulating substrate 41 Buffer layer 42 Under cladding layer 43 Activation layer 44 Over cladding layer 45 Ohm contact layer 4 6 Front electrode 47 Back Electrode 120 Substrate 12 1 Lower coating layer 122 Active layer 123 Upper coating layer 124 Ohmic contact layer 125 Metal reflective layer 126 Conductive substrate 127 Back electrode 128 Front electrode 130 Substrate 131 Lower coating layer 132 Active layer 133 Upper coating layer 134 Ohmic contact layer 135 metal reflective layer 136 conductive substrate 137 back electrode 13 8 front electrode 140 substrate 141 lower coating layer 142 active layer 143 upper coating layer 14 4 ohmic contact layer 145 metal reflection layer 146 conductive substrate 147 back electrode 148 front electrode Pole 150 Insulating substrate 151 Buffer layer 152 Under cladding layer -10-I; ----- Γ ---, --- clothing -------- order i = ------- line (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)

46U/4U 五、發明說明(8 153 155 157 159 160 162 164 20 1 167 活性層 歐姆接觸層 導電基板 正面電極 絕緣基板 下披覆層 上披覆層 金屬反射層 背面電極 較佳實施例說明 154 上披覆層 156 金屬反射層 158 背面電極 200 金屬蒸鍍圖案 161 緩衝層 163 活性層 165 歐姆接觸層 166 導電基板 168 正面電極 i·——— Ί!嗤 (請先閱讀背面之注意事項再填寫本頁) 依據本發明之-實施例製作之發光二極體具有如下的4 為結構與導電基板之間加入金J 流阻隔區,不須以兩次]VIOCV: 點: (1) 在發光二極體雙異 反射層之同時亦製作出電 磊晶製作電流阻隔區,降低製程複雜性及成本,由於入J 光只在金屬材料的表面穿透隨即被雙極子(dipole)所反射 所以金屬對光的入射角並無選擇性地反射,所以能增加2 射角頻寬,更有效地達到光的反射,而不易被基板吸收。 (2) 加金屬反射層於發光二極體雙異質結構與導電基未 之間,由於金屬與化合物半導體易形成合金化鍵結,故月 當作晶片結合之介質,較之晶片對晶片直接熱結合容易i 製作簡單。 (3 )加金屬反射層於使用絕緣基板所成長之氮化鎵系發 光二極體雙異質結構與另一導電基板之間,再將絕緣基板 -11 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1^ --------. 經濟部智慧財產局員工消費合作社印製 A746U / 4U V. Description of the invention (8 153 155 157 159 160 162 164 20 1 167 Active layer ohmic contact layer conductive substrate front electrode insulating substrate lower coating layer coating layer metal reflection layer back electrode preferred embodiment description 154 Coating layer 156 Metal reflective layer 158 Back electrode 200 Metal evaporation pattern 161 Buffer layer 163 Active layer 165 Ohmic contact layer 166 Conductive substrate 168 Front electrode i · ———— Ί! 嗤 (Please read the precautions on the back before filling in this Page) The light-emitting diode manufactured according to the embodiment of the present invention has the following 4 structure: a gold J-flow blocking area is added between the structure and the conductive substrate, and there is no need to double] VIOCV: points: (1) at the light-emitting diode At the same time, the body's double-differential reflection layer also produces electric epitaxy to make the current blocking area, which reduces the complexity and cost of the process. Since the incident J light only penetrates on the surface of the metal material and is then reflected by the dipole, the metal is opposite to the light The angle of incidence is not selectively reflected, so it can increase the bandwidth of the two angles of incidence, more effectively achieve light reflection, and not be easily absorbed by the substrate. (2) Add a metal reflective layer to the light-emitting diode double Between the solid structure and the conductive substrate, since metal and compound semiconductors easily form alloyed bonds, the moon is used as a medium for wafer bonding, which is easier than direct thermal bonding of the wafer to the wafer. (3) Adding a metal reflective layer Between the gallium nitride-based light-emitting diode double heterostructure grown using an insulating substrate and another conductive substrate, the insulating substrate is then used.-11-This paper size applies to China National Standard (CNS) A4 (210 X 297) %) 1 ^ --------. Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs

480740 五、發明說明(9 ) 除去如此可製作成垂直式電極結構之氮化鎵系發光二極體 ,有利於晶粒之打線及封裝作業,並可減小晶粒之製作面 積,故可降低成本。 圖5所7F為依據本發明之面射型發光二極體的架構,由下 而上,係於一導電基板i (conductive substra⑹,一金屬反射層 8 (metal reflection layer),一歐姆接觸層 7 (〇hmic c〇ntact iayer),一上 披覆層 6(cladding layer),一 活性層 5(actlve layer),一下披覆層 4 (cladding layer),最後再製作正面金屬電極n及背面金屬電 極10。 為了使本發明的特徵,方法及目的易於明瞭,茲配合較 佳之實施例詳述如下。 實施例一: 請參閱圖6a,在本發明之一實施例中,在第一個η型砷化 鎵(GaAs)基板120上依序磊晶成長一 ^型鋁鎵銦磷 (AlGalnP)下披覆層121,一AlGalnP活性層122係為習知 的組成結構,其可為單層量子井(SQW)或多層量子井 (MQW),一 P型AlGalnP上披覆層123,一 P型銦鎵轉 (InGaP)與P型GaAs組合而成之歐姆接觸層124。磊晶成長 完成後將部份P型歐姆接觸層124利用蝕刻技術移去,並暴 露出P型上披覆層123,如圖6b所示;接下來利用蒸鍍或賤 鍍的技術將一金屬反射層125鍍在P型歐姆接觸層124及P型 上披覆層123上,如圖6c所示;接下來將第二個p型導電基 板126以熱結合的方法與此金屬反射層125結合,完成後, 將第一個η型GaAs基板120移去,如圖6d所示;接下來再 -12 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -I. ^ τ — --------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 480740 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(10 ) 製作正面金屬電極128及背面金屬電極丨27如圖6 e所示。 此金屬反射層125能與P型歐姆接觸層124形成良好的歐 姆性接觸(Ohmic contact),卻與P型上披覆層123形成蕭 基性接觸(Schottky contact)。此金屬歐姆性接觸導電性 相奂向’除了可做為電流擴散路徑外,由於此金屬反射層 125對光的入射角並無選擇性地反射,所以能增加反射角頻 寬’故能更有效地將自活性層K2所發出的光反射,而金屬 蕭基性接觸導電性相對地較差,可當作電流阻隔區,但亦 可將自活性層122所發出的光反射。 圖6f所示為本實施例中輸入之電流在發光二極體中分佈 的情形。此加入之金屬反射層125能有效地將電流散開,以 提高發光效率。 凊參閱圖6 g ’可看出此加入之金屬反射層1 2 5如何將活性 層所發出的光反射而不被基板吸收,以提高發光效率。 實施例二: 請參閱圖7 a,在本發明另一實施例中,在第一個n型 GaAs基板130上依序磊晶成長一 ^型AlGalnP下披覆層13 1 ,一 AlGalnP活性層1 32係為習知的組成結構,其可為單層 f子井(SQW)或多層量子井(MQW),一 P型AlGalnP上披 覆層133,一 p型歐姆接觸層134。磊晶成長完成後,接下 來利用蒸鍍或錢鍍的技術將一金屬反射層135鍍在p型歐姆 接觸層134之上;接著如圖7b所示,再將部份金屬反射層 1 3 5以蚀刻技術移去,並暴露出p型歐姆接觸層丨3 4 ;接下 來如圖7c所示,將第二個p型導電基板136以熱結合的方法 13 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱 J ; ;-----------^訂 i:------- (請先閱讀背面之注意事項再填寫本頁) 480740 經濟部智慧財產局員工消費合作社印製 I.-----_----Γ-----------訂 i、-------MjlpH (請先閱讀背面之注咅?事項再填寫本頁} A7 B7 五、發明說明(11 ) 與此金屬反射層1 3 5結合’芫成後,將第一個η型GaAs基板 130移去;最後,如圖7d所示,再製作正面金屬電極138及 背面金屬電極1 3 7。 此金屬反射層135能與P型歐姆接觸層134形成良好的歐 姆性接觸(Ohmic contact),此金屬歐姆性接觸的功能同實 施例一中所描述,而暴露出之P型歐姆接觸層134與第二個 P型導電基板1 3 6之間之空隙則當作電流阻隔區,而且由於 AlGalnP上披覆層133之折射係數n(refracti〇I1 index)約 為3·5,而P型歐姆接觸層134與第二個p型導電基板136之 間之空隙的折射係數n(refraction index)約等於1,所以 自活性層132所發出的光進入p型歐姆接觸層134與第二個p 型導電基板1 3 6之間之空隙時,光係從密介質到疏介質,所 以此空隙亦能將光反射回來。 本實施例之電流分佈及自活性層所發出的光之反射情形 同實施例一。 實施例三: 請參閱圖8a,在本實施例中,在第一個η型GaAs基板 140上’依序磊晶成長一 ^型AlGalnP下披覆層141,一 AlGalnP活性層142係為習知的組成結構,其可為單層量子 井(SQW)或多層量子井(MQW),一 P型AlGalnP上披覆層 143,一 P型歐姆接觸層144。磊晶成長完成後,接下來利 用蒸鍍或濺鍍的技術將一金屬反射層i 4 5鍍在第二個p型導 電基板146上,再將部份金屬反射層145移去,暴露出第二 個P型導電基板146,如圖8b所示;接下來以熱結合的方法 -14 - 本紙張尺度適用中國國家標準(CNS)A4規格(21G X 297公釐) '—-—- 480740 經濟部智慧財產局員工消費合作社印製 A7 ______B7____ 五、發明說明(12 ) 將此金屬反射層145與歐姆接觸層144結合,完成後,將第 一個η型GaAs基板140移去,如圖8c所示;最後,再製作 正面金屬電極148及背面金屬電極147,如圖8d所示。 此金屬反射層145能與P型歐姆接觸層144形成良好的歐 姆性接觸(Ohmic contact),此金屬歐姆性接觸及暴露出之 第二個P型導電基板146與歐姆接觸層144之間的空隙之功 能與實施例二中所描述相同。 本實施例之電流分饰及自活性層所發出的光之反射情形 同實施例一。 實施例四: 請參閱圖9 a,在本實施例中,在第一個藍寶石絕緣基板 150上依序暴晶成長一 η型氮化鎵(GaN)緩衝層151,一 η型 氮化鋁鎵(AlGaN)下披覆層152,一氮化錮鎵(inGaN)活性 層153係為習知的組成結構,其可為單層量子井(SqW)或多 層量子井(MQW),一 P型氮化鋁鎵(AlGaN)上披覆層154 ,一 P型氮化鎵(GaN)歐姆接觸層155。磊晶成長完成後將 部份P型歐姆接觸層155利用光罩蝕刻的技術製作出金屬蒸 鍍圖案(pattern)200,如圖9b所示。接下來利用蒸鍍或濺 鍍的技術將一金屬反射層156鍍在P型歐姆接觸層155金屬 蒸鍍圖案200之上,如圖9c所示。接下來將第二個p型導電 基板157以熱結合的方法與此金屬反射層156結合,完成後 ,將第一個藍寶石絕緣基板150移去,如圖9d所示。最後, 再製作正面金屬電極159及背面金屬電極158,如此即可製 作出垂直式電極之氮化鎵系發光二極體,如圖9e所示。 -15 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -- (請先閱讀背面之注音?事項再填寫本頁) ---------訂---------. 480740 經濟部智慧財產局員工消費合作社印製 A7 ______Bl 五、發明說明(13 ) 此金屬反射層156能與P型歐姆接觸層155形成良好的歐 姆性接觸(Ohmic contact),此金屬歐姆性接觸155及第二 個P型導電基板157與歐姆接觸層155之間暴露出之空隙之 功能與實施例二中所描述相同。 本實施例之電流分佈及自活性層所發出的光之反射情形 同實施例一。 實施例五: 一 請參閱圖1 0 a,在本實施例中,在第一個藍寶石絕緣基板 160上依序嘉晶成長一 η型GaN缓衝層161,一η型AlGaN下 披覆層162,一 InGaN活性層163係為習知的组成結構,其 可為單層量子井(SQW)或多層量子井(MQW),一 P型 AlGaN上披覆層164,一 P型GaN歐姆接觸層165。 磊晶成長完成後,接下來利用蒸鍍或濺鍍的技術將一金 屬反射層201圖案鍍在第二個p型導電基板166上,接下來 將以熱結合的方法將此金屬反射層2 0 1與歐姆接觸層1 6 5結 合,如圖1 Ob所示。完成後,將第一個藍寶石絕緣基板1 60 移去,接下來再製作正面金屬電極168及背面金屬電極167 如此即可製作出垂直式電極之氮化鎵系發光二極體,如圖 10c所示。 此金屬反射層201能與P型歐姆接觸層165形成良好的歐 姆性接觸(Ohmic contact),此金屬歐姆性接觸及暴露出之 第二個P型導電基板166與歐姆接觸層165之間的空隙之功 能與實施例四中所描述相同。 本實施例之電流分佈及自活性層所發出的光之反射情形 -16 - 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) I >-----_—;—--------訂 i=-------竣 (請先閱讀背面之注意事項再填寫本頁) A7480740 V. Description of the invention (9) Excluding the gallium nitride light emitting diode which can be made into a vertical electrode structure in this way, it is conducive to the wiring and packaging of the die, and it can reduce the production area of the die, so it can reduce cost. 7F in FIG. 5 is a structure of a surface-emission type light emitting diode according to the present invention. The bottom-up structure is connected to a conductive substrate i (conductive substra⑹), a metal reflection layer 8 and an ohmic contact layer 7. (〇hmic c〇ntact iayer), a cladding layer 6 (acting layer), an active layer 5 (actlve layer), a cladding layer 4 (cladding layer), and finally a front metal electrode n and a back metal electrode 10. In order to make the features, methods, and objectives of the present invention easy to understand, the preferred embodiments are described in detail below. Embodiment 1: Refer to FIG. 6a. In one embodiment of the present invention, the first n-type arsenic A gallium (GaAs) substrate 120 is sequentially epitaxially grown to form a ^ -type aluminum gallium indium phosphorus (AlGalnP) lower cladding layer 121, and an AlGalnP active layer 122 is a conventional composition structure, which may be a single-layer quantum well ( SQW) or multilayer quantum wells (MQW), a P-type AlGalnP cladding layer 123, an ohmic contact layer 124 composed of a P-type indium gallium transition (InGaP) and a P-type GaAs. After the epitaxial growth is completed, some The P-type ohmic contact layer 124 is removed by using an etching technique, and the P-type upper cladding is exposed. Layer 123, as shown in FIG. 6b; next, a metal reflective layer 125 is plated on the P-type ohmic contact layer 124 and the P-type upper cladding layer 123 by using evaporation or base plating technology, as shown in FIG. 6c; Next, the second p-type conductive substrate 126 is thermally bonded to this metal reflective layer 125. After the completion, the first n-type GaAs substrate 120 is removed, as shown in FIG. 6d; This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -I. ^ Τ — --------------- (Please read the precautions on the back before filling (This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 480740 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 V. Description of the invention (10) The front metal electrode 128 and the back metal electrode 丨 27 are shown in Figure 6e. The metal reflective layer 125 can form a good ohmic contact with the P-type ohmic contact layer 124, but forms a Schottky contact with the P-type upper cladding layer 123. The metal ohmic contact is conductive The opposite direction can be used as a current diffusion path, because the metal reflective layer 125 The incident angle of light is not selectively reflected, so the reflection angle bandwidth can be increased, so that the light emitted from the active layer K2 can be reflected more effectively. The metal-based contact is relatively poor in conductivity and can be regarded as The current blocking region, but the light emitted from the active layer 122 can also be reflected. Fig. 6f shows the distribution of the input current in the light emitting diode in this embodiment. The added metal reflective layer 125 can effectively spread the current to improve the luminous efficiency.凊 Refer to FIG. 6 g ′, it can be seen how the added metal reflective layer 1 2 5 reflects the light emitted by the active layer without being absorbed by the substrate, so as to improve the luminous efficiency. Second Embodiment: Please refer to FIG. 7 a. In another embodiment of the present invention, a first-type AlGalnP lower cladding layer 13 1 and an AlGalnP active layer 1 are epitaxially grown on the first n-type GaAs substrate 130 in order. The 32 series is a conventional composition structure, which may be a single-layer f-well (SQW) or a multilayer quantum well (MQW), a P-type AlGalnP coating layer 133, and a p-type ohmic contact layer 134. After the epitaxial growth is completed, a metal reflective layer 135 is then plated on the p-type ohmic contact layer 134 by evaporation or coin plating; then as shown in FIG. 7b, a part of the metal reflective layer is 1 3 5 It is removed by an etching technique, and the p-type ohmic contact layer is exposed. 3 4; Next, as shown in FIG. 7 c, the second p-type conductive substrate 136 is thermally bonded. 13-This paper size applies Chinese national standards ( CNS) A4 Specification (210 X 297 Public Love J;; ----------- ^ Order i: ------- (Please read the precautions on the back before filling this page) 480740 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau I .-----_---- Γ ----------- Order i, ------- MjlpH (Please read the Note 咅? Please fill in this page again} A7 B7 V. Description of the invention (11) After combining with this metal reflective layer 1 3 5, the first n-type GaAs substrate 130 is removed; finally, as shown in Figure 7d Then, the front metal electrode 138 and the back metal electrode 1 3 7 are fabricated. The metal reflective layer 135 can form a good ohmic contact with the P-type ohmic contact layer 134, and the function of the metal ohmic contact is the same as in the embodiment. As described in the above description, the gap between the exposed P-type ohmic contact layer 134 and the second P-type conductive substrate 136 is used as a current blocking area, and the refractive index n (refracti) of the coating layer 133 on AlGalnP 〇I1 index) is about 3.5, and the refractive index n (refraction index) of the gap between the P-type ohmic contact layer 134 and the second p-type conductive substrate 136 is approximately equal to 1, so the emission from the active layer 132 When light enters the gap between the p-type ohmic contact layer 134 and the second p-type conductive substrate 136, the light is from a dense medium to a sparse medium, so this gap can also reflect light back. Current distribution in this embodiment The reflection of the light emitted from the active layer is the same as that of the first embodiment. Third embodiment: Please refer to FIG. 8a. In this embodiment, the first n-type GaAs substrate 140 is sequentially epitaxially grown into a ^ -type. AlGalnP lower cladding layer 141, an AlGalnP active layer 142 is a conventional composition structure, which may be a single-layer quantum well (SQW) or multi-layer quantum well (MQW), a P-type AlGalnP upper cladding layer 143, a P Ohmic contact layer 144. After epitaxial growth is completed, A metal reflective layer i 4 5 is plated on the second p-type conductive substrate 146, and a part of the metal reflective layer 145 is removed to expose the second p-type conductive substrate 146, as shown in FIG. 8b; Come down by thermal method -14-This paper size applies Chinese National Standard (CNS) A4 specification (21G X 297 mm) '—-—- 480740 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______B7____ 5. Description of the invention (12) Combine this metal reflective layer 145 with the ohmic contact layer 144, and after the completion, remove the first n-type GaAs substrate 140, as shown in FIG. 8c; finally, make the front metal electrode 148 and the back metal electrode 147 , As shown in Figure 8d. The metal reflective layer 145 can form a good ohmic contact with the P-type ohmic contact layer 144. The metal ohmic contact and the gap between the exposed second P-type conductive substrate 146 and the ohmic contact layer 144 The function is the same as that described in the second embodiment. The current distribution and reflection of light emitted from the active layer in this embodiment are the same as those in the first embodiment. Embodiment 4: Please refer to FIG. 9 a. In this embodiment, an n-type gallium nitride (GaN) buffer layer 151 and an n-type aluminum gallium nitride are sequentially grown on the first sapphire insulating substrate 150. (AlGaN) lower cladding layer 152, a gallium gallium nitride (inGaN) active layer 153 is a conventional composition structure, which may be a single-layer quantum well (SqW) or a multilayer quantum well (MQW), a P-type nitrogen An overcoat layer 154 of aluminum gallium (AlGaN) and an ohmic contact layer 155 of p-type gallium nitride (GaN). After the epitaxial growth is completed, a part of the P-type ohmic contact layer 155 is fabricated with a mask etching technique to produce a metal evaporation pattern 200, as shown in FIG. 9b. Next, a metal reflection layer 156 is plated on the metal evaporation pattern 200 of the P-type ohmic contact layer 155 by using a vapor deposition or sputtering technique, as shown in FIG. 9c. Next, the second p-type conductive substrate 157 is thermally bonded to this metal reflective layer 156. After completion, the first sapphire insulating substrate 150 is removed, as shown in FIG. 9d. Finally, the front metal electrode 159 and the back metal electrode 158 are fabricated, so that a gallium nitride-based light emitting diode with a vertical electrode can be fabricated, as shown in FIG. 9e. -15-This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)-(Please read the note on the back? Matters before filling out this page) --------- Order-- -------. 480740 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______Bl V. Description of the invention (13) The metal reflective layer 156 can form a good ohmic contact with the P-type ohmic contact layer 155 (Ohmic contact ), The functions of the metal ohmic contact 155 and the gaps exposed between the second P-type conductive substrate 157 and the ohmic contact layer 155 are the same as described in the second embodiment. The current distribution and the reflection of light emitted from the active layer in this embodiment are the same as those in the first embodiment. Embodiment 5: Please refer to FIG. 10A. In this embodiment, an n-type GaN buffer layer 161 and an n-type AlGaN lower cladding layer 162 are sequentially grown on the first sapphire insulating substrate 160. An InGaN active layer 163 is a conventional composition structure, which may be a single-layer quantum well (SQW) or a multilayer quantum well (MQW), a P-type AlGaN cladding layer 164, and a P-type GaN ohmic contact layer 165. . After the epitaxial growth is completed, a metal reflective layer 201 is patterned on the second p-type conductive substrate 166 by evaporation or sputtering. Next, the metal reflective layer is thermally bonded. 1 is combined with the ohmic contact layer 165, as shown in Fig. 1 Ob. After completion, remove the first sapphire insulating substrate 1 60, and then fabricate the front metal electrode 168 and the back metal electrode 167, so that a gallium nitride-based light emitting diode with a vertical electrode can be fabricated, as shown in FIG. 10c. Show. The metal reflective layer 201 can form a good ohmic contact with the P-type ohmic contact layer 165. The metal ohmic contact and the gap between the exposed second P-type conductive substrate 166 and the ohmic contact layer 165 The function is the same as that described in the fourth embodiment. Current distribution of this example and reflection of light emitted from the active layer -16-This paper size applies the Chinese National Standard (CNS) A4 specification (21 × X 297 mm) I >-----_-; -------- Order i = ------- End (Please read the precautions on the back before filling this page) A7

480740 五、發明說明(14 ) 同實施例一。 本發明之實施例中之反射層可以是鈦(Ti)、鋁(A1)或金 (Au)等之單層結構或金/鍺(Au/Ge)、鈦/鋁(Ti/Ai)或鎳/金 (Ni/Au)等之多層結構。 本發明之實施例中之第二基板之材質可為鍺(Ge)、矽 (Si)或磷化鎵(GaP)、磷化錮(Inp)等任何組成之化合物半 導體,亦可為如氧化銦錫(IT〇)、氧化鋅(Zn〇)等導電型氧 化物。 本發明之其他實施例之發光半導體裝置可以不包含活化 層’而由上披覆層及下披覆層間之介面發光。 本發明之其他實施例中的電流阻隔區之組成可以是絕緣 氧化物或絕緣氮化物。 本發明之不同實施例中的電極結構亦可視需要而製作成 橫向式電極結構。 本發明之特點及技術内容已充分揭示如上,任何熟於本 項技藝之士可依據本發明之揭示及教示而作各種不背離本 發明精神之替換或修飾,因此本發明之保護範圍不應限於 所揭示之實施例,而應涵蓋這些替換及修飾。 -I.----^----:----------訂·.I------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規公釐_)_480740 V. Description of the invention (14) Same as the first embodiment. The reflective layer in the embodiment of the present invention may be a single-layer structure such as titanium (Ti), aluminum (A1), or gold (Au), or gold / germanium (Au / Ge), titanium / aluminum (Ti / Ai), or nickel. / Gold (Ni / Au) and other multilayer structures. The material of the second substrate in the embodiment of the present invention may be a compound semiconductor of any composition such as germanium (Ge), silicon (Si), gallium phosphide (GaP), gadolinium phosphide (Inp), or indium oxide. Conductive oxides such as tin (IT0) and zinc oxide (Zn〇). The light emitting semiconductor device according to another embodiment of the present invention may not include an activation layer 'but emit light through an interface between the upper cladding layer and the lower cladding layer. The composition of the current blocking region in other embodiments of the present invention may be an insulating oxide or an insulating nitride. The electrode structure in different embodiments of the present invention can also be made into a lateral electrode structure according to need. The features and technical contents of the present invention have been fully disclosed as above. Any person skilled in the art can make various substitutions or modifications without departing from the spirit of the present invention in accordance with the disclosure and teachings of the present invention. Therefore, the protection scope of the present invention should not be limited to The disclosed embodiments should cover these substitutions and modifications. -I .---- ^ ----: ---------- Order · .I ------- (Please read the notes on the back before filling out this page) Ministry of Economy Wisdom The paper size printed by the Employees' Cooperative of the Property Bureau applies the Chinese National Standard (CNS) A4 mm__

Claims (1)

ABCDABCD 第88117814號專利申請案 中文申請專利範圍修正本(91年1月) 六、申請專利範圍 1 . 一種發光半導體裝置,包括 一半導體堆疊結構,用以回應電流之導通而產生光; 一反射層,位於該半導體堆疊結構之一主要表面上,用 以反射產生自該堆疊結構且射向該反射層的光; 一厚層,位於該反射層之表面上,作用為一基板;以及 電極結構,用以施加電流至該半導體堆疊結構。 2.如申請專利範圍第1項之裝置,其中該反射層中至少具 有一個導電性較其他部分為差之區域,作用為電流阻隔 區。 3 ·如申請專利範圍第2項之裝置,其中該電流阻隔區可為 絕緣氧化物、絕緣氮化物、空氣或蕭基性接觸區。 4 ·如申請專利範圍第1或2項之裝置,其中該反射層可以 是欽(Ti)、鋁(A1)或金(Au)等之單層結構或金/鍺 (Au/Ge)、鈦/鋁(Ti/Al)或鎳/金(Ni/Au)等之多層結構。 5 ·如申請專利範圍第1或2項之裝置,其中該半導體堆疊 結構包括: 一下披覆層,該下披覆層中摻入第一導電型雜質; 一上披覆層,該上披覆層中摻入第二導電型雜質且鄰接 於該下披覆層;以及 歐姆接觸層,形成於該上披覆層之上。 6. 如申請專利範圍第5項之裝置,其中該半導體堆疊結構 更包括: 一活性層,界於該下披覆層與該上披覆層之間。 7. 如申請專利範圍第5項之裝置,其中該下披覆層為一 n 480740Patent application No. 88117814 Chinese amendment to the scope of patent application (January 91) 6. Scope of patent application 1. A light-emitting semiconductor device including a semiconductor stack structure for generating light in response to the conduction of current; a reflective layer, Located on one of the major surfaces of the semiconductor stack structure to reflect light generated from the stack structure and directed to the reflective layer; a thick layer located on the surface of the reflective layer and serving as a substrate; and an electrode structure for To apply a current to the semiconductor stack structure. 2. The device according to item 1 of the scope of patent application, wherein the reflective layer has at least one region having a lower conductivity than the other portions, and functions as a current blocking region. 3. The device according to item 2 of the patent application range, wherein the current blocking region may be an insulating oxide, an insulating nitride, air, or a Schottky contact region. 4. The device according to item 1 or 2 of the scope of patent application, wherein the reflective layer may be a single-layer structure such as Ti (Ti), aluminum (A1) or gold (Au), or gold / germanium (Au / Ge), titanium / Aluminum (Ti / Al) or nickel / gold (Ni / Au) multilayer structure. 5. The device according to item 1 or 2 of the patent application scope, wherein the semiconductor stack structure includes: a lower cladding layer, which is doped with a first conductivity type impurity; an upper cladding layer, the upper cladding A second conductive type impurity is doped in the layer and is adjacent to the lower cladding layer; and an ohmic contact layer is formed on the upper cladding layer. 6. The device as claimed in claim 5, wherein the semiconductor stack structure further includes: an active layer bounded between the lower cladding layer and the upper cladding layer. 7. For the device in the scope of application for patent item 5, wherein the lower coating layer is a n 480740 型之銘鎵銦磷(AlGalnP)半導體層,而該上披覆層為 一 P型之鋁鎵銦磷(AlGalnP)半導體層。 8-如申請專利範圍第5項之裝置,其中該下披覆層為—n 型之氮化鎵皿-V族化合物半導體層,而該上披覆層為 一 ρ型之氮化鎵m-v族化合物半導體層。 9.如申請專利範圍第1或2項之裝置,其中該厚層之材質 可為鍺(Ge)、矽(Si)或磷化鎵(GaP)、磷化銦(Inp)等 任何組成之化合物半導體,亦可為如氧化銦錫(IT〇)、 氧化鋅(ΖηΟ)等導電型氧化物。 如申請專利範圍第1或2項之裝置,其中該電極結構包 含兩個電極分別位於該厚層之表面及該堆疊結構相對於 該主要表面之另一表面上。 11· 一種製造發光半導體裝置之方法,包括下列步驟: 形成第一導電型之下披覆層於一第一基板上; 形成第二導電型之上披覆層鄰接於該下披覆層; 形成一歐姆接觸層於該上披覆層之上; 形成一反射層於該歐姆接觸層上; 將一第二基板結合於該反射層上; 移去該第一基板;以及 製作可分別導通至該上披覆層及該下披覆層之電極結構。 1 2 .如申請專利範圍第11項之方法,其中於形成該下披覆層 之前,該第一基板上已形成有一第一導電型之緩衝層, 而該下披覆層係形成於該緩衝層之上。 1 3 ·如申請專利範圍第1 2項之方法,其中該下披覆層為一 η 本纸張尺度適用中國國家標準(cns) Α4規格(21〇 χ 公董) 480740 A8 B8 C8 D8 六、申請專利範圍 型之氮化鎵Π-V族化合物半導體層,而該上披覆層為 一 Ρ型之氮化鎵瓜-V族化合物半導體層。 1 4 ·如申請專利範圍第11或1 2項之方法,其中於形成該上 披覆層之前,更包括形成一活性層於該下披覆層之上之 步驟,使該活性層界於該下披覆層與該上披覆層之間。 1 5 ·如申請專利範圍第1 1或i 2項之方法,其中該反射層中 至少具有一個導電性較其他部分為差之區域,作用為電流 阻隔區。 1 6 .如申請專利範圍第丨5項之方法,其中該電流阻隔區可為 絕緣氧化物、絕緣氮化物、空氣或蕭基性接觸區。 1 7 ·如申請專利範圍第1 1或丨2項之方法,其中該反射層可 以是钦(Ti)、鋁(A1)或金(Au)等之單層結構或金/鍺 (Au/Ge)、鈦/鋁(Ti/Al)或鎳/金(Ni/Au)等之多層結 構。 1 8 ·如申請專利範圍第丨丨項之方法,其中該下披覆層為一 n 型之銘鎵銦磷(AlGalnP)半導體層,而該上披覆層為一 ρ型之鋁鎵銦磷(AlGalnP)半導體層。 1 9 ·如申請專利範圍第丨丨或丨2項之方法,其中該第二基板 之材質可為鍺(Ge)、矽(Si)或磷化鎵(GaP)、磷化銦 (InP)等任何組成之化合物半導體,亦可為如氧化銦錫 (ITO)、氧化鋅(Zn〇)等導電型氧化物。 2 0 .如申請專利範圍第1 1項之方法,其中該電極結構包含兩 個電極分別位於該第二基板及該下披覆層之表面上。 21 .如申請專利範圍第丨2項之方法,其中該電極結構包含兩 本紙張尺度適用中國國家揉準(CNS) A4規格(210X297公潑)A type of gallium indium phosphorus (AlGalnP) semiconductor layer, and the upper cladding layer is a P type of aluminum gallium indium phosphorus (AlGalnP) semiconductor layer. 8- The device according to item 5 of the application, wherein the lower cladding layer is an n-type gallium nitride dish-V compound semiconductor layer, and the upper cladding layer is a p-type gallium nitride mv group Compound semiconductor layer. 9. The device according to item 1 or 2 of the scope of patent application, wherein the material of the thick layer may be a compound of any composition such as germanium (Ge), silicon (Si) or gallium phosphide (GaP), indium phosphide (Inp), etc. The semiconductor may also be a conductive oxide such as indium tin oxide (IT0) or zinc oxide (ZηΟ). For example, the device of claim 1 or 2, wherein the electrode structure includes two electrodes on the surface of the thick layer and the other surface of the stacked structure opposite to the main surface. 11. A method for manufacturing a light-emitting semiconductor device, comprising the following steps: forming a lower conductive layer of a first conductivity type on a first substrate; forming an upper coating layer of a second conductivity type adjacent to the lower coating layer; forming An ohmic contact layer on the upper cladding layer; forming a reflective layer on the ohmic contact layer; bonding a second substrate to the reflective layer; removing the first substrate; and making it respectively conductive to the The electrode structure of the upper cladding layer and the lower cladding layer. 12. The method according to item 11 of the scope of patent application, wherein a buffer layer of a first conductivity type has been formed on the first substrate before forming the lower cladding layer, and the lower cladding layer is formed on the buffer Layer above. 1 3 · The method according to item 12 in the scope of patent application, wherein the lower coating layer is η. The paper size is applicable to the Chinese National Standard (cns) A4 specification (21〇χ 公 董) 480740 A8 B8 C8 D8 The patent application type gallium nitride Π-V compound semiconductor layer, and the upper cladding layer is a P-type gallium nitride melon-V compound semiconductor layer. 14 · The method according to item 11 or 12 of the scope of patent application, wherein before forming the upper cladding layer, it further comprises the step of forming an active layer on the lower cladding layer so that the active layer is bounded on the Between the lower cladding layer and the upper cladding layer. 15 · The method according to item 11 or i 2 of the scope of patent application, wherein the reflective layer has at least one region having a lower conductivity than the other portions and functions as a current blocking region. 16. The method according to item 5 of the patent application scope, wherein the current blocking region may be an insulating oxide, an insulating nitride, air, or a Schottky contact region. 17 · The method according to item 11 or 2 of the scope of patent application, wherein the reflective layer may be a single-layer structure such as Ti (Ti), aluminum (A1), or gold (Au), or gold / germanium (Au / Ge ), Titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au) and other multilayer structures. 18 · The method according to item 丨 丨 in the patent application range, wherein the lower cladding layer is an n-type gallium indium phosphorus (AlGalnP) semiconductor layer, and the upper cladding layer is a p-type aluminum gallium indium phosphorus (AlGalnP) semiconductor layer. 1 9 · If the method of the scope of application for patent No. 丨 丨 or 丨 2, the material of the second substrate may be germanium (Ge), silicon (Si) or gallium phosphide (GaP), indium phosphide (InP), etc. Compound semiconductors of any composition can also be conductive oxides such as indium tin oxide (ITO), zinc oxide (Zn0), and the like. 20. The method according to item 11 of the scope of patent application, wherein the electrode structure includes two electrodes on the surface of the second substrate and the lower cladding layer, respectively. 21. The method according to item 2 of the scope of patent application, wherein the electrode structure includes two paper sizes applicable to China National Standard (CNS) A4 (210X297) 裝 訂Binding 480740 8 8 8 8 A B c D 申請專利範圍 個電極分別位於該第二基板及該緩衝層之表面上 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)480740 8 8 8 8 A B c D Patent application scope Each electrode is located on the surface of the second substrate and the buffer layer -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
TW88117814A 2000-04-12 2000-04-12 Light-emitting semiconductor device with reflective layer structure and method for making the same TW480740B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88117814A TW480740B (en) 2000-04-12 2000-04-12 Light-emitting semiconductor device with reflective layer structure and method for making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88117814A TW480740B (en) 2000-04-12 2000-04-12 Light-emitting semiconductor device with reflective layer structure and method for making the same

Publications (1)

Publication Number Publication Date
TW480740B true TW480740B (en) 2002-03-21

Family

ID=21642625

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88117814A TW480740B (en) 2000-04-12 2000-04-12 Light-emitting semiconductor device with reflective layer structure and method for making the same

Country Status (1)

Country Link
TW (1) TW480740B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112456B2 (en) 2002-12-27 2006-09-26 Samsung Electro-Mechanics Co., Ltd. Vertical GaN light emitting diode and method for manufacturing the same
TWI492418B (en) * 2010-02-23 2015-07-11 Lg Innotek Co Ltd Light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112456B2 (en) 2002-12-27 2006-09-26 Samsung Electro-Mechanics Co., Ltd. Vertical GaN light emitting diode and method for manufacturing the same
TWI492418B (en) * 2010-02-23 2015-07-11 Lg Innotek Co Ltd Light emitting device

Similar Documents

Publication Publication Date Title
US6492661B1 (en) Light emitting semiconductor device having reflection layer structure
JP6722221B2 (en) Light emitting diode
US7355212B2 (en) Light emitting element
JP4644193B2 (en) Semiconductor light emitting device
US6958494B2 (en) Light emitting diodes with current spreading layer
US7319247B2 (en) Light emitting-diode chip and a method for producing same
US8674375B2 (en) Roughened high refractive index layer/LED for high light extraction
US11404606B2 (en) Semiconductor light-emitting element
KR101007139B1 (en) Light emitting device and method for fabricating the same
JP2001144321A (en) Light-emitting device and manufacturing method therefor
TW200541112A (en) Semiconductor light emitting devices including in-plane light emitting layers
JP2013201411A (en) Semiconductor light-emitting device
WO2006006555A1 (en) Semiconductor light-emitting device
KR20020089466A (en) Semiconductor light-emitting device, method for fabricating semiconductor light-emitting device, and electrode layer connection structure
US8158995B2 (en) Optoelectronic semiconductor chip
US10156335B1 (en) Light-emitting device
TWI230472B (en) Semiconductor light emitting device and the manufacturing method thereof
TW201817033A (en) III-P light emitting device with a superlattice
JP2009277898A (en) Semiconductor luminous element and manufacturing method of semiconductor luminous element
US6169298B1 (en) Semiconductor light emitting device with conductive window layer
TW480740B (en) Light-emitting semiconductor device with reflective layer structure and method for making the same
JP2003243699A (en) Semiconductor light emitting element
TW202215684A (en) Optoelectronic semiconductor device
US20240222588A1 (en) Semiconductor light-emitting element and light-emitting device thereof
TWI823644B (en) Optoelectronic semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees