TW480667B - Method to prevent via poisoning in dual damascene process - Google Patents

Abstract

This invention provides a method to prevent via poisoning in dual damascene process, which consists of the following steps: providing a semiconductor substrate having a dielectric layer with a specific dielectric constant; depositing a silicon oxynitride on the dielectric layer; forming a via photoresist layer on the silicon oxynitride layer; etching the dielectric layer to expose the substrate to form a via opening; removing the resist layer; depositing a liner oxide layer on the silicon oxynitride layer and the via opening to function as a barrier layer; and removing the liner oxide layer to expose the silicon oxynitride layer so that via poisoning is prevented in the dual damascene process.

Description

480667 V. Description of the invention (l) 'Field of invention: The invention relates to a method for avoiding a via hole in a semiconductor dual damascene process', especially using a wire oxide layer to avoid blocking. Background of the invention: > Super two-speed and ultra-large-capacity generation components, semiconductor manufacturers have tried several wire manufacturing methods, including single-mosaic, dual-mosaic and traditional " Plug and pattern " designs, and each method requires materials and Make some basic changes in process technology. As far as the current semiconductor technology is concerned, with a complete process technology, a dual damascene process (Duai Daniascene) combining Ming, copper alloys and low dielectric materials can meet the needs of most customers. These technologies have been fully proven that month b is enough to produce the complete wire structure required for ultra-large-capacity components. These integrated processes provide customers with choices in many processes, which can help customers save time in many process development and quality certifications, and more importantly, save time in product launches. In general, the traditional dual damascene technology uses conventional plasma etching to complete the trenches for plugs and connections, and then uses chemical vapor deposition to fill in the barrier layer and copper thin film materials. Mechanical polishing flattening table

480667 Description of the invention. However, in the traditional copper double inlaid funeral process, due to the nitrogen-containing dreams (meaning), the nitrogen-containing wounds will have a slight joint effect with the photoresist, which will affect the performance of the product. At the same time, during the development in the dual damascene process, the photoresist layer will remain in the opening 10 of the interlayer hole, as shown in the first figure A, as the photoresist layer remaining in the volcanic opening 10 ′ blocks the medium层 洞孔 10。 Hole openings 10. Therefore, if the first B® is viewed, that is, when the top view of the distribution surface of the integrated circuit is viewed, the mark 14 is a normal via hole 14 'and the mark 15 is a portion of the opening 15 blocked by the residual photoresist layer. The portion of the opening 15 blocked by the residual photoresist layer is smaller than the normal via hole opening π 14. In other words, the interstitial opening cannot be fully opened, which seriously affects the development effect. The above process, therefore, the occurrence of the poor performance of the semiconductor integrated circuit of Wang Qingxue SA ^ at. U ^ A ^ I Wang Jun continued, significantly affecting the group | & φ ^ I And waste of material costs and manpower. Summary of the Invention: In the double-embedded process of opening == intermediary ==, another object of the present invention is to improve the subsequent semiconductor volume circuit.

480667 V. Description of the invention (3)-Bad condition of machine month b 'significantly improves the yield of the assembly process, and reduces the cost of materials and waste of manpower. The present invention is a method of implementing a method for avoiding blocking of a via hole in a semiconductor dual damascene process. The steps include the following steps: First, a semiconductor substrate is provided, and the semiconductor substrate has a dielectric layer with a specific dielectric constant. Next, a silicon oxynitride (si 0N) layer is deposited on the dielectric layer with a specific dielectric constant. μ continues to form a via hole (Via) photoresist layer on the oxynitride layer until the substrate is followed, followed by 'etching the dielectric layer with a specific dielectric constant to expose to form a via hole. Continue, remove the via hole photoresist layer. 1. a line of oxide

Oxide) on the surface of the silicon oxynitride layer and on the surface of the interlayer hole so that ^ a μ evil horse and a barrier layer 〇 Finally, remove the line oxide layer on the oxynitride layer to expose the oxynitride layer So as to avoid a via hole blocking in the semiconductor dual damascene process. Say

480667 V. Description of the invention (4) In order to allow your reviewers to have a better understanding and approval of the present invention, a detailed description is given below in conjunction with the drawings. Detailed description of the invention: The present invention is a method for avoiding blocking of a via hole in a semiconductor dual damascene process, which includes the following steps:

First, as shown in FIG. 2A, a semiconductor substrate 21 is provided, and the semiconductor substrate 21 has a dielectric layer 22 having a specific dielectric constant. The semiconductor substrate 21 generally used is mainly a silicon wafer, and the dielectric layer having a specific dielectric constant is mainly a low dielectric material. The so-called low dielectric (Low-K) materials here include materials with a dielectric constant of about 4 or less, such as low dielectric materials containing Si0FX or SiOH3. Low dielectric constant materials with AMAT, NVLS, PORA, PORB, PORC and LKD on the market can also be used. Followed by ’as shown in FIG. 2B, a silicon oxynitride (SiON) layer was deposited by a conventional chemical vapor deposition method (Chemical Vapor Deposition).

23 is on the dielectric layer of the above-mentioned specific dielectric constant. Continuing, as shown in FIG. 2C, a conventional development method (? 11〇1: 〇1 丨 1:] 10) is used to form a via hole (1 ^ 3) and a photoresist layer (Photoresist). 24。 23 on the silicon oxynitride layer. The photoresist layer 24 described above is a type of DUV photoresist, and usually contains molecules of bases in the composition to achieve development.

Page 8 480667 V. Description of the Invention (5) Effect. Then, as shown in the second D diagram, a conventional non-isotropic etching method (Etching) is used, such as the plasma method to etch the dielectric layer 22 with a specific dielectric coefficient until the substrate 21 is exposed to form a dielectric hole. Open 6 〇. Then, as shown in FIG. 2E, the via hole photoresist layer 24 is removed by a conventional dry etching method, such as a plasma etching method. As shown in the second F diagram, a conventional chemical vapor deposition method is used to deposit a linear oxide layer 25, such as silicon oxide (SiO2), on the surface of the aforementioned silicon oxynitride layer 23 and the via 60. The opening surface is used as a barrier layer. The use of silicon oxide is to avoid the interaction with the photoresist, which can really achieve the purpose of blocking the barrier layer. As shown in the second G diagram, a conventional chemical mechanical polishing method ((: hemicai ό Slow CMP)) is used to polish to remove the upper part of the silicon oxynitride 23 = layer 25 until the oxynitride layer 23 is exposed, and Layer: The line oxide layer on the surface of the 60 opening is used to increase the development of the via hole in the semi-conductor to avoid-via hole blockage. After the above steps, as shown in the top view of the surface, all holes are replaced. In other words, all the interlayer openings are shown in the second figure, that is, the distribution port 31 of the integrated circuit is not blocked by the residual photoresist layer. The port 31 can be fully opened, which enhances the development of 480667. 5. The effect of the invention description (6), It also avoids the blocking of the via hole. Therefore, according to the present invention, the subsequent semiconductor integrated circuit failure can be improved, the yield of the assembly process can be significantly improved, and the waste of manpower is reduced. The invention is a method for blocking a via hole in a semiconductor dual damascene process. The implementation steps include: firstly, a semiconductor substrate is provided, and the dielectric layer is one of the dielectric constants of the semiconductor substrate. Next, a layer is deposited. nitrogen A silicon oxide (SiON) layer is formed on the electrical layer with a specific dielectric constant. A via hole photoresist layer is further formed on the silicon oxynitride layer. Next, the dielectric layer with a specific dielectric constant is etched to expose the substrate. So as to form a via hole opening. • Continue, remove the via hole photoresist layer. Deposit a linear oxide layer (Linear

Oxide) on the surface of the silicon oxynitride layer and the surface of the via hole as a barrier layer.

Page 10 480667 V. Description of the invention (7) Finally, the line oxide layer on the silicon oxynitride is removed until the silicon oxynitride layer is exposed, so as to avoid a via hole blocking in the semiconductor dual damascene process. The above description uses a preferred embodiment to describe the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the present invention. It does not depart from the spirit and scope of the present invention. Therefore, in summary, the specificity of this book has already met the requirements of the invention patent prescribed by Xuan Xiyu t & 4 W Ling Ling, which was reviewed by the Examination Committee of India and awarded the patent. For prayer.

The 480667 diagram on page 11 simply illustrates that the first A is a cross-sectional view of the conventional art; the first B is the top view of the conventional art; the second A to the second G are continuous cross-sectional views of the embodiment of the present invention; And the third figure is a continuous sectional view of an embodiment of the present invention. Figure number description:

1 0 via hole opening 11 residual photoresist layer 1 4 unopened via hole opening 1 5 normal via hole opening 21 semiconductor substrate 22 dielectric layer-2 3 silicon oxynitride layer 2 4 via hole photoresist layer 2 5 line oxide layer 31 interstitial hole 6 0 interstitial hole

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Claims (1)

480667 6. Scope of patent application h. A method for avoiding blocking of a via hole in a semiconductor dual damascene process, at least including: providing a semiconductor substrate having a dielectric layer with a specific dielectric constant on the semiconductor substrate; forming a A silicon oxynitride (Si 0N) layer is formed on the dielectric bulge of the specific dielectric constant; 9 a via hole photoresist layer is formed on the silicon oxynitride layer; the dielectric of the specific dielectric constant is etched Layer until the substrate is exposed to form a via hole opening; remove the via hole photoresist layer; deposit a line of oxide (Li near Oxide) on the surface of the silicon oxynitride layer and the surface of the via hole; remove The wire oxide layer on the silicon oxynitride is used to avoid the via hole blocking in the semiconductor dual damascene process. 2. The method according to item 丨 of the patent application scope, wherein the specific dielectric constant is less than about 4. 3 of the package = the method described in which the specific dielectric coefficient of 4 :::; =: the method of the description ′ in which the specific dielectric coefficient 480667 6. Scope of patent application 5. The method according to item 1 of the scope of patent application, wherein depositing the oxynitride layer includes chemical vapor deposition. 6. The method according to item 1 of the stated patent scope, wherein forming the interlayer hole photoresist layer includes lithography. 7. The method according to item 1 of the scope of patent application, wherein the dielectric layer for etching the specific dielectric constant comprises an anisotropic etching method. 8. The method according to item 1 of the scope of patent application, wherein the dielectric layer for etching the specific dielectric constant comprises a plasma etching method. Wherein, the interlayer hole is removed. 9. The method as described in item 1 of the scope of patent application, and the photoresist layer includes a dry etching method. Wherein, the interlayer hole is removed, and the line oxidation is deposited. The method described in item 1 of the patent application scope, wherein the photoresist layer includes a plasma etching method. 11. The method as described in item 丨 of the patent application, wherein the layer includes a chemical vapor deposition method. 12. The method described in item 1 of the scope of patent application, oxidizing crushing. Where the wire oxide layer includes 480667 VI. Application for Patent Scope 13. The method as described in item 1 of the scope of application for patent, wherein removing the wire oxide layer on the oxynitride includes chemical mechanical polishing. 14. A square house in a semiconductor dual damascene process to avoid blocking of a via hole at least includes: long: for a semiconductor substrate, the semiconductor substrate has a dielectric layer with a specific dielectric coefficient; μ deposits a nitrogen A silicon oxide (SiON) layer is formed on the dielectric sound of the specific dielectric coefficient; θ forms a dielectric hole (Via) photoresist layer on the silicon oxynitride layer; the dielectric layer of the specific dielectric coefficient is engraved Until the substrate is exposed to form a via hole opening; ^ remove the via hole photoresist layer; > Lineai Oxide on the surface of the silicon oxynitride layer and the surface of the via hole It is used as a barrier layer; removing the line oxide layer on the silicon oxynitride until the silicon oxynitride layer is exposed, so as to avoid the via hole blocking in the semiconductor dual damascene process. 15. The method according to item 14 of the scope of patent application, wherein the specific dielectric coefficient is less than about 4. / "16. The method as described in item 14 of the scope of patent application, wherein the dielectric layer with a specific dielectric constant contains at least Si OFX. 480667 6. Application for patent scope @ '17 · As described in the scope of patent application item 14 The method, wherein the dielectric layer with a specific dielectric constant comprises at least 30.1 (18. 18.) The method according to item 14 of the scope of the patent application, wherein depositing the oxynitride layer includes a chemical vapor deposition method. 19. The method according to item 14 in the scope of patent application, wherein forming the photoresist layer of the interlayer hole includes lithography. 20. The method according to item 14 in the scope of patent application, wherein the specific etching is performed The dielectric layer of the dielectric constant includes a buried isotropic etching method. 21. The method according to item 14 of the scope of the patent application, wherein the dielectric layer of the specific dielectric constant includes a plasma etching method. The method according to item 14 of the patent application, wherein removing the via hole photoresist layer includes a dry etching method. 23. The method according to item 14 of the patent application scope, wherein the via hole photoresist layer is removed. Including plasma etching. The method according to item 14 of the scope of patent application, wherein depositing the linear oxide layer includes a chemical vapor deposition method. 480667 VI. Scope of patent application 25. The method described in item 14 of the scope of patent application, wherein the wire oxide layer includes silicon oxide. 26. The method according to item 14 of the application, wherein removing the wire oxide layer on the silicon oxynitride includes a chemical mechanical polishing method. Page 17