TW480631B - Chip package structure - Google Patents

Chip package structure Download PDF

Info

Publication number
TW480631B
TW480631B TW90106421A TW90106421A TW480631B TW 480631 B TW480631 B TW 480631B TW 90106421 A TW90106421 A TW 90106421A TW 90106421 A TW90106421 A TW 90106421A TW 480631 B TW480631 B TW 480631B
Authority
TW
Taiwan
Prior art keywords
circuit board
printed circuit
chip package
package structure
chip
Prior art date
Application number
TW90106421A
Other languages
Chinese (zh)
Inventor
Ying-De Ou
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21677689&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW480631(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW90106421A priority Critical patent/TW480631B/en
Priority to US09/841,935 priority patent/US20020135059A1/en
Application granted granted Critical
Publication of TW480631B publication Critical patent/TW480631B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip package structure is disclosed, which comprises: a printed circuit board which includes a patterned circuit structure and an insulation structure, wherein the patterned circuit structure is interlaced among the insulation structure, and the insulation structure is formed of polymer; plural leads arranged at the edge of the printed circuit board in a row, and electrically connected to the printed circuit board; a chip fixed to the printed circuit board and electrically connected to the printed circuit board; a packaging material wrapping the chip, printed circuit board, the portion of leads close to the printed circuit board.

Description

480631 A8 B8 C8 D8 7 1 92twf1 .doc/008 爲弟⑽1。6 4 2 1 P 0 1號専利範圍修止本一 修正日期：2002.10.25 六、申請專利範圍 之族群中的一種材質。 6.如申請專利範圍第1項所述之晶片封裝結構，其 中該些導腳與該印刷電路基板的接合方式，係先藉由網板 印刷的方式將複數個凸塊置於該印刷電路基板上，再透過 迴焊的方式，將該些導腳與該些凸塊接合。 :至 Γρ480631 A8 B8 C8 D8 7 1 92twf1 .doc / 008 is the younger brother 1. 6 4 2 1 P 0 No. 1 scope of profit is amended This amendment date: 2002.10.25 Sixth, a material in the family of patent application. 6. The chip package structure according to item 1 of the scope of patent application, wherein the way of bonding the lead pins to the printed circuit board is to first place a plurality of bumps on the printed circuit board by screen printing. Then, the guide pins are joined to the bumps by means of re-soldering. : To Γρ

II

I H 土 414 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公釐） -------------裝--------訂-------I ·線 (請先閱讀背面之注意事項再填寫本頁)IH soil 414 This paper size is applicable to China National Standard (CNS) A4 specification (2) 〇χ 297 mm) ------------- Installation -------- Order --- ---- I · Line (Please read the precautions on the back before filling this page)

TW90106421A 2001-03-20 2001-03-20 Chip package structure TW480631B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW90106421A TW480631B (en) 2001-03-20 2001-03-20 Chip package structure
US09/841,935 US20020135059A1 (en) 2001-03-20 2001-04-25 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90106421A TW480631B (en) 2001-03-20 2001-03-20 Chip package structure

Publications (1)

Publication Number Publication Date
TW480631B true TW480631B (en) 2002-03-21

Family

ID=21677689

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90106421A TW480631B (en) 2001-03-20 2001-03-20 Chip package structure

Country Status (2)

Country Link
US (1) US20020135059A1 (en)
TW (1) TW480631B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7551455B2 (en) 2006-05-04 2009-06-23 Cyntec Co., Ltd. Package structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8026580B2 (en) * 2005-11-02 2011-09-27 International Rectifier Corporation Semiconductor device package with integrated heat spreader

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7551455B2 (en) 2006-05-04 2009-06-23 Cyntec Co., Ltd. Package structure

Also Published As

Publication number Publication date
US20020135059A1 (en) 2002-09-26

Similar Documents

Publication Publication Date Title
TW488042B (en) Quad flat non-leaded package and its leadframe
TW445612B (en) Solder ball array structure to control the degree of collapsing
TW579582B (en) Packaging system for die-up connection of a die-down oriented integrated circuit
TW463346B (en) Dual-leadframe package structure and its manufacturing method
TW409377B (en) Small scale ball grid array package
TW459361B (en) Three-dimensional multiple stacked-die packaging structure
TW523894B (en) Semiconductor device and its manufacturing method
TW463276B (en) Plastic packaging for a surface mounted integrated circuit
TW454287B (en) Multi-media chip package and its manufacture
TW488049B (en) Semiconductor device
TW575951B (en) Semiconductor device
TW447059B (en) Multi-chip module integrated circuit package
TW490830B (en) Heat sink with a shrinking mechanism and semiconductor device having the heat sink
TW517318B (en) Semiconductor device
TW480631B (en) Chip package structure
TW401629B (en) Semiconductor device and method for making the same
TW507502B (en) Semiconductor module
TW506093B (en) Cavity down ball grid array package and its manufacturing process
TW434760B (en) Interlaced grid type package structure and its manufacturing method
TW441053B (en) Semiconductor chip package with multilevel leads
TW480686B (en) Intersecting stacked type dual die package structure and manufacturing process
US6565008B2 (en) Module card and a method for manufacturing the same
TWI287876B (en) Semiconductor package
JPH11186492A (en) Semiconductor package and its mounting structure
TW480633B (en) Method of wire bonding, semiconductor device, circuit board, electronic machine and wire bonding device