480401 A7 B7 6522twf.doc/008 五、發明說明（I ) 發明領域 良·！ (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種用於處理器之掌控例外之裝置及 方法，且特別是有關於一種其使用軟體控制來掌控例外流 程之裝置及運作方法。 相關技藝之說明 —般都知道所提供的中央處理單元（Central Processing Unit ’簡稱CPU)同時在主處理模式及一個或多個例外處理 模式下運作。主處理模式是用來執行應用程式，藉以完成 使用者所需之資料處理。例外處理模式通常是用在諸如回 應外部提供之中斷信號之運作。 一般希望在主處理模式及例外處理模式之間的移動時 是可回復性的，即在回到主處理模式時，可以繼續主處理 模式的運作，好像未曾被中斷過。爲了達到此種可回復性， 在離開主處理模式時，必須將CPU中的各個處理暫存器 的內容儲存起^來，使其在例外處理模式結束時，可以回復 所使用的暫存器，以及將控制返回主處理模式。 經濟部智慧財產局員Η消費合作社印製480401 A7 B7 6522twf.doc / 008 V. Description of Invention (I) Field of Invention Good! (Please read the notes on the back before filling this page) The present invention relates to a device and method for controlling exceptions of processors, and in particular to a device and method for controlling exception processes using software control . Explanation of related techniques-It is generally known that the provided Central Processing Unit (CPU) is operating in both the main processing mode and one or more exception processing modes. The main processing mode is used to execute the application to complete the data processing required by the user. The exception handling mode is usually used for operations such as responding to externally provided interrupt signals. It is generally hoped that the movement between the main processing mode and the exception processing mode is recoverable, that is, when the main processing mode is returned, the operation of the main processing mode can be continued as if it has not been interrupted. In order to achieve this recoverability, when leaving the main processing mode, the contents of each processing register in the CPU must be stored ^ so that when the exception processing mode ends, the used register can be restored. And return control to main processing mode. Printed by Consumer Property Cooperative, Member of Intellectual Property Bureau, Ministry of Economic Affairs
傳統上，在離開主處理模式後，係將主處理模式下的 暫存器所儲存的內容傳到外部的一隨機存取記憶體 (Random Access Memory，RAM)上。而在回復到主處理模 式時，會將儲存在隨機存取記憶體內之主處理模式資料存 回暫存器中。此傳統的方法存在一問題，即從堆疊式記憶 體（Stack Memory)中循序地寫入或是讀出的速度皆非常 慢，會造成中央處理單元（CPU)的效能降低。另外一問題 即在進入或是離開主處理模式時，必須儲存相當多的資料 (例如不同的狀態旗標，用以指出所要或是所允許的CPU 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 480401 A7 B7 經濟部智慧財產局員工消費合作社印製 6522twf.doc/008 五、發明說明（π) 操作等等）。 另外，有一習知作法揭露於US Patent No. 5,386,563， 其發明名稱爲 ’’Register substitution during exception processing”，以及 US Patent No· 5,701，593，其發明名稱 爲"Exception handling method and apparatus in data processing systems" o 如這些專利所陳述的，當使用者程式以正常方式執行 時，程式計數器(Program Counter，簡稱PC)會依序地增加。 在執行使用者程式期間，處理器會檢查正常執行流程是否 被中斷。假如此正常執行流程被中斷，則爲例外發生。這 些例外或中斷允許處理器掌控產生此例外的事件。這些例 外可以是由內部的或外部的來源所引起的以及可以是由不 同原因的硬體或軟體所產生的。 一般而言，硬體會提供許多的暫存器，以供應在一般 主處理模式下（底下稱爲使用者模式User32)或是其他例外 事件時暫存資料。在此使用者模式下，具有十五個暫存器 用以作爲一般用途的資料暫存處理之用（底下以R〇、 到R14稱之）。而一程式計數暫存器R15pc係用來當成程 式計數器，以指出在將要執行的指令順序中目前的位置。 一目前程式狀態暫存器（Current Program Status Register， 底下稱爲CPSR)係用以儲存不同的旗標，以指出中央處理 單元CPU的控制參數(Control Parameters)，而其中有5個 位元，可用以指出目前處理的模式。此使用者模式User32 係提供用以執行使用者的程式。 所有不同類型的例外處理模式包括SVC32模式、 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 言 (請先閱讀背面之注意事項再填寫本頁)Traditionally, after leaving the main processing mode, the content stored in the register in the main processing mode is transferred to an external Random Access Memory (RAM). When reverting to the main processing mode, the main processing mode data stored in the random access memory is stored in the register. This conventional method has a problem that the sequential writing or reading speed from the stack memory is very slow, which will cause the performance of the central processing unit (CPU) to decrease. Another problem is that when entering or leaving the main processing mode, a considerable amount of data must be stored (for example, different status flags to indicate the required or allowed CPU. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 480401 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6522twf.doc / 008 V. Description of the invention (π) operation, etc.). In addition, there is a known practice disclosed in US Patent No. 5,386,563, whose invention name is "Register substitution during exception processing", and US Patent No. 5,701, 593, whose invention name is " Exception handling method and apparatus in data processing systems " o As stated in these patents, when the user program is executed in a normal manner, the Program Counter (PC) is sequentially increased. During the execution of the user program, the processor checks whether the normal execution flow is Interrupted. If normal execution flow is interrupted, exceptions occur. These exceptions or interruptions allow the processor to control the event that generated this exception. These exceptions can be caused by internal or external sources and can be caused by different reasons Hardware or software. Generally speaking, the hardware will provide a lot of registers to temporarily store data in the general main processing mode (hereinafter referred to as the user mode User32) or other exceptional events. In this user mode, there are fifteen registers to be used as General purpose data is temporarily stored for processing (referred to below as R0 to R14). A program counter register R15pc is used as a program counter to indicate the current position in the sequence of instructions to be executed. The current program status register (CPSR below) is used to store different flags to indicate the control parameters of the central processing unit CPU (Control Parameters), and there are 5 bits, which can be used to Indicate the current processing mode. This user mode User32 is provided to execute the user's program. All different types of exception processing modes include SVC32 mode. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297). Li) (Please read the notes on the back before filling out this page)
480401 A7 B7 6 5 2 2 twf . doc /0 0 8 五、發明說明（b)480401 A7 B7 6 5 2 2 twf .doc / 0 0 8 V. Description of the invention (b)
Undef32 模式、Abt32 模式、IRQ32 模式與 FIQ32 模式。SVC32 模式係用以當處理器重置（Reset)或是當軟體中斷指令 -I · I I (請先閱讀背面之注意事項再填寫本頁) (Software Interrupt Instruction)執行時進入。AM32 模式係 當記憶體系統終止記憶體存取時進入。IRQ32(Inten*upt Request)模式係當nlRQ腳位維持在低位準（邏輯〇)時，而 在CPSR的Ibit係淸楚地指出這樣的慢速中斷要求係容許 時會進入。FIQ32(Fast Interrupt request)模式係在當 hFIQ 腳位維持在低位準(邏輯0)時，而在CPSR的Fbit係淸楚 地指出這樣的快速中斷要求係容許時會進入。 經濟部智慧財產局員工消費合作社印製 每一個例外處理模式SVC32模式、Undef32模式、 AM32模式、IRQ32模式與FIQ32模式皆具有兩個例外模 式暫存器，當在進入這些模式後，可用以替換在使用者模 式時的第13個暫存器R13與第14個暫存器R14之內容。 而第13個暫存器R13通常用來儲存在使用者模式USer32 或是例外處理模式下的堆疊點（Stack Pointer)。當進入這些 例外模式其中之一時，系統將會儲存在程式計數暫存器 R15pc的內容到暫存器R14，以當成跳回使用者模式時的 位址暫存位置。這樣當此系統從例外處理模式跳回使用者 模式後，可以依此位址跳回。因此，如何在每一個例外處 理之事件處理後，將暫存器原來所儲存的資料存回則相當 地重要。 每一例外模式有其對應的儲存程式狀態暫存器（Saved Program Status Register，SPSR)。此 SPSR 係用以暫時儲 存之前一次模式中CPSR的資料，並且容許當前一次模式 回復後，重新存回CPSR。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 480401 A7 B7 6522twf.doc/008 五、發明說明（彳） ^ 經過例外處理之程序後'，則必須回到原來執行的位 址，此要求此例外處理能夠讓CPSR的資料重存回SPSR。 接著，程式計數器(Program Counter，簡稱PC)將會以儲存 在暫存器R14的回復位址(Return Address)，重新返回到此 回復位址，並接著執行使用者模式下的執行程式。 傳統的例外處理流程有嚴重的限制，其不容許在例外 處理時，在未切換暫存器列（Register Bank)或是切換模式 前進行儲存重要資訊或是偵錯値(Debug value)的動作。若 是具有此功能，假如需要的話，則可允許程式人員在設計 例外程式時有更多的彈性。 爲了達到這些及其他優點以及依照本發明之目的’ 如在此具體化及明白地說明，本發明提出一種用於一處理 器之一資料處理之軟體控制例外掌控流程之裝置及運作方 法，該裝置於一使用者模式、一例外前期模式、及一例外 模式之運作之間切換。本發明可在未切換暫存器列（Register Bank)或是切換模式前，進行儲存重要資訊或是偵錯値的 動作，使程式設計人員更具有彈性與效率。 在一例外發生後，該處理器可以在執行該例外程式 之前，執行設定及啓始程式。於該設定程式期間，在跳到 啓始程序之前，會將目前模式及返回位址儲存至緩衝器 中。 於該啓始程序期間，因爲該模式尙未改變至例外模 式，可以儲存資訊及檢視暫存器的値，藉以允許程式人員 除錯。這在除錯中斷的原因時是非常有用的。 本發明提出一種用於一處理器之一資料處理之軟體控 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 480401 6 5 2 2 twf . doc /0 0 8 A7 經濟部智慧財產局員工消費合作社印製 ____ B7 __—--—-- 五、發明說明（t) _ 制例外掌控流程之裝置，該裝置於一使用者模式、一例外 前期模式（pre-exception mode)、及一例外模式（exception mode)之運作之間切換，該裝置包括一程式狀態暫存器， 用以儲存在該使用者模式之處理狀態資訊；一程式計數器 暫存器，用以儲存在該使用者模式之一目前執行之程式指 令之一位址；一目前程式狀態暫存器緩衝器及一程式計數 器緩衝器，用以在一例外發生且該裝置從該使用者模式改 變運作時，於該例外前期模式之一例外掌控者設定程序期 間，分別儲存該程式狀態暫存器之內容及該程式計數器暫 存器之內容；以及一儲存程序狀態暫存器及一連結暫存 器，用以在一改變模式指令輸入該處理器後’分別儲存該 目前程式狀態暫存器緩衝器之內容及該程式g十數器緩衝器 之內容，其中該裝置改變運作從該例外前期模式至該例外 模式，其中該裝置在該例外前期模式運作之一期間足以供 一使用者執行一軟體運作。 本發明提出一種用於一處理器之一資料處理之軟體控 制例外掌控流程之運作方法，該處理器於一使用者模式、 一例外前期模式、及一例外模式之運作之間切換，該方法 包括當該處理器在該使用者模式運作時，將處理狀態資訊 儲存在一程式狀態暫存器；當該處理器在該使用者模式運 作時，將一目前執行之程式指令之一位址儲存在一程式計 數器暫存器；當一例外發生且該處理器從該使用者模式改 變運作時，於該例外前期模式之一例外掌控者設定程序期 間’分別將該程式狀態暫存器之內容及該程式計數器暫存 器之內容儲存在一目前程式狀態暫存器緩衝器及一程式計 -I - I I (請先閲讀背面之注意事項再填寫本頁) 0 訂· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 480401 A7 B7 6522twf.doc/008 五、發明說明（L) 數器緩衝器；以及在一改變模式指令輸入該處理器後，分 別將該目前程式狀態暫存器緩衝器之內容及該程式計數器 緩衝器之內容儲存在一儲存程序狀態暫存器及一連結暫存 器，其中該處理器改變運作從該例外前期模式至該例外模 式，其中該處理器在該例外前期模式運作之一期間足以供 一使用者執行一軟體運作。 必須明瞭前面之一般性說明及以下之詳細說明，皆是 示範性的，並且預備提出更進一步之本發明之解釋做爲宣 告。 圖式之簡單說明 包括所附之圖式，藉以提供對本發明之更進一步之瞭 解，以及結合在與構成此說明書之一部份。該些圖式繪示 本發明之實施例以及，與說明一起，用來解釋本發明之原 理。在這些圖式中， 第1圖是依照本發明之軟體控制例外掌控流程之較佳 實施例之流程圖。 較佳實施例之說明 請參照第1圖，其繪示依照本發明之用於處理器之軟 體控制例外掌控流程之裝置及其運作方法之較佳實施例的 流程圖。其裝置及方法可在使用者模式、例外前期模式、 及例外模式間切換。 持續執行步驟S 110的主程式直到在步驟S120發生中 斷。當在步驟S120發生中斷時，處理器會進入例外前期 本紙m尺度週用T國國豕ί示準（CNS)A4規格（21〇 x 297公爱） - ϋ 1 (請先閱讀背面之注意事項再填寫本頁) t^J· 經濟部智慧財產局員工消費合作社印製 480401 6 5 2 2 twf . doc/0 〇 8 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ) 模式，其包括例外掌控制者設定程序及啓始程序，如第1 圖之步驟130及步驟140所繪示。在步驟S130旳例外掌 控制者設定中，將目前程式狀態暫存器（Current Program Status Register，簡稱CPSR)的內容暫時複製到CPSR緩衝 器中。其儲存在使用者模式中的目前的處理狀態資訊（例 如目前模式、中斷遮罩及條件旗號）。然後將程式計數器 (Program Counter，簡稱PC)的內容，其儲存在使用者模式 中的目前執行的程式指令的位址，複製到PC緩衝器中。 然後處理器跳到步驟S140的例外前期模式的啓始程序。 在步驟S140中，啓始程序允許程式人員在切換暫存 器組，其具有保存被運用的資料的暫存器，之前，執行選 擇的軟體運作，例如儲存資訊、除錯或使用的値。這允許 程式人員在進入例外程式之前有最大的彈性。處理器在例 外前期模式的時間取決於使用者的需求。假如使用者需要 較多的時間來執行軟體運作，則處理器在例外前期模式運 作的時間較久。在例外前期模式的精確時間可藉由發出如 改變模式指令來決定。 在完成步驟S140的啓始程序後，接著到步驟S150， 執行啓始程序之後接著的改變模式指令，例如CDP協同 處理器指令。處理器會將原來的處理狀態資訊及返回位址 分別從CPSR緩衝器及PC緩衝器複製到相關的儲存處理 狀態暫存器（Saved Program Status Register ’ 簡稱 SPSR)及 一連結暫存器(Link Register，簡稱LR)中。此連結暫存器 係位於一例外模式下的一暫存器，用以儲存返回主程式之 位址亦即，執行CDP協同處理器指令來控制（register bank) (請先閲讀背面之注意事項再填寫本頁) 裝 訂： 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 480401 6522twf.doc/〇〇8 B7 五、發明說明（$ ) 切換。 ί :^一 — I (請先閱讀背面之注意事項再填寫本頁) CPSR緩衝器被複製到相關的一儲存處理狀態暫存器 (Saved Program Status Register，簡稱 SPSR)，其儲存的處 理狀態資訊包括目前模式、中斷遮罩及條件旗號。然後將 PC緩衝器，其儲存內容爲一返回位址，複製到暫存器組 的連結暫存器中。最後，在步驟S160，處理器改變模式到 例外模式，執行適當的例外程式。 當例外程式束後，在步驟S170，處理器必須回復系 統在主程式遇到例外時之系統之狀態。將SPSR複製到 CPSR，其回復處理狀態資訊，例如儲存的模式、中斷遮 罩及條件旗號。然後將LR，其用來儲存返回位址，複製 到PC 〇 然後，處理器返回到使用者模式，繼續執行指令。 在習知技藝中，例外切換是由硬體來控制的。軟體沒 有機制來決定切換時間。在本發明中，提出在例外掌控流 程的軟體控制機制。軟體可以決定在使用者模式或例外模 式之間切換的精確時間。其可以在例外之後立刻切換模 式，或是在儲存返回後要用的資訊後才切換模式。顯然的， 此機制在程式人員設計例外程式時，更具彈性。 經濟部智慧財產局員工消費合作社印製 很顯然的，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作少許之更動與潤飾。在前述之觀點下， 本發明涵蓋本發明之修飾及變化’其皆在下述之宣告及其 等同之範圍內。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Undef32 mode, Abt32 mode, IRQ32 mode and FIQ32 mode. SVC32 mode is used to enter when the processor is reset (Reset) or when the software interrupt instruction -I · I I (Please read the precautions on the back before filling this page) (Software Interrupt Instruction). AM32 mode is entered when the memory system terminates memory access. The IRQ32 (Inten * upt Request) mode is when the nlRQ pin is maintained at a low level (logic 0), and the Ibit of the CPSR clearly states that such a slow interrupt request is entered when allowed. The FIQ32 (Fast Interrupt request) mode is entered when the hFIQ pin is maintained at a low level (logic 0), and the Fbit of the CPSR clearly states that such a fast interrupt request is entered when allowed. The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs prints each exception handling mode, SVC32 mode, Undef32 mode, AM32 mode, IRQ32 mode and FIQ32 mode. There are two exception mode registers. The contents of the 13th register R13 and the 14th register R14 in the user mode. The 13th register R13 is usually used to store stack points in the user mode USer32 or the exception processing mode. When entering one of these exception modes, the system will store the contents of the program counter register R15pc to the register R14 as the temporary address location when jumping back to the user mode. In this way, when the system jumps from the exception processing mode back to the user mode, it can jump back at this address. Therefore, it is very important to return the original data stored in the temporary register after the processing of each exceptional event. Each exception mode has its corresponding Saved Program Status Register (SPSR). This SPSR is used to temporarily store the CPSR data in the previous mode, and allows the CPSR to be re-stored after the current mode is restored. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 480401 A7 B7 6522twf.doc / 008 V. Description of the invention (彳) ^ After going through the exception process, you must return to the original implementation Address, which requires this exception to allow CPSR data to be restored back to SPSR. Then, the Program Counter (PC for short) will return to this reset address with the return address stored in the register R14, and then execute the execution program in the user mode. The traditional exception processing flow has severe limitations. It does not allow the operation of storing important information or debugging value (Debug value) before switching the register bank (Register Bank) or switching modes during exception processing. If it has this function, it can allow programmers more flexibility in designing exception programs if needed. In order to achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and clearly described herein, the present invention proposes a device and an operating method for a software control exception control flow for a processor-data processing, the device Switch between the operation of a user mode, an exception early mode, and an exception mode. The invention can perform the action of storing important information or detecting errors before switching the register bank or switching mode, so that the programmer has more flexibility and efficiency. After an exception occurs, the processor can execute the setup and startup routines before executing the exception routine. During the setup procedure, the current mode and return address are stored in the buffer before jumping to the start procedure. During the start-up process, because the mode has not been changed to the exception mode, information can be stored and the register can be viewed to allow programmers to debug. This is useful when debugging the cause of an interrupt. The present invention proposes a software-controlled paper size for one processor and one data processor. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page). Printed by the Employees 'Cooperatives of the Ministry of Intellectual Property Bureau 480401 6 5 2 2 twf .doc / 0 0 8 A7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ____ B7 __---------- V. Description of Invention (t) _ A device for controlling an exception control process. The device switches between operation of a user mode, a pre-exception mode, and an exception mode. The device includes a program status register. It is used to store the processing state information in the user mode; a program counter register is used to store the address of one of the currently executing program instructions in the user mode; a current program state register buffer and A program counter buffer, which is used to store an exception when the device changes operation from the user mode, during the setting procedure of the exception controller of one of the previous exception modes. The contents of the program status register and the program counter register; and a program status register and a link register, which are used to respectively store the current after a change mode command is input to the processor The contents of the program status register buffer and the program g ten device buffer, wherein the device changes operation from the pre-exception exception mode to the exception mode, where the device is sufficient for one of the periods during which the pre-exception exception mode operates. A user performs a software operation. The present invention provides an operation method for software-controlled exception control flow for data processing of a processor. The processor switches between operation of a user mode, an early exception mode, and an exception mode. The method includes: When the processor is operating in the user mode, processing state information is stored in a program state register; when the processor is operating in the user mode, an address of a currently executing program instruction is stored in A program counter register; when an exception occurs and the processor changes operation from the user mode, during the setting procedure of the exception controller in one of the previous exception modes, the contents of the program status register and the The contents of the program counter register are stored in a current program status register buffer and a program counter-I-II (please read the precautions on the back before filling this page). 0 Order · This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) 480401 A7 B7 6522twf.doc / 008 5. Description of the invention (L) Counter buffer; and a mode change instruction After entering the processor, the contents of the current program state register buffer and the program counter buffer are stored in a stored program state register and a link register, respectively, where the processor changes the operation from The early exception mode to the exceptional mode, wherein the processor is sufficient for a user to execute a software operation during one of the operations in the early exception mode. It must be understood that the foregoing general description and the following detailed description are exemplary, and further explanations of the present invention are intended to be made as declarations. A brief description of the drawings includes the accompanying drawings to provide a further understanding of the invention, and to incorporate and form part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. Among these drawings, FIG. 1 is a flowchart of a preferred embodiment of a software control exception control process according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Please refer to FIG. 1, which shows a flowchart of a preferred embodiment of a device for software control exception control flow for a processor and an operation method thereof according to the present invention. The device and method can switch between user mode, pre-exception mode, and exception mode. The main routine of step S110 is continuously executed until an interruption occurs at step S120. When an interruption occurs in step S120, the processor will enter the exception of the previous paper m-scale weekly T-country standard (CNS) A4 specification (21〇x 297 public love)-ϋ 1 (Please read the precautions on the back before (Fill in this page) t ^ J · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 480401 6 5 2 2 twf .doc / 0 〇8 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs It includes an exception controller setting procedure and a starting procedure, as shown in steps 130 and 140 in FIG. 1. In step S130: Exceptional controller setting, the content of the current program status register (CPSR) is temporarily copied to the CPSR buffer. It stores the current processing status information in the user mode (for example, current mode, interrupt mask, and condition flags). Then, the content of the Program Counter (PC for short) is stored in the address of the currently executing program instruction in the user mode, and copied to the PC buffer. The processor then jumps to the initiation procedure of the exception early mode in step S140. In step S140, the start-up procedure allows the programmer to switch the register group, which has a register for storing the used data, and before executing the selected software operation, such as storing information, debugging, or using data. This allows programmers to have maximum flexibility before entering exception programs. The amount of time the processor spends in pre-exception mode depends on the needs of the user. If the user needs more time to execute the software operation, the processor will take longer to run in the exception pre-mode. The exact time in the early exception mode can be determined by issuing commands such as change mode. After completing the start-up procedure of step S140, proceed to step S150, and execute the mode change instruction that follows the start-up procedure, such as a CDP coprocessor instruction. The processor will copy the original processing status information and return address from the CPSR buffer and the PC buffer to the relevant stored processing status register (SPSR) and a link register (Link Register , Referred to as LR). This link register is a register located in an exception mode, used to store the address returned to the main program, that is, to execute the CDP coprocessor instructions to register (register bank) (Please read the precautions on the back before (Fill in this page) Binding: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 480401 6522twf.doc / 〇〇8 B7 V. Description of invention ($) Switch. ί: ^ 一 — I (Please read the notes on the back before filling this page) The CPSR buffer is copied to a related Saved Program Status Register (SPSR), which stores the processing status information. Includes current mode, interrupt mask, and condition flags. Then the PC buffer, whose storage content is a return address, is copied to the link register of the register group. Finally, in step S160, the processor changes the mode to the exception mode and executes an appropriate exception routine. After the exception program is terminated, the processor must restore the state of the system when the main program encounters the exception in step S170. The SPSR is copied to the CPSR, which restores processing status information such as the stored mode, interrupt mask, and condition flags. Then the LR, which is used to store the return address, is copied to the PC. Then, the processor returns to the user mode and continues executing instructions. In conventional techniques, exception switching is controlled by hardware. The software has no mechanism to determine the switching time. In the present invention, a software control mechanism that controls the process exceptionally is proposed. Software can determine the exact time to switch between user mode or exception mode. It can switch the mode immediately after an exception, or switch the mode after saving the information to be used after returning. Obviously, this mechanism is more flexible when programmers design exception programs. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs It is clear that anyone skilled in this art can make a few changes and retouching without departing from the spirit and scope of the present invention. Under the foregoing point of view, the present invention encompasses modifications and variations of the present invention ', which are all within the scope of the following claims and their equivalents. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)