478160 經濟部智慧財產局員工消費合作社印製 7101twf.doc/006 __B7__ 五、發明說明（/ ) 本發明是有關於一種與具有內建電感元件之晶片結 構，且特別是有關於一種於電感元件下方形成具有靜電屏 蔽（electrostatic shielding )效果之場氧元件（field device )， 用以阻斷矽基底中寄生損失電流（eddy current )產生的晶片 結構。 現今的高頻矽晶片（RF silicon chip )基於成本的考 量，以內建電感元件之方式將被動元件例如電感元件整合 於主動元件內，由於電感元件很接近矽基底（約小於10 微米以下），在使用高頻元件的操作頻率下，矽基底會形 同導體般消耗掉大量的能量，使得電感元件之Q値（Quality factor )降低。再者，由於砷化鎵（GaAs )在高頻操作時會 產生半導體的隔離效果，因此一般在製作高頻晶片時，通 常會使用昂貴的砷化鎵晶片來替代矽晶片，以改善電感元 件之能量消耗問題，提高高頻矽晶片上電感元件之效能。 然而，砷化鎵晶片雖具有較佳隔離效果，但因其材料本身 較爲昂貴，使得製造成本遠高於互補金氧半導體 (Complement Metal Oxide Silicon，CMOS )製程。 請參照第1圖，其繪示爲習知具有內建電感元件矽晶 片之剖面示意圖。提供一矽基底100，矽基底100上具有 一主動區域102與一隔離區域1〇4。其中，主動區域1〇2 上配置有若干之主動元件，而以場氧化層（FOX )作爲隔離 區域104,主動元件與隔離區域1〇4上更配置有一平坦化 之介電層106覆蓋其上。而在介電層1〇6的上方以內建的 方式將電感元件108整合於矽基底1〇〇之隔離區域1〇4上 3 本紙張尺度適用中國國家標準（CNS)A4規格X 297公爱） ---------^--------1^. (請先閱讀背面之注意事項再填寫本頁) 478160 7101twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 方，電感元件108包括多層的電感線圈（trace )108a，各層 ‘ 電感線圏l〇8a之間以介電層108b作爲電性絕緣，且各層 電感線圏l〇8a之間並以插塞108c彼此電性連接。 同樣請參照第1圖，具有內建電感元件108之矽晶片 1〇〇結構中，由於電感元件108架構於矽基底100的隔離 區域104如場氧化層（Field Oxide，FOX )上方，故矽基底 100上會因電感元件108的電磁感應而產生寄生損失電流 I，寄生損失電流I會在矽基底1〇〇中順著電感線圈l〇8a 的軸方向流動，因此寄生損失電流I將會造成電感元件108 的Q値下降，進而影響到電感元件108在高頻操作下的表 現（performance ) 〇 因此，本發明的目的在提出一種具有內建電感元件 之晶片結構，將電感元件架構於由η井（n-well )、場氧化 層以及場氧化層（FOX )下方的p井（p-well )所組成之場氧 元件（Held device )上方，由於η井及p井之間的深p-n接 合（deep p-n· junction )會形成較佳的阻障效果（barrier height )，故可有效地阻斷基底中的寄生損失電流。 爲達本發明之上述目的，提出一種具有內建電感元 件之晶片結構至少包括一基底、配置於基底上方之若干主 動元件、一上表面平坦之介電層以及一電感元件。其中， 基底上具有一主動區域與一柵狀結構之場氧元件，柵狀結 構之場氧元件由多個配置於基底上之場氧化層、多個配置 於場氧化層下方基底中的第一型離子摻雜區域，以及多個 配置於場氧化層之間基底中的第二型離子摻雜區域所構 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 478160 7101twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>) 成，第一型離子摻雜區域與第二型離子摻雜區域之間會形 成接合區域，利用這些第一型離子摻雜區域與第二型離子 摻雜區域之間所形成的接合區域，在特定方向上阻斷基底 中之寄生損失電流。此外，介電層配置於基底上用以覆蓋 於主動元件與場氧元件上方，而電感元件則配置於場氧元 件上方之介電層上。由於第一型離子摻雜區域與第二型離 子摻雜區域係交互且相互平行地配置於基底中，故所形成 的接合區域會呈現一柵狀結構以阻斷基底中的寄生損失電 流。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1圖繪示爲習知具有內建電感元件矽晶片之剖面示 意圖； 第2圖繪示爲依照本發明一較佳實施例具有內建電感 元件晶片之剖面示意圖；以及 第3圖繪示爲依照本發明一較佳實施例具有內建電感 元件晶片之俯視示意圖。 圖式之標示說明： 100 :矽基底 102 :主動區域 104 :隔離區域 106 :介電層 5 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經齊邹智慧財產局員工消費合作fi-印製 478160 ?101twf.doc/006 A7 --------B7 __ 五、發明說明（今） 108 :電感元件 k l〇8a:電感線圈 108b :介電層 108c :插塞 200 :基底 202 :主動區域 202a :主動元件 204 :隔離區域 206 :場氧化層 208 :第一型離子摻雜區域 210 :第二型離子摻雜區域 212 :介電層 214 :電感元件 214a :電感線圏 214b :介電層 214c :導體插塞 較佳實施例 首先請參照第2圖，其繪示爲依照本發明一較佳實施 例具有內建電感元件之晶片的剖面示意圖。首先提供一基 底200，基底200例如爲矽基底，且基底200上具有一主 動區域202以及一隔離區域204,但基底200的主動區域202 上具有多個主動元件202a，而基底200之隔離區域204上 具有多個互相平行之場氧化層206，場氧化層206例如是 以區域氧化（LOCal Oxidation Silicon，LOCOS )製程，而在 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） — — — — — — — — — — — — 奮 I I I I I I I — — — — — — — I· - _ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 478160 7101twf. doc/ 0 0 6 A7 _ B7 五、發明說明（f) 定義主動區域202與隔離區域204時，例如以經過圖案化 之氣化砂層爲罩幕（mask )，於基底200隔離區域204上的 部分區域形成場氧化層206。而在形成場氧化層206之前 需先進行一第一型離子植入步驟，之後再將基底200置於 氧化爐管中將場氧化層206製作於基底200隔離區域204 的部分區域上，並藉由氧化爐管之高溫將第一型離子驅入 (drive in )基底200中，以形成第一型離子摻雜區域208， 之後再將氮化矽層移除。 同樣請參照第2圖，將氮化矽層移除之後，再以基底 200上之場氧化層206爲罩幕，進行一第二型離子摻雜步 驟，並接著進行一回火（annealing )步驟將第二型離子驅入 基底200中，以於場氧化層206之間的基底200中形成第 二型離子摻雜區域210。而上述第一型離子摻雜區域208 於第二型離子摻雜區域210爲不同型（type )之摻雜’例如 第一型離子摻雜區域208爲η型摻雜而第二型離子摻雜區 域210爲ρ型摻雜，或是第一型離子摻雜區域208爲ρ型 摻雜而第二型離子摻雜區域210爲η型摻雜。因此，在第 一型離子摻雜區域208與第二型離子摻雜區域210之間的 接合處會形成ρ-η接面。 同樣請參照第2圖，基底200上更配置有一介電層 212，此介電層212例如爲一具有平坦上表面之二氧化矽 (Si02 )或其他具有低介電常數（low k )之材質，其主要作 用在於保護主動元件202a以及將隔離區域204上方的電感 元件214於基底200隔開。而在介電層212上方則配置一 7 ^-----------------^ (請先閱讀f*面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478160 7101twf.doc/〇〇6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6) 被動元件例如爲電感元件214，其中，電感元件214例如 、 包括多層結構的電感線圈214a，各層電感線圈214a之間 例如以介電層214b作爲電性絕緣，且各層電感線圈214a 之間例如以導體插塞214c彼此電性連接。 由於電感元件214架構於基底200的隔離區域上方， 且基底200與電感元件214之間以場氧化層206以及介電 層212作爲電性隔離，但是基底200於電感元件214之間 會因電感元件214的電磁感應而於基底200上產生寄生損 失電流，故本發明中於基底200之隔離區域204上形成由 場氧化層206、第一型離子摻雜區域208以及第二型離子 摻雜區域210所組成之柵狀結構的場氧元件（field device )，用以阻斷基底200中之寄生損失電流，避免造成 電感元件214的Q値下降，進而改進電感元件214在高頻 操作下的表現。 上述於基底200上所形成之場氧化層206、場氧化層 206下方的第·一型離子摻雜區域208以及場氧化層206之 間的第二型離子摻雜區域210具有一柵狀結構。其中，場 氧化層206係具有將基底200與電感元件214間的距離拉 大的作用，而第一型離子摻雜區域208與第二型離子摻雜 區域210之間的接合區域，係用以阻斷基底200中因電感 元件214所感應之寄生損失電流。 最後請參照第3圖，其繪示爲依照本發明一較佳實施 例具有內建電感元件晶片之俯視示意圖。由第3圖可以淸 楚看到，配置於電感元件214下方的場氧化層206、場氧 8 ^-----------------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 478160 經濟部智慧財產局員工消費合作社印製 71 Ο 1twf. doc/0 0 6 五、發明說明（I ) 化層206下方的第一型離子摻雜區域208以及場氧化層206 之間的第二型離子摻雜區域210爲一柵狀結構，此柵狀結 構之場氧元件中由第一型離子摻雜區域208以及第二型離 子摻雜區域210間所形成之接合區域亦呈現柵狀結構’故 可以將電感元件214因電磁感應所產生的寄生損失電流在 X方向上阻斷，有效的改善因寄生損失電流所導致電感Q 値降低的缺點。 綜上所述，本發明具有內建電感元件之矽晶片結構 至少具有下列優點： 1.本發明具有內建電感元件之晶片結構中，場氧化 層、其下方的第一型離子摻雜區域以及其間的第二型離子 摻雜區域爲一柵狀結構，此柵狀結構可以將電感元件因電 磁感應所產生的寄生損失電流在特定方向上阻斷，有效的 改善因寄生損失電流所導致電感Q値降低的缺點。 2·本發明具有內建電感元件之晶片結構中，藉由摻雜 型態相反之第一型離子摻雜區域以及第二型離子摻雜區域 所形成之p-n接面，其具有較高的阻障效果（barrier height )，用以阻斷基底中之寄生損失電流。 3.本發明具有內建電感元件之晶片結構中，場氧化 層、其下方的第一型離子摻雜區域以及其間的第二型離子 摻雜區域的形成方式可與現行之半導體製程相容。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 9 本紙張尺度適用中國國家標準（CNS)A‘1規格（210 X 297公釐） -------------^--------^---------^ - * - - (請先閱讀背面之注意事項再填寫本頁)478160 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7101twf.doc / 006 __B7__ V. Description of the Invention (/) The present invention relates to a chip structure with a built-in inductive element, and in particular to an under-inductive element A field device having an electrostatic shielding effect is formed to block a chip structure generated by a parasitic loss current (eddy current) in a silicon substrate. Today's RF silicon chips are based on cost considerations. Passive components such as inductive components are integrated into active components with built-in inductive components. Because inductive components are very close to the silicon substrate (less than about 10 microns), At the operating frequency of using high-frequency components, the silicon substrate consumes a large amount of energy like a conductor, making the Q 値 (Quality factor) of the inductive component lower. In addition, since gallium arsenide (GaAs) will produce semiconductor isolation effect at high frequency operation, generally when manufacturing high frequency wafers, expensive gallium arsenide wafers are often used instead of silicon wafers to improve the inductance components. Energy consumption issues to improve the performance of inductive components on high-frequency silicon chips. However, although the gallium arsenide wafer has a better isolation effect, its material is more expensive, which makes the manufacturing cost much higher than that of the Complement Metal Oxide Silicon (CMOS) process. Please refer to Figure 1, which is a schematic cross-sectional view of a conventional silicon wafer with a built-in inductor element. A silicon substrate 100 is provided. The silicon substrate 100 has an active region 102 and an isolation region 104. Among them, a number of active elements are arranged on the active region 102, and a field oxide layer (FOX) is used as the isolation region 104. A flattened dielectric layer 106 is further disposed on the active element and the isolation region 104 to cover it. . The inductive element 108 is integrated on the silicon substrate 100 in the isolation region 10 on the dielectric layer 106 in a built-in manner. 3 This paper size applies the Chinese National Standard (CNS) A4 specification X 297. ) --------- ^ -------- 1 ^. (Please read the notes on the back before filling out this page) 478160 7101twf.doc / 006 A7 B7 Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed 5. Description of the invention (2) Fang, the inductive element 108 includes a multi-layered inductive coil (trace) 108a, and the dielectric layer 108b is used as the electrical insulation between the various layers of the inductance wire 圏 108a, and the inductance wires of each layer 圏108a is electrically connected to each other with a plug 108c. Please also refer to FIG. 1. In a silicon wafer 100 structure with a built-in inductive element 108, since the inductive element 108 is structured above the isolation region 104 of the silicon substrate 100 such as a field oxide (FOX), the silicon substrate A parasitic loss current I will be generated on the 100 due to the electromagnetic induction of the inductive element 108. The parasitic loss current I will flow in the silicon substrate 100 along the axial direction of the inductance coil 108a, so the parasitic loss current I will cause inductance. The Q 値 of the element 108 decreases, which further affects the performance of the inductive element 108 under high-frequency operation. Therefore, the object of the present invention is to propose a chip structure with a built-in inductive element. (N-well), the field oxide layer, and the p-well (p-well) under the field oxide layer (FOX), above the field oxygen element (Held device), due to the deep pn junction between the n-well and the p-well ( deep pn junction) will form a better barrier height, so it can effectively block the parasitic loss current in the substrate. In order to achieve the above object of the present invention, a wafer structure with a built-in inductor element is provided which includes at least a substrate, a plurality of active elements disposed above the substrate, a dielectric layer having a flat upper surface, and an inductor element. The field oxygen element on the substrate has an active region and a grid-like structure. The field oxygen element of the grid-like structure consists of a plurality of field oxide layers disposed on the substrate and a plurality of first substrates disposed below the field oxide layer. Type ion-doped regions, and a plurality of second type ion-doped regions arranged in the substrate between the field oxide layers 4 This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^- ------- ^ --------- line (please read the precautions on the back before filling out this page) 478160 7101twf.doc / 006 A7 B7 Printed by the Staff Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention (>) The junction region is formed between the first-type ion-doped region and the second-type ion-doped region, and the first-type ion-doped region and the second-type ion-doped region are used. The formed junction area blocks the parasitic loss current in the substrate in a specific direction. In addition, a dielectric layer is disposed on the substrate to cover the active element and the field oxygen element, and the inductive element is disposed on the dielectric layer above the field oxygen element. Since the first-type ion-doped region and the second-type ion-doped region are arranged in the substrate alternately and in parallel with each other, the formed bonding region will present a gate structure to block the parasitic loss current in the substrate. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 shows FIG. 2 is a schematic cross-sectional view of a silicon wafer with a built-in inductive element; FIG. 2 is a schematic cross-sectional view of a wafer with a built-in inductive element according to a preferred embodiment of the present invention; and FIG. The preferred embodiment has a top view of a chip with a built-in inductor element. Description of the drawing: 100: silicon substrate 102: active area 104: isolation area 106: dielectric layer 5 ------------- installation -------- order --- ------ Line (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed 478160? 101twf.doc / 006 A7 -------- B7 __ V. Description of the invention (present) 108: Inductive element k10a: Inductive coil 108b: Dielectric layer 108c: Plug 200: Substrate 202 : Active region 202a: active element 204: isolation region 206: field oxide layer 208: first-type ion-doped region 210: second-type ion-doped region 212: dielectric layer 214: inductance element 214a: inductance line 214b: Dielectric layer 214c: A preferred embodiment of a conductive plug Please first refer to FIG. 2, which is a schematic cross-sectional view of a chip with a built-in inductance element according to a preferred embodiment of the present invention. First, a substrate 200 is provided. The substrate 200 is, for example, a silicon substrate, and the substrate 200 has an active region 202 and an isolation region 204. However, the active region 202 of the substrate 200 has a plurality of active elements 202a, and the isolation region 204 of the substrate 200 There are multiple field oxide layers 206 parallel to each other. For example, the field oxide layer 206 is manufactured by a local oxidation (LOCal Oxidation Silicon, LOCOS) process, and the Chinese National Standard (CNS) A4 specification (210 X 297) ) — — — — — — — — — — — — — FenIIIIIII — — — — — — — I ·-_ (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 478160 7101twf.doc / 0 0 6 A7 _ B7 V. Description of the invention (f) When defining the active area 202 and the isolation area 204, for example, a patterned gasified sand layer is used as a mask on the isolation area 204 of the substrate 200 A partial oxide region 206 is formed. Before the field oxide layer 206 is formed, a first-type ion implantation step is required, and then the substrate 200 is placed in an oxidation furnace tube. The field oxide layer 206 is fabricated on a part of the isolation region 204 of the substrate 200 and borrowed. The first type ions are driven into the substrate 200 by the high temperature of the oxidation furnace tube to form a first type ion doped region 208, and then the silicon nitride layer is removed. Similarly, referring to FIG. 2, after the silicon nitride layer is removed, a field oxide layer 206 on the substrate 200 is used as a mask to perform a second-type ion doping step, and then an annealing step is performed. The second type ions are driven into the substrate 200 to form a second type ion doped region 210 in the substrate 200 between the field oxide layers 206. The first type ion doped region 208 and the second type ion doped region 210 are doped with different types. For example, the first type ion doped region 208 is n-type doped and the second type ion doped. The region 210 is p-type doped, or the first-type ion-doped region 208 is p-type doped and the second-type ion-doped region 210 is n-type doped. Therefore, a ρ-η junction is formed at the junction between the first-type ion-doped region 208 and the second-type ion-doped region 210. Referring to FIG. 2 as well, a dielectric layer 212 is further disposed on the substrate 200. The dielectric layer 212 is, for example, a silicon dioxide (Si02) having a flat upper surface or other materials having a low dielectric constant (low k). Its main function is to protect the active element 202 a and separate the inductance element 214 above the isolation region 204 from the substrate 200. A 7 ^ ----------------- ^ is placed above the dielectric layer 212 (please read the precautions on the f * face before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 478160 7101twf.doc / 〇〇6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The passive element is, for example, the inductive element 214, of which The inductive element 214 includes, for example, a multi-layered inductive coil 214a. The inductive coils 214a of each layer are electrically insulated, for example, by a dielectric layer 214b, and the inductive coils of each layer 214a are electrically connected to each other by, for example, a conductor plug 214c. Since the inductive element 214 is structured above the isolation region of the substrate 200, and the field oxide layer 206 and the dielectric layer 212 are used for electrical isolation between the substrate 200 and the inductive element 214, the substrate 200 and the inductive element 214 may be separated by the inductive element. A parasitic loss current is generated on the substrate 200 by the electromagnetic induction of 214. Therefore, in the present invention, a field oxide layer 206, a first type ion-doped region 208, and a second type ion-doped region 210 are formed on the isolation region 204 of the substrate 200 The formed field device of the grid structure is used to block the parasitic loss current in the substrate 200 to prevent the Q 値 of the inductive element 214 from decreasing, thereby improving the performance of the inductive element 214 under high frequency operation. The field oxide layer 206 formed on the substrate 200, the first-type ion-doped region 208 under the field oxide layer 206, and the second-type ion-doped region 210 between the field oxide layer 206 have a gate structure. The field oxide layer 206 has a function of increasing the distance between the substrate 200 and the inductive element 214, and the junction region between the first-type ion-doped region 208 and the second-type ion-doped region 210 is used for The parasitic loss current induced by the inductive element 214 in the substrate 200 is blocked. Finally, please refer to FIG. 3, which is a schematic plan view of a chip with a built-in inductor element according to a preferred embodiment of the present invention. As can be clearly seen from Figure 3, the field oxide layer 206 and the field oxygen 8 ^ ----------------- line disposed under the inductive element 214 (please read the Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 x 297 mm). 478160 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 71 〇 1twf. Doc / 0 0 6 V. Description of the invention (I) The first-type ion-doped region 208 under the chemical layer 206 and the second-type ion-doped region 210 between the field oxide layer 206 are a gate-like structure. The junction region formed between the ion-type ion-doped region 208 and the second-type ion-doped region 210 also exhibits a gate-like structure. The improvement of the shortcoming of the inductance Q due to the parasitic loss current. In summary, the silicon wafer structure of the present invention with a built-in inductive element has at least the following advantages: 1. In the wafer structure of the present invention with a built-in inductive element, the field oxide layer, the first type ion-doped region below it, and The second type of ion-doped region therebetween is a grid structure. This grid structure can block the parasitic loss current generated by the inductive element due to electromagnetic induction in a specific direction, and effectively improve the inductance Q caused by the parasitic loss current.値 Reduced disadvantages. 2. In the wafer structure with a built-in inductance element of the present invention, the pn junction formed by the first type ion doped region and the second type ion doped region with opposite doping types has a higher resistance. A barrier height is used to block parasitic loss current in the substrate. 3. In the wafer structure with a built-in inductance element of the present invention, the formation method of the field oxide layer, the first-type ion-doped region below it, and the second-type ion-doped region therebetween can be compatible with the current semiconductor manufacturing process. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 This paper size applies to China National Standard (CNS) A'1 (210 X 297 mm) ------------- ^ -------- ^ ----- ---- ^-*--(Please read the notes on the back before filling this page)