TW478159B - Differential amplifier of an integrated semiconductor circuit - Google Patents

Differential amplifier of an integrated semiconductor circuit Download PDF

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Publication number
TW478159B
TW478159B TW089110056A TW89110056A TW478159B TW 478159 B TW478159 B TW 478159B TW 089110056 A TW089110056 A TW 089110056A TW 89110056 A TW89110056 A TW 89110056A TW 478159 B TW478159 B TW 478159B
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Taiwan
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terminal
differential amplifier
input
well
substrate
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TW089110056A
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Chinese (zh)
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Sebastian Kuhne
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier

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  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Abstract

An integrated semiconductor circuit has a differential amplifier (10) having two input transistors (T1, T2), a current source, (30) and a load element (20). One input transistor (T1, T2) of the NMOS type is arranged in a well (Wp) of the p conductivity type, which, for its part, is arranged in a substrate (Sp) of the p conductivity type. The well (Wp) is electrically insulated from the substrate (Sp). The well (Wp) has a well terminal (B), which is connected to the source terminal (S). By avoiding a potential difference between the well terminal (B) and the source terminal (S), the switching behavior of the transistor (T1, T2) and thus of the differential amplifier (10) is not adversely affected.

Description

經濟部智慧財產局員工消費合作社印製 478159 A7 B7__ 五、發明說明（< ) 本發明掲示一種具有差動放大器之積體半導體電路，包 含兩個輸入電晶體、一電流源及負載元件。 在積體電路中，差動放大器大致可使用在不同應用尤 其最近世代半導體記億體模組（memory module)由於更新 技術而需要較低内部電源電壓（internal supply ν ο 1 t a g e )。習用輸人信號放大器也稱為輸入接收器（i n p u t r e c e i v e r> )及以反相器之形式形成，不再能完全滿足在所 降低電源電壓範圍内作業，因為在一些實例中信號過渡狀 態（signal transition)不能再可靠地檢測。差動放大器 之基本設計具有高輸入電阻，和反相器相同。因為差動放 大器甚至要以較低輸入電源電壓來作業，其可在應用中使 用為輸入接收器。其功能在於撿測變動之輸入信號，且適 當地放大信號。 原理上，不同設計之差動放大器具有習知型式之相同基 本電路。該基本電路包含兩個輸入電晶體、一電流源及 主動或被動負載（active and passive load)。在兩個輸 入電晶體處所出現兩個輸入信號間的電位差（potential d i f f e r e n c e )，造成在差動放大器之輸出處電位的變化。 輸入電晶體通常設計使用NM0S技術。比較PM0S電晶體， 該輸入電晶體通常具有更高增益及需要較小空間。 在DRAM型式之半導體記億體中，尤其，差動放大器原則 上早已使用做為信號産生器（signal generator)。通常， 後者在作業期間具有很小輸入信號電位變動（P 〇 t e n t i a 1 -3 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) • n ϋ ϋ ϋ 一：口、 ϋ ϋ ϋ —.1 ϋ 1 ϋ ^78159 A7 ^_E__ 五、發明說明（> ) f luc tuat ion)。和在輸入接收器之作業期間相對比，通常 可見到較高輸入信號電位變動。 ------------β裝—— (請先閱讀背面之注意事項再填寫本頁) NM0S電晶體通常形式在具有P導電性型之基本摻雜的 基體（s u b s t r a t e )。因而，其定位具有以η導電性型個別 慘雜之汲極端及源極端的區域、以及具有閘極端之通道 (c h a η n e 1 )。在通道下側之基體通常包含電晶體之第四端， 其也稱爲大塊（b u 1 k )端。該電極具有控制動作和閘極相 同。通常，其控制動作不使用，而其及源極電極連結到相 同電位。 經濟部智慧財產局員工消費合作社印製 NM0S電晶體所形成之基體通常連接到積體霞路之固定 參考地電位。如果電晶體沒有電氣隔離積體電路之其餘 基體，因而其大塊端同樣地在參考地電位。爲避免控制作 用，根據上述說明，源極電極端必需同樣地連接到參考地 電位。如果所連接到輸入電晶體之閘極端的差動放大器 輸入信號具有高電位變動，則在所連接到差動放大器之電 流源的電晶體源極端處，由於在閘極及源極電極間之電容 性耦合也同樣地可見升高的電位差。因爲大塊端連接到 固定參考地電位，因此在大塊端及源極端之間產生升高的 電位差。本作用也稱爲本體-源極效應（body effect )。 由於大塊-源極效應電晶體之臨限電壓（t h r e s hold》 vo 1 t age)改變。如此不良地影響差動放大器之切換行爲 (s w i t e h i n g be h a v i p r ),例如因爲輸入電晶體之過渡狀態 行爲的改變。 本發明之目的在提供一種具有差動放大器之電路裝置， -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478159 Α7 Β7 五、發明說明（4) 其降低上述差動放大器之不良切換行爲。 本發明之目的根據申請專利第1項之特徵之半導體電 路來獲得，較佳設計及開發之特徵在申請專利範圍附屬項 說明。 半導體電路具有上述基本電路的差動放大器。NMOS型 之至少一輸入電晶體形成P導電性型之井部),用於 其部份配置在同樣Ρ導電性型之基體。具有個別汲極及 源極端之區及在該兩區之間的通道也配置在井部。井部 和基體電氣.絕緣，具有連接到源極端之井部端。如此確保 大塊處之電位等於在源極端處之電位，因而，避免大塊源 極效應。 因爲在差動放大器之基本電路中，輸入電晶體的源極端 連接到電流源，所以電流源端沒有連接到積體電路之固定 參考地電位。相對比之，通常積體電路之基體固定地連接 到參考地電位。因此，需要自基體來電氣絕緣適當輸入電 晶體以及其大塊端。如此使得電晶體之大塊端能連接到 源極端。 本發明適用於任何所期望使用差動放大器之半導體電 路。通常，如此和基體絕緣之NMOS電晶體可有利地使用. 在由晶體源極端處能看到很大電位變動的電路。如所述， 該電路包括使用爲輸入接收器之差動放大器。在輸入信 號端處之大變動電位不會造成大塊源極效應，因而不會不 良地影響差動放大器之交換行爲。 本發明參照詳細附圖在下文中更詳細說明，其中： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) ϋ ϋ ·ϋ 1 I n^OJ — — — — — — — 經濟部智慧財產局員工消費合作社印製 478159 A7 B7 五、發明說明（4) 第1圖表示差動放大器之基本結構； 第2圖表示第1圖之NMOS輸入電晶餅的橫剖面圖示； •第3圖表示具有絕緣輸入電晶體之差動放大器結構圖 示；及 第4圖是第3圖之絕緣N Μ 0 S輸入電晶體的橫剖面圖示。 第1圖所示差動放大器1 〇之基本電路，包含輸入電晶 體Τ 1及Τ 2、及電流源3 0及電流鏡形式之負載元件2 0。 差動放大器1 0以負載元件2 0來連接到內部電源電位ν 1、 及以電流源3 0來連接到積體電路之參考地電位GND。差 動放大器1 0之輸入信號1出現在輸入電晶體Τ1之閘極 端G處；例如，參考電位施加到輸入電晶體Τ2之閘極端。 在本情形中，差動放大器1 〇之輸出信號4端連接在負載 元件2 0及電晶體Τ1之間。 第2圖表示第1圖所使用電晶體Τ1及Τ2之橫剖面圖。 所示是NMOS型電晶體，該電晶體形成在Ρ導電性型之基 體SP。區η 1及η 2分別連接到電晶體之汲極端D及源極 端S。閘極端G施加在通道n k上側。區η 1及η 2具有η 導電性型。通道nk形成所謂反相器層。更進一步，在本· 實施例中基體Sp具有一端，其對應電晶體之大塊端B ° 基體Sp連接到積體電路之固定參考地電位GNP，尤其爲 了避免寄生電流通過導電性Ρ η接面（P n j u n c t i ο η ) ° 第1圖中，如果在作業期輸入信號1具有高電位變動， 則節點k同樣地因輸入電晶體Τ 1之閘電極及源電極間之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 ^/^159 A7 B7 五、發明說明（r ) 電容性耦合而造成受到很高電位變動。因爲後者之大塊 端B連接到固定參考地電位GND ,電壓UBS可在大塊端B 及源極端S觀看，其電壓大小大於零。在大塊及源極端之 間的電位差異導致上述大塊-源效應。 第3圖表示一種差動放大器10,其基本結構對應第1圖 所示差動放大器。相對照後者，電晶體T 1及T 2之大塊端 連接到個別源極端。 第4圖所示是第3圖所使用電晶體T1或T2之一的橫 剖面圖.N Μ 0 S電晶體現在不再直接施加到基體S p ,而是配 置在Ρ導電性型之井部Wp，井部Wp以絕緣層I和基體Sp 電氣絕緣。絕緣層I 1具有導電性型，而且連接到內部電 源電位V1。如此使得NMOS電晶體之大塊端B能和積體 電路之基體Sp的基體端SA隔離。更進一步基體Sp連接 到固定參考地電位GND。爲了確保井部Wp之電位和在電 晶體之源極端S處電位相同，井部端B連接到源極端S ° 大塊-源效應因此有效地避免。爲了確保井部WP之電位 和電晶體之源極端處的電位相同，井部端B連接到源極端 S。大塊-源效應因此有效地防止。 符號之說明 (請先閱讀背面之注意事項再填寫本頁) 0 ^1 11 ϋ ϋ i^i 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478159 A7 B7__ V. Description of the invention (&); The present invention shows an integrated semiconductor circuit with a differential amplifier, which includes two input transistors, a current source and a load element. In integrated circuits, differential amplifiers can be used in different applications, especially in recent generations of semiconductor memory modules, which require lower internal supply voltages (internal supply ν ο 1 t a g e) due to newer technologies. The conventional input signal amplifier is also called an input receiver (input receiver) and is formed in the form of an inverter, which can no longer fully satisfy the operation within the reduced power supply voltage range, because in some examples the signal transition state (signal transition ) Can no longer be detected reliably. The basic design of the difference amplifier has a high input resistance, which is the same as the inverter. Because the differential amplifier is even required to operate with a lower input supply voltage, it can be used as an input receiver in applications. Its function is to detect the changing input signal and appropriately amplify the signal. In principle, differential amplifiers of different designs have the same basic circuit of a known type. The basic circuit consists of two input transistors, a current source, and active and passive loads. The potential difference between the two input signals (potential d i f e r e n c e) appears at the two input transistors, causing a change in the potential at the output of the differential amplifier. Input transistors are usually designed using NMOS technology. Comparing PMOS transistors, this input transistor usually has higher gain and requires less space. Among the DRAM-type semiconductor memory devices, in particular, differential amplifiers have long been used as signal generators in principle. Generally, the latter has a small input signal potential variation during operation (Potentia 1 -3-this paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm)) (Please read the precautions on the back before filling This page) • n ϋ ϋ ϋ 1: mouth, ϋ ϋ ϋ —.1 ϋ 1 ϋ ^ 78159 A7 ^ _E__ 5. Description of the invention (>) f luc tuat ion). Compared with the operation period of the input receiver, higher input signal potential changes are usually seen. ------------ β package—— (Please read the precautions on the back before filling this page) NM0S transistor is usually in the basic doped matrix (s u b s t r a t e) with P conductivity type. Therefore, it is positioned to have regions of the drain terminal and the source terminal that are individually miscellaneous with the η conductivity type, and a channel with a gate terminal (c h a η n e 1). The substrate on the underside of the channel usually contains the fourth end of the transistor, which is also called the bulk (b u 1 k) end. This electrode has the same control action as the gate. Normally, its control action is not used, and it and the source electrode are connected to the same potential. The substrate formed by the NM0S transistor printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is usually connected to the fixed reference ground potential of Xialu Road. If the transistor does not electrically isolate the rest of the substrate of the integrated circuit, its bulk terminal is likewise referenced to ground potential. To avoid control, according to the above description, the source electrode terminal must also be connected to the reference ground potential. If the input signal of the differential amplifier connected to the gate terminal of the input transistor has a high potential variation, at the transistor source terminal of the current source connected to the differential amplifier, the capacitance between the gate and the source electrode Sexual coupling is similarly seen with increasing potential differences. Because the bulk terminal is connected to a fixed ground reference potential, an increased potential difference is generated between the bulk terminal and the source terminal. This effect is also known as the body effect. The threshold voltage of the bulk-source effect transistor (t h r e s hold >> vo 1 t age) changes. This adversely affects the switching behavior of the differential amplifier (sw i t e h i n g be h a v i p r), for example because of a change in the behavior of the transition state of the input transistor. The purpose of the present invention is to provide a circuit device with a differential amplifier. -4-This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 478159 Α7 B7 5. Description of the invention (4) It reduces the above Bad switching behavior of the differential amplifier. The purpose of the present invention is obtained based on the semiconductor circuit with the features of the first item of the patent application. The features of better design and development are described in the appended items of the patent application scope. The semiconductor circuit has a differential amplifier having the basic circuit described above. At least one input transistor of the NMOS type forms a well portion of the P conductivity type), and is used for a part of which is arranged on a substrate of the same P conductivity type. A region having individual drain and source terminals and a channel between the two regions are also disposed at the well portion. The well section and the substrate are electrically insulated and have a well section end connected to the source terminal. This ensures that the potential at the bulk is equal to the potential at the source terminal, thus avoiding the bulk source effect. Because in the basic circuit of the differential amplifier, the source terminal of the input transistor is connected to the current source, the current source terminal is not connected to the fixed reference ground potential of the integrated circuit. In contrast, the base of an integrated circuit is usually fixedly connected to a reference ground potential. Therefore, it is necessary to properly insulate the input transistor and its bulk terminal from the substrate for electrical insulation. This allows the bulk terminal of the transistor to be connected to the source terminal. The present invention is applicable to any semiconductor circuit in which it is desired to use a differential amplifier. Generally, an NMOS transistor thus insulated from the substrate can be used to advantage. Circuits with large potential fluctuations can be seen at the extremes of the crystal source. As mentioned, the circuit includes a differential amplifier used as an input receiver. The large fluctuation potential at the input signal terminal will not cause a large source effect, so it will not adversely affect the exchange behavior of the differential amplifier. The present invention will be described in more detail below with reference to the detailed drawings, in which: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297) (please read the precautions on the back before filling this page) ϋ ϋ · ϋ 1 I n ^ OJ — — — — — — — Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478159 A7 B7 V. Description of the invention (4) Figure 1 shows the basic structure of the differential amplifier; Figure 2 shows the first structure Cross-section diagram of the NMOS input transistor cake; Figure 3 shows the structure of a differential amplifier with an insulated input transistor; and Figure 4 is a cross-section of the insulated N M 0 S input transistor of Figure 3 Icon. The basic circuit of the differential amplifier 10 shown in Fig. 1 includes input transistors T1 and T2, and a current source 30 and a load element 20 in the form of a current mirror. The differential amplifier 10 is connected to the internal power supply potential ν 1 with a load element 20 and to the reference ground potential GND of the integrated circuit with a current source 30. The input signal 1 of the differential amplifier 10 appears at the gate terminal G of the input transistor T1; for example, a reference potential is applied to the gate terminal of the input transistor T2. In this case, the 4 terminal of the output signal of the differential amplifier 10 is connected between the load element 20 and the transistor T1. Fig. 2 shows a cross-sectional view of the transistors T1 and T2 used in Fig. 1. Shown is an NMOS type transistor which is formed on a substrate SP of the P conductivity type. Regions η 1 and η 2 are connected to the drain terminal D and the source terminal S of the transistor, respectively. The gate terminal G is applied on the upper side of the channel n k. The regions η 1 and η 2 have an η conductivity type. The channel nk forms a so-called inverter layer. Furthermore, in this embodiment, the base body Sp has one end, which corresponds to the bulk end B of the transistor. The base body Sp is connected to the fixed reference ground potential GNP of the integrated circuit, in particular to prevent parasitic currents from passing through the conductive P η junction. (P njuncti ο η) ° In the first figure, if the input signal 1 has a high potential variation during the operation period, the node k is similarly applied to the Chinese paper standard due to the paper size between the gate electrode and the source electrode of the input transistor T 1 (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ / ^ 159 A7 B7 V. Description of Invention (r) Capacitor Sexual coupling causes high potential changes. Because the bulk terminal B of the latter is connected to the fixed reference ground potential GND, the voltage UBS can be viewed at the bulk terminal B and the source terminal S, and its voltage is greater than zero. The potential difference between the bulk and source extremes results in the bulk-source effect described above. FIG. 3 shows a differential amplifier 10 whose basic structure corresponds to the differential amplifier shown in FIG. In contrast to the latter, the bulk terminals of the transistors T 1 and T 2 are connected to individual source terminals. Figure 4 shows a cross-sectional view of one of the transistors T1 or T2 used in Figure 3. The NM 0 S transistor is no longer directly applied to the substrate S p but is arranged in the well portion of the P conductive type. Wp and well portion Wp are electrically insulated by the insulating layer I and the substrate Sp. The insulating layer I 1 has a conductivity type and is connected to an internal power supply potential V1. This allows the bulk terminal B of the NMOS transistor to be isolated from the base terminal SA of the substrate Sp of the integrated circuit. Furthermore, the substrate Sp is connected to a fixed reference ground potential GND. In order to ensure that the potential of the well portion Wp is the same as the potential at the source terminal S of the transistor, the well terminal B is connected to the source terminal S °. The bulk-source effect is effectively avoided. To ensure that the potential of the well section WP is the same as the potential at the source terminal of the transistor, the well terminal B is connected to the source terminal S. Bulk-source effects are therefore effectively prevented. Explanation of symbols (Please read the notes on the back before filling out this page) 0 ^ 1 11 ϋ ϋ i ^ i Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

11 T SB 晶 電 入 輸 器 大件 放元源 動載»f 差負電 端 極 閘 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478159 A7 B7 五、發明說明（^11 T SB Transistor Power Input Unit Large-scale Source Source Dynamic Load »f Differential Negative Electric Terminal Gate This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 478159 A7 B7 V. Description of the invention (^

Sp...基體 B...大塊端 V 1 ...內部電源電位 GND..·參考地電位 --------------裂--- (請先閱讀背面之注意事項再填寫本頁) . -線· W I 丨才 t h 肖 Ψ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Sp ... substrate B ... bulk terminal V 1 ... internal power potential GND .. · reference ground potential -------------- crack --- (Please read the back first Please pay attention to this page, please fill in this page). -Line · WI 丨 cath Xiao Xiao This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

478159 A8 B8 C8 D8 六、申請專利範圍 1· 一種具有差動放大器（10)之積體半導體電路，包含兩個 輸入電晶體（T1，T2), —電流源（30)及一負載元件（20)， 具有下列特徵； -至少該輸入電晶體（Τ1，Τ2)中之一具有NM0S型而 且配置在Ρ導電性型之基體（Sp )的Ρ導電性型井部（Wp )， 具有汲極端（D )之第一區（η 1 )及具有源極端（s )之第二 區U2)配置在該井部（Wp); -該井部（Wp )具有井部端（B )，而且和該基體（Sp )電 氣絕緣； -該井部端（B )連接到該源極端（S )。 2 .如申請專利範圍第丨項之積體半導體電路，其中： 該基體（S ρ )具有基體端（S A)，其連接到用該積體電路之 固定參考地電位（G N D )端。 3 ·如申請專利範圍第1或2項之積體半導體電路，其中該 差動放大器容納在該積體電路之輸入接收器的電路裝 置，及 -該輸入電晶體（T 1 )中之一的閘極端（g.)連接到用於 該輸入接收器之輸入信號（1 )端。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 — · ϋ I ϋ ϋ n ϋ ϋ 一5、I _n ϋ 1 I Hi I I —I- ϋ .1 ϋ I n n -ϋ I ϋ n ί I I ϋ ϋ n ϋ - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）478159 A8 B8 C8 D8 6. Scope of patent application 1. A integrated semiconductor circuit with a differential amplifier (10), including two input transistors (T1, T2), a current source (30) and a load element (20 ), Has the following characteristics;-at least one of the input transistors (T1, T2) has a NMOS type and is disposed in a P-conducting well (Wp) of a P-conducting substrate (Sp), having a drain terminal ( D) the first zone (η 1) and the second zone U2 with the source terminal (s) are arranged in the well section (Wp);-the well section (Wp) has a well section end (B), and The base body (Sp) is electrically insulated;-the well end (B) is connected to the source terminal (S). 2. The integrated semiconductor circuit according to item 丨 of the patent application scope, wherein: the substrate (S ρ) has a substrate terminal (S A), which is connected to a fixed reference ground potential (G N D) terminal using the integrated circuit. 3. If the integrated semiconductor circuit of item 1 or 2 of the patent application scope, wherein the differential amplifier is accommodated in the circuit device of the input receiver of the integrated circuit, and-one of the input transistors (T 1) The gate terminal (g.) Is connected to the input signal (1) terminal for this input receiver. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs — · ϋ I ϋ ϋ n ϋ ϋ 5, I _n ϋ 1 I Hi II — I- ϋ .1 ϋ I nn -ϋ I ϋ n ί II ϋ ϋ n ϋ-This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)
TW089110056A 1999-05-26 2000-05-24 Differential amplifier of an integrated semiconductor circuit TW478159B (en)

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DE19924151A DE19924151A1 (en) 1999-05-26 1999-05-26 Semiconductor integrated circuit with differential amplifier, e.g. for DRAM

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