474121 五、發明說明（1) 多單元多晶片微電子包裝 1 .摘要 本技藝是一種微型球閘陣列多單元多晶片微電子包裝，將 習知只有單晶片之微型球閘陣列包裝，以陶瓷板或是金屬 板作為背板提供散熱以及支撐功能，整合一顆以上之傳統 單晶片包裝，達成微型球閘陣列多單元多晶片微電子包 裝。 2. 背景說明 積體電路記憶體容量愈做愈大，由早期的4M、1 6M、64M到 128M或是256M，製程困難度愈來愈高，而隨著記憶體密度 的提高，產品良率即相對著降低。然而高記憶體或是高電 晶體容量等，亦可以封裝方式之改良來達成。如一顆128M 單一晶片可以由兩顆64M包裝在一起，如此相對良率可以 提高，且製程複雜度與成本也相對降低。習知技藝如圖1 A 的微型球閘陣列（micro Ball Grid Array, uBGA)所示之 單晶片微型球閘陣列包裝，都是只有單一晶片1 0的包裝， 尚未見有具有陶瓷之多單元多晶片微電子包裝之結構，圖 1B為圖1A的底面視圖，顯示單一晶片10其輸出入【I/O】474121 V. Description of the invention (1) Multi-unit multi-chip microelectronic packaging 1. Abstract This technology is a miniature ball-gate array multi-unit multi-chip micro-electronic packaging. Or a metal plate can be used as a backplane to provide heat dissipation and support functions, and integrate more than one traditional single-chip package to achieve a miniature ball brake array multi-unit multi-chip microelectronic package. 2. Background description The memory capacity of integrated circuit is getting larger and larger. From the early 4M, 16M, 64M to 128M or 256M, the process difficulty is getting higher and higher, and as the memory density increases, the product yield rate That is, relatively lower. However, high memory or high transistor capacity can also be achieved by improving the packaging method. For example, a single 128M chip can be packaged by two 64M chips, so the relative yield can be improved, and the process complexity and cost can be reduced. The single-chip micro ball grid array package shown in the micro ball grid array (uBGA) shown in Figure 1A is a package with only a single chip 10, and there are no ceramics with multiple cells and multiple packages. The structure of the chip microelectronic package, FIG. 1B is a bottom view of FIG. 1A, showing a single chip 10 whose input and output [I / O]
C:\WIND0WS\Desktop\working\8812tw.ptd 第 4 頁 474121 五、發明說明（2) 墊片1 2排列於I C周邊四邊；並以導線/導腳1 6與基材1 4上 的電路（圖中未表示）相互耦合；基材1 4另外一面以球閘陣 列1 8作為晶片1 0之輸出入延伸端，提供整個包裝耦合至外 部之印刷電路板的連接端點。晶片1 0以緩衝固定膠體 1 5 (圖1 A )固著於基材1 4上，緩衝固定膠體1 5提供晶片1 0以 及基材1 4之間因為溫度變化所產生之膨脹收縮之緩衝以及 固著功能，致使晶片1 0以及基材1 4之間的不匹配熱應力可 以降低，以便提高產品的可靠度。包裝膠體1 9，用以封裝 保護電路、導線/導腳、晶片等元件。 陶 片 一 以 是 則 藝 習板單 將屬統 ，金傳 板是之 背或上 為板以 作瓷顆 板陶一 屬以合 金，整 是裝， 或包能 板列功 瓷陣撐 閘支 球及 型以 微熱 之散 片供 晶提 技單板 明有背 發只為 本知作 以 合 整 膠 封 以 加 並 裝 包 片 晶 以 雖 明 發 本 ο 裝 包 子 電 微 片 晶 多 元裝 單包 多為 列合 陣組 閘之 球量 型容 微體 成憶 達記 以發 ，本 裝為 包亦 合 ， 組用 片應 晶換 之轉 能單 功簡 同之 不藝 於技 對一 ，此 而是 然也 明積圍 說體範 以裝利 加包權 意小之 示減明 明 說 單 簡 的 示 圖 3 圖1 Α· 圖1Β· 裝 包 列 •L 閘 球 型 微 之 片。 晶圖 單視 ， 面 藝底 技的 知1Α 習圖 為為C: \ WIND0WS \ Desktop \ working \ 8812tw.ptd Page 4 474121 V. Description of the invention (2) The gasket 1 2 is arranged on the four sides of the periphery of the IC; the wires / lead pins 16 and the circuit on the substrate 14 ( (Not shown in the figure) are mutually coupled; the other side of the substrate 14 uses the ball brake array 18 as the input and output extension of the wafer 10, providing the entire package to be connected to the external printed circuit board connection terminal. The wafer 10 is fixed on the substrate 14 with a buffer-fixing colloid 15 (Fig. 1A). The buffer-fixing colloid 15 provides a buffer for expansion and contraction between the wafer 10 and the substrate 14 due to temperature changes, and With the fixing function, the mismatched thermal stress between the wafer 10 and the substrate 14 can be reduced, so as to improve the reliability of the product. Packaging gel 19 is used to encapsulate components such as protective circuits, leads / leads, and chips. The pottery piece is the art board, the gold plate is the back or the top is the plate for the porcelain plate, the pottery is the alloy, the whole is installed, or the plate can be used to support the porcelain array. The ball and the shape use micro-heat scattered pieces for the crystal technology veneer. There is only a back hair. This is known as the whole plastic seal to add and pack the crystals to make the hair. Bao Duo is a ball-type volumetric micro-body of the array array gates. It is issued by Yi Da Ji. This equipment is packaged by Bao Yihe. The unit should be replaced by crystals. However, it is also clear that the body style is based on the presumption of the benefit and the enclosing of the right. The diagram is clearly shown in Figure 3. Figure 1 Α · Figure 1B · Packing column • L brake ball micro-chip The crystal map is a single view, and the knowledge of the surface technology is 1A.
C:\WIND0WS\Desktop\working\8812tw.ptd 第 5 頁 474121C: \ WIND0WS \ Desktop \ working \ 8812tw.ptd page 5 474121
本技藝之 散熱以及 圖2A的局 含有陶瓷板或是金 圖2A. 為 屬板提供 圖2B· 為 多早元多 支撐功能 部元件底 晶片包裝 〇 面視圖。 4 ·本發明之詳細說明 圖2 A ·為本技藝之客;夕η 屬板提供散熱以及支撐功‘ :a片包裝’含有陶究板或是金 :究=”屬，供支撐功*，將一個以上之晶片整The heat dissipation of this technique and the board of Figure 2A contain ceramic plate or gold. Figure 2A. Provide for the metal board. Figure 2B. Multi-early and multi-support function. 4 · Detailed description of the present invention Figure 2 A · This is a guest of the art; Xi η plate provides heat dissipation and support work ': a piece of packaging' contains ceramic study board or gold: study = "genus, for support work *, Integrate more than one wafer
之瞽厶A r如始口 電包裝。以兩片晶片20A， 20B 方弋：：& 日之’更多片晶片之整合可以依照相同的 20:，曰二。A陶瓷板或是金屬板27下方附著有晶片20A， 曰曰 ，2〇B不方分別對映有電路板基材24A， 24B必要時曰曰片20A， 20B並分別以緩衝固定膠體25a 2 5B分別固著於電路板基材24A, 24b。 ’ 緩衝固定膠體25A, 25B提供晶片20A, 20B以及散熱材料27 對基材24A， 24B之間因為溫度變化所產生之膨脹收縮之熱 應力緩衝以及固著功能，致使晶片20 A, 2 0B以及散熱材^ 2 7對基材2 4 A, 2 4 B之間的不匹配熱應力可以降低，以便Zhi 瞽 厶 A r is like the original electrical packing. With two wafers 20A, 20B, Fang :: & Rizhi ’integration of more wafers can follow the same 20 :, two. A ceramic plate or metal plate 27 is attached with a wafer 20A below it, that is, 20B is opposite to the circuit board substrate 24A, 24B, if necessary, it is said to be 20A, 20B, and the colloids 25a 2 5B are respectively fixed with buffers. They are fixed to the circuit board substrates 24A and 24b, respectively. '' The buffer fixing colloids 25A, 25B provide wafers 20A, 20B, and heat-dissipating materials. 27 pairs of substrates 24A, 24B due to thermal expansion and contraction due to temperature changes, thermal stress buffering and fixing function, resulting in wafers 20 A, 2 0B and heat dissipation. Material ^ 2 7 pairs of substrates 2 4 A, 2 4 B mismatch thermal stress can be reduced in order to
高產品的可靠度。 BHigh product reliability. B
474121 五、發明說明（4) --- 陶瓷板或是金屬板2 7提供支撐以及散熱功& ;印刷電路板 基材24A， 24B分別以導線/導腳26A， 26B耦合電路於晶片 20A， 20B周邊的輸出入【1/〇】墊片22A， 22B ;印刷電路 板基材2 4 A， 2 4 B的另外一面，分別以球閘陣列2 8 A, 2 8 B作 為晶片20A, 20B之輸出入延伸端。 緩衝固定膠體25A, 25B，可以依據產品可靠度要求之高 低，而選擇使用或是省略不用。 緩衝固定膠體25A， 25B也可以是一個整體定膠一次同時固 定晶片20A， 20B。緩衝固定膠體25Α， 25Β&可以是多個分 離之小團膠體，分別固定或是一次整體固定晶片2 〇 a , 20B 〇 本產品也可以附加包裝膠體2 9，封裝保護個別晶片單元之 電路、晶片20A， 20B、導線/導腳26A， 26B等元件，也隔 絕空氣使得元件不會吸收空氣中的水分，以提高產品的可 靠度。 圖2B.為圖2A的局部元件底面視圖。 陶瓷板或是金屬板2 7下方黏著有晶片20八，208，晶片20八， 20B兩邊具有輸出入【I/O】墊片22A， 22B，實際設計時， 也可以是四邊具有輸出入【I/O】墊片，視需要而定。印474121 V. Description of the invention (4) --- Ceramic plate or metal plate 2 7 Provide support and heat dissipation work & Printed circuit board substrates 24A, 24B are coupled to the chip 20A with wires / leads 26A, 26B, I / O around 20B [1 / 〇] pads 22A, 22B; the other side of the printed circuit board substrate 2 4 A, 2 4 B, using the ball brake array 2 8 A, 2 8 B as the chip 20A, 20B I / O extension. The buffer fixing colloids 25A and 25B can be selected or omitted according to the reliability requirements of the product. The buffer fixing colloids 25A and 25B may also be integrally fixed and fixed the wafers 20A and 20B at one time. The buffer fixing colloids 25A, 25B & can be multiple separate small colloids, which can be fixed separately or fixed as a whole wafer 2 〇a, 20B 〇 This product can also be packaged with colloid 29, which protects the circuits and wafers of individual chip units. 20A, 20B, wire / lead pins 26A, 26B and other components, also isolated from the air so that the components will not absorb moisture in the air to improve product reliability. FIG. 2B is a bottom view of a part of FIG. 2A. The ceramic plate or metal plate 27 has wafers 20,208 on the two sides, and the wafers 20 and 20B have I / O pads 22A and 22B on both sides. In actual design, it can also have I / O pads on the four sides. / O] gasket, as required. Seal
C:\WIND0WS\Desktop\working\8812tw.ptd 第 7 頁 —- S喊 881Q547R__^_jg_日 __修正 _ 五、發明說明（5) — ^ ' '一"· 席J電路板基材24A，24B(圖2A)的一面異有電路，並且以導 線/導腳26柄合電路於晶片20A，20B兩邊之輸出入【I/O】 墊片 22A， 22B。 修炽 正％ i:. ::夕' Λ =述，述揭不了本發明之較佳實施例以及設計圖式，惟， 1佳實施例以及設計圖式僅是舉例說明’並非用於限制 發明技藝之權利範圍於此，Α是以均等之技藝手段、或是 二下述之「申請專利範圍」戶斤涵蓋之權利範圍而實施者， 均不脫離本發明之精神而為申請人之權利範圍。 5 ·元件編號表 晶片 10，20Α， 20Β 輸出入墊片12, 22Α，22Β 基材 14, 24Α，24Β 緩衝固定膠15, 25Α，25Β 導線/ 導腳 1 6, 26, 26Α，26Β 球閘陣列18, 28Α，28Β 包裝膠體19, 29 陶瓷板或是金屬板2 7C: \ WIND0WS \ Desktop \ working \ 8812tw.ptd page 7—-S shout 881Q547R __ ^ _ jg_ 日 __correct_ V. Description of the invention (5) — ^ '' 一 " · J J circuit board substrate 24A There is a circuit on one side of 24B (Fig. 2A), and the wires / lead pins 26 handle the circuit on both sides of the chips 20A, 20B. The input and output [I / O] pads 22A, 22B. Xiu Zhengzheng i :. :: Xi 'Λ = description, can not disclose the preferred embodiment and design drawings of the present invention, but the 1st embodiment and design drawings are only examples, not for limiting the invention The scope of the right of technology is here, and A is implemented by equal means of technology or the scope of rights covered by the following "patent application scope", which does not depart from the spirit of the invention and is the scope of the applicant's rights . 5 · Component No. Table Wafer 10, 20A, 20B I / O pads 12, 22A, 22B Base material 14, 24A, 24B Buffer fixing glue 15, 25A, 25B Wire / Guide 1 6, 26, 26A, 26B Ball brake array 18, 28Α, 28Β Packaging colloids 19, 29 Ceramic plate or metal plate 2 7
2000.12. 27. 0082000.12. 27. 008