TW471131B - Etching method for dual damascene pattern - Google Patents

Abstract

The present invention relates to an etching method for forming dual damascene pattern in the dielectric, and especially to an etching method for a mixed type of dielectric with the organic low-K dielectric on the upper layer and the chemical vapor deposition dielectric on the lower layer. The method comprises the following steps: first, providing a substrate which is a stack structure with at least a first dielectric/an etching stop layer/a second dielectric from the bottom to the top in which the first dielectric has a wiring formed therein; next, using the photolithography and partial etching techniques to transfer the wiring trench pattern to the hard mask (without opening); then, using another photoresist patterning and etching techniques to define the via hole pattern on the hard mask (opening via hole pattern) to expose or partially etch the second dielectric; after removing the photoresist, etching the hard mask (opening wiring trench pattern); through the residual hard mask, continuously etching the second dielectric to form the dual damascene in the second dielectric; finally, etching through the etching stop layer to expose the wiring.

Description

471131 V. Description of the invention (1) Field of the invention: The present invention discloses a technology related to the manufacturing of semiconductor elements, in particular: a technique for performing a dual damascene pattern etching process with a hard mask is suitable for using an organic low-k dielectric layer as The dual damascene etching technology of the upper and lower chemical vapor deposition constant dielectric layers is a mixed layer of the lower layer, or the dual damascene etching technology mainly composed of organic low dielectric constant dielectric layers. Background of the Invention: In addition to the purpose of making the integrated circuit in the chip smaller than the density of the chip and reducing the unit cost, the end of the component is more critical. In addition to the design of the transistor component itself, it is finally connected with metal wires and even The dielectric layer between the interconnects is an important factor that affects the components. This is because the resistance value R of the wire, there will be a capacitor C between the upper wire and the wire and the adjacent wire. As we all know, the lower the RC value is, the lower the time delay is. It has become a trend to use copper instead of aluminum for front interconnects. Change the dielectric layer between interconnects to a low dielectric constant layer to reduce parasitics and increase speed. No doubt, it has become the goal of the current semiconductor industry. Commonly used low dielectric constant dielectric layers can be mainly divided into a layer with a low dielectric constant (1 ow-k) formed by the spin-on glass method, such as ρ ο 1 ymer or silicon-oxygen-based spin-on coating. Silicate glass (siloxane-based S0G) or SiLK, FLare, H0SP, etc.

It ’s all about ‘special low-level dielectrics’. They ’re all connected to the performance of the speedometer 7, which is the lower level of the MEMS support. Therefore, the two types of capacitors can be pursued together.

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471131 V. Description of the invention (2), the other is 10w »k 丨 black diamond deposited by chemical vapor deposition; Coral, etc. Generally speaking, if the dielectric layer is all based on silicon dioxide of chemical vapor deposition method, when the dual damascene process is performed, it is mostly performed by an etching gas containing fluorine. Therefore, unless the hole size of the dielectric layer is very small, it is not easy to do so. An additional hard mask is required on the dielectric layer. For example, as shown in FIG. 1, a photoresist pattern 30 of an etching mask defining a via hole (via ho 1 e) is first formed, the dielectric layer 20 is etched, and a liner layer (Π ning 1 ayer) or the termination layer 5 stops. Next, as shown in FIG. 2, another photoresist pattern 40 defining the wire trench is formed on the dielectric layer 20 to etch the dielectric layer I, and at the same time backfill the hole of the dielectric layer. When the engraved termination layer 15 in the dielectric layer is engraved, the photoresist is finally removed as shown in FIG. 3 to expose the lining layer 5 in the dielectric hole at the same time, and then the lining layer is named lining. layer) 5 to expose the metal wires 3. However, please refer to FIG. 4 if the dielectric layer 20 is a low-k organic dielectric layer, such as SiLK, or the dielectric layer 20 is a mixed layer. That is, the part that is used as the wire trench is Si LK, and the lower layer that is used as the interlayer hole is the oxide stone or inorganic acid salt deposited by chemical vapor deposition. The double-hard mask (for example, ___ one, one, one, one, one, one, one, etc.) is a commonly used etching mask. The first is to prevent Si LK and photoresist contact. The use of mixed layers is mainly based on thermal stability considerations and mechanical stress considerations. In terms of thermal stability considerations, although the Si LK flatness is better, the heat dissipation is not as good as that of silicon oxide or inorganic silicate.

Page 5 471131 V. Description of the invention (3) ^^ ______ The heat dissipation can be improved by about 30-40%. In terms of machinery, purely J low-k organic dielectric and electrical layers are too thick. If the application method of force grinding is considered, the problem of cracking will be stabilized. Chem./ earning machine. Vm ": However, because of the oxide stone deposited by chemical vapor deposition method, the fluorine-containing gas is generally used to etch, and this is the same as the above The selectivity is very low. Therefore, it can be predicted that the metal wires to be connected to the double-rigid hood are close to the consumer stage j and are not etched to a disadvantage. In view of the problems described above, the present invention will provide a method to solve the problem. The purpose and summary of the invention are as follows: The dielectric YT is intended to provide a method of forming a double mosaic pattern on an organic layer of p " electrical layer on top and a chemical vapor deposition (ICVD) iow κ layer, # by the present invention Cover: The double-mosaic pattern fails due to the insufficient hard selection ratio in the etch selection b 13 Baizhi technology. 'The present invention discloses a method such as the Zhongqi country method, particularly an organic (10H Λ t electric layer with the remaining squares below the "mixed-type dielectric", and a U⑽ 骖 pore oxide layer formed by chemical vapor deposition, Due to: 471131 V. Description of the invention (4) Dimensions require hard mask etching. The steps of the present invention include at least the following steps: First, a substrate is provided, and the substrate is at least a first dielectric layer from bottom to top / Surface-cut stop layer / Second dielectric layer stack structure, where the first dielectric layer has a conductive line formed therein; then, the lithography and partial etching techniques are used to define the conductive line trench pattern on the hard mask. After that, Then another lithography and lithography technique is used to first open a hole pattern on the hard mask layer, and then etch to form a hole in the second dielectric layer. After removing the photoresist, the hard mask is then etched. To form a wire trench pattern exposing the second dielectric layer, and continue to etch the second dielectric layer through the hard mask to form a dual damascene pattern in the second dielectric layer, and finally etch through the etch stop layer to expose the wires. Hard mask etching The timing of etching termination is controlled by time mode. Detailed description of the invention: The main idea of the present invention is to apply a single mask with a high etching selectivity to the relative oxide layer on the dual mosaic pattern. The medium-layer Hqw κ organic dielectric layer, the low-K organic dielectric layer and the CVD dielectric layer are double-etched masks, or the double-damascene pattern of the θ and size dielectric layers faces high depth and width The problem of ratio limitation. Please refer to the cross-sectional diagram shown in Figure 4. First prepare a substrate. The substrate must be at least the first dielectric layer 100/1/1 etch stop layer 11 0 / second dielectric layer 1 2 from bottom to top. 0, in which a first dielectric layer 100 and a wire 105 are formed therein. A hard mask layer 130 is then deposited on the second dielectric layer.

471131 Fifth, the description of the invention (5) on 120. Then, the positions of the lead trenches are defined by the photoresist pattern 140. The above-mentioned etch stop layer II0 may be a silicon nitride layer or a silicon carbide layer. The second dielectric layer 120 may be a low-k organic dielectric layer, such as Pol ymer or siloxane-based SO G or SiLK, One of FLare, etc., or one of the organic dielectric layers such as SiLK, FLare is the upper dielectric layer, and one of the silicate, black diamond, or oxide layer deposited by chemical vapor deposition is the lower dielectric. A hybrid layer of electrical layers. Secondly, if there is an etching stop layer between the organic dielectric layer and the CVD oxide layer, the same is possible: f: the hard mask layer 130 can be a silicon nitride layer, silicon nitride oxide or carbon cutting, etc.-etc. The choice of emulsification etching is better than that of the other. ^〗 丨 The electricity increase is good if it is 2 0 0-4 0 0 0 Angstrom / shell. For the thickness of the hard mask layer 130, please refer to Figure 5 and Figure 140. Mask 140 is used to etch a hard cross-section. Then, a photoresist pattern is used to form a wire diffuser mask 130. Please note that the '\ steps only need to partially open the hard mask pattern 1 30A', that is, do not (acoustic erosion through) (or not to etch using the etching time control. In a preferred embodiment, this You can choose the appropriate time to complete the electricity. Please refer to the chart in Figure 6, to explain the depth and time line as long as the curtain, such as CH 〆〇〆Ar touches the above-mentioned hard cover 26 6 / zm wire trench trench relationship. For example Small since 0 2 / zm, as large as 0. Therefore, the wider the wire channel, the uniformity will not be affected.

Page 8 471131 V. Description of the invention (6) 彳 1 General: ^, N 2 / Hf 2 2/0 thin etching gas etch Si to etch the hard mask, the etching selection ratio is very high, about 30: 1 Therefore, the thickness of the original hard mask 130 is about 2000 angstroms to 30,000 angstroms, which is sufficient. The hard mask 13 only needs to retain a thickness of about 300 to 800 angstroms in the above-mentioned etching step. . In terms of ^ =, the remaining hard mask 13 is left. Can be used as anti-reflection coating 5 Angstroms, otherwise only a hard mask 13 to 300 Angstroms thick can be left. If the lower layer of the second dielectric layer 120 is black diamond or oxidized, the vermiculite ^ black diamond or licetic layer chemically vapor-deposited from the layer structure 4 shall use fluorine-containing etching gas. In contrast, the etching selection ratio between hard mask and chemical deposition is about i d 〇. Therefore, the thickness of the original hard mask 130 needs to be about 35,000 angstroms to 4,000 angstroms thicker. At this time, the hard mask 130 needs to retain about 300-800 angstroms in the above-mentioned etching step. Thickness / whether to use the remaining hard mask 130 as an anti-reflection coating. Remove the photoresist pattern 1 4 0 with 1. Now refer to the schematic cross-sectional view of Figure VII, and then form another pattern 1 50 on the belt. The hard mask with a wire channel pattern is red. The photoresist pattern 150 is a mask, and the etching of the hard mask 130A is used to etch the hard mask 130A. The hard mask 13B shown is completed. The dielectric pattern is etched, and the second dielectric layer 12 is exposed. 9/11 Please refer to the schematic cross-sectional view of FIG. 8 and describe as follows. The photoresist pattern 150 is removed first, and then the mask is etched with a hard mask. , '/, / ^-；; " ··' 'ψ 1, Ν V.!. ^ 471131 V. Description of the invention (7) N 2/0 舁 etching gas or fluorine-containing etching gas etc. Dielectric layer 1 2 0 to form a dielectric hole 16 0. Please note that if the second dielectric layer 1 2 0 is a material of 10 watt-k organic dielectric layer The previous photoresist pattern 150 may not need to be removed first, because if N2 / 0 is used as the etching gas for the low-k organic dielectric layer, the photoresist pattern 1 50 will be etched at the same time as the hole 160 in the interlayer is etched. Melt and remove at the same time. The etching step of the dielectric hole 160 can control the time) mode, or use a # etch stop layer in the middle of the dielectric layer 120 (not shown in Figure 8 but similar to Figure 1) Please refer to the schematic diagram of the cross section shown in Figure IX, and then use CH2F2 / 02 / Ar etching gas to etch the hard mask 1 30B to form a hard mask with a wire trench pattern 1 3 0 C, (If there is an etch stop layer in the dielectric layer 120 as the etch stop layer of the wire trench, this step can also etch through the etch stop layer at the same time.) Please refer to the cross-sectional diagram shown in FIG. N 2 / Η or N 2/0 salt or fluorine-containing etching gas, etc., etch the second dielectric layer 1 2 0 and continue to etch the wire trenches and via holes until the etch stop layer 11 0. This part can also be controlled by time Method, or add an etch stop layer (not (Shown) to control the end of the etched wire trench. Finally, as shown in Figure 11, the plasma gas of the etch stop layer is also used, for example ([1 疋 2 / 〇2 / 八 1 'etch stop layer 110 to complete The last double mosaic pattern is engraved.

Page 10 471131 V. Description of the invention (8) Although the above-mentioned embodiments are not limited, the size of the via hole applicable to the system is, for example, 0.1 5 / z m or less. However, traditionally, if a dielectric layer deposited by a chemical vapor deposition method can define a via hole by a photoresist pattern and etch, as described in the background of the invention. However, the photoresist needs to be backfilled after the via hole is etched to protect i: The metal wires below can be used to define the wire trench with another photoresist pattern. At this time, the backfill photoresistor of the too small via will have a high depth. limit. Therefore, I still have to use a hard screen. In the hard mask of the present invention, part of the etching concept does not limit the situation of extremely small interlayer holes. Therefore, the present invention is also applicable to a dielectric layer deposited by a chemical vapor deposition method and the interlayer hole has a very small size. example of. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included below Within the scope of the patent mentioned in the application ii.

Page 471131 The diagram briefly illustrates the preferred embodiment of the present invention and will be explained in more detail in the following explanatory text with the following figures: Fig. 1 shows the etching of interconnects using a photoresist pattern as a mask according to the traditional method A schematic cross-sectional view of a dielectric layer to form a dielectric hole. Figure 2 shows that the cross-section of an interconnect dielectric layer is etched with another photoresist pattern as a mask to form a wire trench according to the conventional method. Please note that the interlayer hole is backfilled with a photoresist pattern to protect it Under the metal wire. Figure 3 shows a schematic cross-sectional view of the etched backing layer after photoresist removal by conventional methods. FIG. 4 is a schematic cross-sectional view of a photoresist pattern formed on a hard mask according to the method of the present invention to define a position of a wire trench. FIG. 5 is a schematic cross-sectional view of etching a wire trench to transfer a photoresist pattern to a hard mask according to the method of the present invention. Fig. 6 shows a linear relationship between the etching hard mask and time according to the method of the present invention. FIG. 7 is a schematic cross-sectional view of a method according to the present invention, defining a via hole with a photoresist pattern, and then etching to form a via hole. FIG. 8 shows a schematic cross-sectional view of a via hole in a hard mask with a via hole opening # in accordance with the method of the present invention. Fig. 9 is a schematic cross-sectional view of etching a hard mask to form a wire trench opening according to the method of the present invention. FIG. 10 is a schematic cross-sectional view of forming a wire trench and a via hole using a hard mask as an etching mask according to the method of the present invention. Figure 11 shows a cross-section of an etched backing layer according to the method of the present invention

Page 12 471131 Schematic illustrations Schematic. Drawing number comparison table: Dielectric layer 20 Lining layer 5 First dielectric layer 100 Metal wire 3, 105 Etched stop layer 15, 110 Second dielectric layer 120 Hard mask layer 130 Photoresist pattern 30, 40, 140, 150 Hard mask layer (with wire trench etch pattern) 130A Hard mask layer (with wormhole pattern 1) 130B via hole 160 Wire trench 170

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Claims (1)

471131 VI. Scope of patent application 1. A method for etching a dual-mosaic pattern, the method includes at least the following steps: A substrate is provided, and the substrate is at least a first dielectric layer / etch stop layer / second dielectric layer stack from bottom to top Structure, in which the first dielectric layer and a wire are formed therein, and the second dielectric layer is all organic 10w K dielectric layer, or all pores 100w K dielectric of chemical vapor deposition Layer, or an organic 1 ow K dielectric layer on top and a chemical vapor deposition dielectric layer on the lower one; forming a photoresist pattern defining a wire channel on the hard mask; partially etching the hard mask layer Using the photoresist pattern as a mask to transfer the wire trench pattern in the photoresist pattern to the hard mask without exposing the second dielectric layer; removing the photoresist pattern; forming a hole defining the dielectric layer A photoresist pattern is formed on the hard mask; the hard mask is etched to form a via hole opening, and the second dielectric layer 9 is etched through the via hole opening to form a via hole in the hard mask. The resist pattern is a mask; Residual photoresist pattern; Etching the hard mask so that the wire trench pattern continues to be etched to expose the second dielectric layer underneath; using the residual hard mask to etch the second dielectric layer to Forming a conductive line trench in the second dielectric layer, and exposing the etching stop layer to the bottom of the dielectric hole; and etching the etching stop layer to expose the conductive line. Page 14 471131 6. Scope of patent application 2. For the method of the first scope of patent application, wherein the hard mask mentioned above contains at least one nitrided layer. 3. The method according to item 1 of the scope of patent application, wherein the hard cover mentioned above contains at least an oxynitride layer. ; 4. The method according to item 1 of the scope of patent application, wherein the hard mask mentioned above includes at least a silicon carbide layer. \ \ 5. If the method of the first item of the patent application scope, wherein the thickness of the hard cover is about 2 0 0-4 0 0 0 Angstroms. : 6. The method according to item 1 of the scope of patent application, wherein the etching gas of the hard mask mentioned above contains at least hydrocarbon fluoride, argon and oxygen. 7. The method according to item 1 of the patent application range, wherein the second dielectric layer i includes at least one of a Si L K dielectric layer or a F 1 a r e dielectric layer. 8. The method according to item 1 of the scope of patent application, wherein the step of forming a lead groove between the second dielectric layer and the second dielectric layer described above uses the time mode to control etching termination. 9. The method according to item 1 of the scope of patent application, wherein the second dielectric layer further includes a wire trench etch stop layer to separate the organic 10w K dielectric 471131 6. The scope of the patent application layer and the chemical vapor phase Deposition of a dielectric layer. 10. The method according to item 9 of the scope of patent application, wherein the step of forming a wire trench between the second dielectric layer described above uses a wire trench etch stop layer to terminate the etching. Page 16