0650TWF.DOC/CHOU/002 A7 B7 五 、發明説明（I ) _ (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種靜態記憶體結構（SRAM)，且特別 是有關於一種具有由對稱性（Symmetrical)記憶細胞 (Memory Cell Arrary)構成之靜態隨機記憶陣列。 由於SRAM是所有半導體記憶體中速度最快者，因此 可應用範圍極廣，例如作爲電腦資料之快取等。但也由於 每一個記憶細胞需由4個電晶體組成，因而與其他記憶體 相比其集積度相對爲低。近年來在SRAM製程技術進入 0.35μπι之設計準則（Design Rule)以下時，常面臨光罩製 作時程過久與製程所需空間容許度（Margin)不足、以及瑕 疵率（Defect)與重製率（Rework)太高之困境，其中SRAM之 記憶細胞結構過於複雜是其主因，其不但造成良率偏低、 產品特性也因而不易控制，例如SRAM之操作電壓Vcc的最 低値不足，此外在具較多雜訊的環境下也有不穩定現象出 現。 目前靜態記憶體已廣泛應用於迷你電腦，微處理器系 統等一類的數位設備中，其可用來儲存一些系統資料，例 如以典型靜態記憶體而言，較普遍的單一記憶細胞電路結 構係如第1A圖所示。 經濟部中夬標準局員工消費合作社印製 請參照第1A圖，典型靜態隨機存取記憶體的記憶細胞 10係由一電阻（或阻抗元件）R1、一電阻（或阻抗元件）R2、 一金氧半（M0S)電晶體T1、一 M0S電晶體T2、-一 M0S電晶 體T3與一 M0S電晶體T4所構成。其中該電阻R1與M0S電 晶體T1構成之串接電路IQa，其兩端點分別耦接於…電壓 源Vcc與接地線Vh ;同理該電阻R2與M0S電晶體T2構成 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（）） 之串接電路10b，其兩端點亦分別耦接於上述電壓源Vcc 與接地線Vss。 此外，在節點A處，係分別連接有該M0S電晶體T2的 閘極（G2 ; Gate)、及M0S電晶體T1和M0S電晶體T3的汲 極（Dl，D3 ; Drain);同理在節點B上，亦分別連接有該 M0S電晶體T1的閘極G卜及M0S電晶體T2和M0S電晶體T4 的汲極D2、D4。至於該M0S電晶體T3與T4的閘極G3、 G4則皆耦接至字元線（Word Line)WL，而該M0S電晶體T3 與T4的源極（S3、S4 ; Source)則分別耦接至位元線（Bit Line)BL與互補位元線。其中，該等電晶體可爲加強型 之NM0S電晶體，電晶體Τ1與該電晶體Τ2是當作驅動器 (Driver)之用，而該電晶體Τ3與該電晶體Τ4則是當作存取 電晶體，以作SRAM的資料存取（Access)之用，而該電阻 R1與該電阻R2則是作負載（Load)之用。 經濟部中央標準局員工消費合作社印製 ·(請先閱讀背面之注意事項再填寫本頁) 圖1B所示爲圖1A之記憶細胞10電路之等效結構， 而圖1C則爲對應圖1B所設計之SRAM記憶細胞之基本層 佈局圖，其中首先在一基底12上定義一主動層14(Active Layer)，第一層多晶矽P0LY1係用以作爲電晶體ΤΙ、T2、 T3與T4之閘極和耦接該電晶體T3與T4之閘極的字元線 WL° 第二層多晶矽P0LY2係用作連接節點A處之該M0S電 晶體T2的閘極G2、及M0S電晶體T1和M0S電晶體T3的汲 極（Dl、D3)，並定義出一電阻R1 ;以及用作連接節點B 之該M0S電晶體T1的閘極G1、及M0S電晶體T2和M0S電 4 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） 47096ΰ Μ 0650TWF.DOC/CHOU/002 ____Β7 五、發明説明（彡） 晶體Τ4的汲極D2、D4，並定義出一電阻R2。此外該結構 也藉第二層多晶矽P0LY2來定義一電源線Vcc。 ί請先閱讀背面之注意事項再填寫本頁) 至於第一金屬層METAL1則用來形成與該電晶體T3、 T4的源極（S3、S4)分別耦接之位元線BL與互補位元線 iT。 另依據該等記憶細胞10組成之部份記憶陣列（Memory Ce 11 Arrary)電路，則如圖2A所示。該記憶陣列（Memory Cell Arrary)主要包括8個記憶細胞10a、1Gb、1.0c、 10d、10e、10f、10g、10h 及感測放大器 12a、12b， 且其係以列與行之方式配置成一陣列。字元線WL1以列的 方式連接記憶細胞10a、10b ;字元線WL2則以列的方式 連接記憶細胞10c、lGd，同理字元線WL3、WL4分別以 列的方式連接記憶細胞10e、10f，l〇g、10h。第一行 之位元線（Bit Line)BLl與互補位元線ϋΓ分別串接該行之 記憶細胞10a、l〇c、10e、10g及感測放大器12a ;第二 行之位元線（Bit Line)BL2與互補位元線則分別串接該 行之記憶細胞10b、l〇d、10f、10h及感測放大器12b。 經濟部中央標隼局員工消費合作社印^0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the Invention (I) _ (Please read the notes on the back before filling out this page) The present invention relates to a static memory structure (SRAM), and in particular to a kind of SRAM It has a static random memory array composed of Symmetrical Memory Cell Arrary. Because SRAM is the fastest of all semiconductor memories, it can be used in a wide range of applications, such as as a computer data cache. However, since each memory cell needs to be composed of 4 transistors, its accumulation degree is relatively low compared to other memories. In recent years, when the SRAM process technology has entered the design rule (Design Rule) of 0.35 μm, it often faces long photomask production time, insufficient space allowance (Margin), and defect rate and remanufacturing rate. (Rework) The predicament is too high, in which the memory cell structure of SRAM is too complicated is the main reason. It not only causes low yield, but also makes the product characteristics difficult to control. For example, the minimum operating voltage VSRAM of SRAM is insufficient. Instability also occurs in noisy environments. At present, static memory has been widely used in digital devices such as mini computers and microprocessor systems. It can be used to store some system data. For example, in typical static memory, the more common single memory cell circuit structure is as follows: Shown in Figure 1A. Printed by the Consumer Cooperative of the China Standards Bureau of the Ministry of Economics Please refer to Figure 1A. The memory cells of a typical static random access memory 10 are composed of a resistor (or impedance element) R1, a resistor (or impedance element) R2, and a gold An oxygen half (M0S) transistor T1, a M0S transistor T2,-a M0S transistor T3 and a M0S transistor T4. Among them, the resistor R1 and the M0S transistor T1 are connected in series to the circuit IQa. The two ends are respectively connected to the voltage source Vcc and the ground line Vh. Similarly, the resistor R2 and the M0S transistor T2 constitute 3. This paper is applicable to China. National Standard (CNS) A4 specification (210X297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention ()) The serial connection circuit 10b is also coupled to the above-mentioned voltage source Vcc and ground respectively Line Vss. In addition, at the node A, the gate (G2; Gate) of the M0 transistor T2 and the drain (D1, D3; Drain) of the M0 transistor T1 and the M0 transistor T3 are connected respectively; the same is true at the node On B, the gates Gb of the MOS transistor T1 and the drains D2 and D4 of the MOS transistor T2 and the MOS transistor T4 are also connected respectively. As for the gates G3 and G4 of the M0S transistor T3 and T4, both are coupled to the Word Line WL, and the sources (S3, S4; Source) of the M0S transistor T3 and T4 are respectively coupled Bit line BL and complementary bit line. Among them, these transistors can be reinforced NMOS transistors. Transistors T1 and T2 are used as drivers, while transistors T3 and T4 are used as access transistors. The crystal is used for data access of the SRAM, and the resistor R1 and the resistor R2 are used for load. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling out this page) Figure 1B shows the equivalent structure of the memory cell 10 circuit of Figure 1A, and Figure 1C is the counterpart of Figure 1B The layout of the basic layer of the designed SRAM memory cell. First, an active layer 14 (Active Layer) is defined on a substrate 12. The first layer of polycrystalline silicon P0LY1 is used as the gate and sum of the transistors Ti, T2, T3 and T4. The word line WL ° coupled to the gates of the transistors T3 and T4. The second layer of polycrystalline silicon P0LY2 is used to connect the gate G2 of the M0 transistor T2 at node A, and the M0S transistor T1 and M0S transistor T3. D1, D3), and defines a resistor R1; and the gate G1 of the M0 transistor T1 and the M0 transistor T2 and M0S used to connect to node B CNS> A4 specification (210X297 mm) 47096ΰ Μ 0650TWF.DOC / CHOU / 002 ____ Β7 V. Description of the invention (彡) The drain D2 and D4 of the crystal T4, and define a resistor R2. In addition, the structure also borrows the second layer Polycrystalline silicon P0LY2 to define a power line Vcc. Ί Please read the notes on the back first Then fill page) As a first metal layer for forming the METAL1 respectively coupled to the electrode (S3, S4) and the source of the transistor T3, T4 of the bit lines BL and a complementary bit line iT. In addition, a part of the memory array (Memory Ce 11 Arrary) circuit composed of the memory cells 10 is shown in FIG. 2A. The memory cell array mainly includes eight memory cells 10a, 1Gb, 1.0c, 10d, 10e, 10f, 10g, 10h, and sense amplifiers 12a, 12b. The memory cells are arranged in an array in a row and a row manner. . The character line WL1 is connected to the memory cells 10a and 10b in columns; the character line WL2 is connected to the memory cells 10c and 1Gd in columns; similarly, the character lines WL3 and WL4 are connected to the memory cells 10e and 10f in columns. 10g, 10h. The bit line BL1 in the first row and the complementary bit line ϋΓ are connected in series to the memory cells 10a, 10c, 10e, 10g and the sense amplifier 12a of the row; the bit line in the second row (Bit Line) BL2 and the complementary bit line are connected in series to the memory cells 10b, 10d, 10f, 10h and the sense amplifier 12b of the line, respectively. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^
以習知由8個記憶細胞IGa-IGh構成之SRAM陣列結構 之佈局（Layout)爲例，如圖2B所示，其係對應上述之圖2A 電路，包括：字元線WL1、WL2、WL3、WL4分別以列的方 式連接記憶細胞。位元線BL1、BL2與互補位元線 分別以行的方式串接該等記憶細胞，電源線Vcc設置於4 個記憶細胞間（10c、10d、10e、10f)之中間列，接地線 Vss則設置於兩行記憶細胞之間而由該8個記憶細胞共享 5 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（f) (share)—接地接觸窗15，其中黑色框線部份爲一記憶細 胞10d，由字元線WL2以階梯狀之方式連接電晶體T3、T4 之閘極。 由上述可知，習知SRAM佈局結構之基本層，如圖樣 (pattern)較爲緊密的主動層14 ，複晶矽層P0LY1 、 P0LY2，及金屬層METAL1，如圖1C所示，不僅轉角極多 且結構複雜，因此在實際生產過程中，其製程精確度及各 層次的對準控制皆不容易，而在光罩製作上更因結構複雜 使製程拉長，導致成本上揚、高失誤率之問題。 此外由於字元線不夠平直，在記憶細胞陣列中，將無 法適度縮短通過該字元線之信號的開關速度。 另一方面，接地線Vss設置於兩行記憶細胞之間而由8 個記憶細胞共享接地接觸窗15的結構使電性品質下降，雜 訊免疫力差，因而SRAM之操作電壓Vcc的最低値不足，在 具較多雜訊的環境下也有不穩定現象出現。 有鑑於此，本發明之主要目的即在於，提供一種靜態 隨機記憶陣列，包括： 複數個記憶細胞，其係以列與行之方式配置成一陣 經濟部中央標隼局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 列； 複數個字元線，分別以約略呈直線之列的方式串接該 記憶細胞； 複數個位元線與互補位元線，分別以行的方式交錯串 接該記憶細胞； 複數個電源線，分別設置於該每一列記憶細胞之丨::側 6 本紙張尺度適用中國國家標準（CNS〉A4規格（210X 297公釐） 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（乡） 而與前一列記憶細胞共用；及 Z請先閱讀背面之注意事項再填寫本頁) 複數個接地線，設置於該每兩相鄰列及兩相鄰行記憶 細胞間而由該四個記憶細胞共用。 本陣列更包括複數個感測放大器，分別以行的方式串 接該記憶細胞。 本陣列中，該記憶細胞結構包括：一第一阻抗元件、 一第二阻抗元件、一第一電晶體、一第二電晶體、一第三 電晶體與一第四電晶體，各電晶體分別具有源極、汲極、 及閘極，其中 該第一阻抗元件與第一電晶體藉一第一節點構成串接 電路，其兩端點分別耦接於上述電源線與接地線； 該第二阻抗元件與第二電晶體藉一第二節點構成串接 電路，其兩端點分別耦接於上述電源線與接地線； 於該第一節點處，係分別連接有該第二電晶體的閘 極、及第一電晶體和第三電晶體的汲極； 於該第二節點處，係分別連接有該第一電晶體的閘 極、及第二電晶體和第四電晶體的汲極； 經濟部中央標準局員工消費合作社印製 該第三、第四電晶體的閘極耦接至上述字元線；及 該第三、第四電晶體的源極分別耦接至上述位元線與 互補位元線。 其中，上述電晶體爲加強型之關0S電晶體。 此外該第一電晶體、第二電晶體係藉其源極耦接於上 述接地線。其中該些接地線，係藉一接地接觸窗而由四個 記憶細胞共用。 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（乙） 本發明之另一目的在於，提供一種靜態隨機記憶陣 列，其由複數個記憶細胞組成，而該記憶細胞之製造方法 包括： 在一基底區域分別定義一第一電晶體、一第二電晶 體、一第三電晶體與一第四電晶體之第一主動區、第二主· 動區、第三主動區、及第四主動區，並設定各主動區內源 極、汲極、閘極之位置； 定義形成第一、第二電晶體中汲極處之第一、第二掩 埋接觸窗； 於該主動區上以絕緣方式選擇性形成第一複晶矽層， 其分別形成各電晶體之閘極結構，並以上述掩埋接觸窗連 通第一、第二電晶體之汲極； 在該第二電晶體之源極處開設一接地接觸窗，及在 該、第三、第四電晶體之源極處分別開設一位示接觸窗、 及一互補位元接觸窗； 經濟部中央標準局員工消費合作杜印製 t請先閱讀背面之注意事項再填寫本頁) 形成一第一金屬層，其藉上述之接地接觸窗、位元接 觸窗、及互補位元接觸窗而分別形成連接該第二電晶體之 源極之接地線、連接第三電晶體之源極之位元線與連接第 四電晶體之源極之互補位元線； 在既定部份之主動區、第一層多晶矽、第一層金屬層 形成第一、第二、第三、第四介層窗，並定義出第一、第 二阻抗元件區； 沈積一第二複晶矽層，其形成第一阻抗元件，並藉上 述之第一介層窗而連接該第三電晶體的汲極，形成第二阻 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（q ) 抗元件，並藉上述之第二介層窗而連接該第四電晶體的汲 極；形成一導線，用來作爲連接上述第一、第二阻抗元件 之電源線，以及形成藉該第三、第四介層窗來連接上述位 兀線及互補位兀線之部分。 其中，在該基底上，係先以局部氧化隔離製程形成場 氧化物區，而未被氧化的平坦部份即形成主動區域。 此外，第三、第四電晶體位在下半區，其第三、第四 主動區略呈I型，源極均位在底側，汲極位在接近第一、 第二電晶體之處。第一、第二電晶體位在上半區，其第一、 第二主動區分別略呈ϋ型及L型，源極位在該基底兩側邊， 汲極位在該基底中間，並且彼此以對角線之方式隔開。 又其中，上述第一複晶矽層亦分別形成爲 第一、第二部份，且其互呈倒L型，並各以既定位置 而藉上述掩埋接觸窗來連通第一、第二電晶體之汲極；以 及 一字元線，用來作爲第三、第四電晶體之閘極，且其 係約略呈一字型。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1Α圖係顯示習知一種由4個金氧半電晶體構成 之記憶細胞的電路圖； 第1 Β係顯示圖1 Α之習知記憶細胞電路之等效結構； 第1C圖係顯示習知對應圖1B所設計之SRAM記憶細胞 9 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐） — (請先閲讀背面之注意事項再填寫本頁) _ f 47ϋ96ΰ 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（？） 之基本層佈局圖； 第2A圖係顯示依據圖1C之記憶細胞組成之部份記憶 陣列（Memory Cell Arrary)電路； 第2B圖係顯示對應上述圖2A電路之習知由8個記憶細 胞構成之SRAM陣列結構佈局； ' 第3A圖至第3K圖係顯示記憶細胞結構之各層佈局 圖； 第3L圖係顯示本發明之較佳實施例中一記憶細胞結構 之完整佈局圖；及 第4圖係顯示本發明之較佳實施例中，依據圖3L之記 憶細胞結構構成之記憶陣列。 實施例 經濟部中央標隼局員工消費合作社印製 ，請參閱第3A-3K圖，3A-3K圖係顯示本發明之較佳實 施例中一記憶細胞結構之各層佈局圖，第3L圖則爲本發明 之較佳實施例中一記憶細胞結構之完整佈局圖，其中本實 施例採用方向爲100之P型矽基底或具P形井之N型矽基底 18，每一層佈局係對應一光罩，每一製程步驟則依據該些 光罩製版來定義所需之圖樣，該些製程步驟係用來達成上 述圖1A電路之結構，包括下式以加號表示之各節點連接關 係，以下即配合圖3A-3L及各製程步驟予以說明。 + Vcc ·(請先閲讀背面之注意事項再填寫本頁) (1)節點 ίο 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 470965 0650TWF.DOC/CHOU/002 A7 __B7 五、發明説明（θ )Taking the conventional SRAM array structure composed of 8 memory cells IGa-IGh as an example, as shown in FIG. 2B, it corresponds to the circuit of FIG. 2A described above, including: word lines WL1, WL2, WL3, WL4 is connected to memory cells in columns. Bit lines BL1, BL2 and complementary bit lines are connected in series to the memory cells respectively. The power line Vcc is arranged in the middle column among the 4 memory cells (10c, 10d, 10e, 10f), and the ground line Vss is It is set between two rows of memory cells and shared by the eight memory cells. The paper size is applicable to Chinese National Standard (CNS) A4 specification (210 × 297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 5. Description of the invention ( f) (share)-the ground contact window 15, in which the black framed line is a memory cell 10d, and the word lines WL2 are connected to the gates of the transistors T3 and T4 in a stepwise manner. From the above, it is known that the basic layers of the SRAM layout structure are familiar, such as the active layer 14 with a tighter pattern, the polycrystalline silicon layers P0LY1, P0LY2, and the metal layer METAL1, as shown in FIG. 1C. The structure is complicated, so in the actual production process, its process accuracy and alignment control at various levels are not easy, and in the production of photomasks, the process is lengthened due to the complicated structure, which causes problems of rising costs and high error rates. In addition, since the word line is not flat enough, in a memory cell array, the switching speed of a signal passing through the word line cannot be appropriately shortened. On the other hand, the structure in which the ground line Vss is disposed between two rows of memory cells and the ground contact window 15 is shared by 8 memory cells reduces the electrical quality and the noise immunity is poor. Therefore, the minimum operating voltage Vcc of the SRAM is insufficient. Instability also occurs in environments with more noise. In view of this, the main object of the present invention is to provide a static random memory array, including: a plurality of memory cells, which are arranged in a row and a row printed by the staff consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please Read the precautions on the back before filling in this page) column; multiple character lines, each connected to the memory cell in a roughly straight line; multiple bit lines and complementary bit lines, respectively, in a row The memory cells are staggered and connected in series; a plurality of power cords are respectively arranged in the memory cells of each column 丨 :: 6 This paper size applies to Chinese national standards (CNS> A4 specification (210X 297 mm) 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of invention (township) It is shared with the previous column of memory cells; and Z, please read the precautions on the back before filling this page) A plurality of ground wires are provided in each two adjacent columns and two adjacent rows The memory cells are shared among the four memory cells. The array further includes a plurality of sense amplifiers, and the memory cells are serially connected in a row manner. In this array, the memory cell structure includes: a first impedance element, a second impedance element, a first transistor, a second transistor, a third transistor, and a fourth transistor, and each transistor is respectively A source electrode, a drain electrode, and a gate electrode, wherein the first impedance element and the first transistor constitute a series circuit by a first node, and two ends of the first impedance element and the first transistor are respectively coupled to the power line and the ground line; The impedance element and the second transistor constitute a series circuit by a second node, and its two ends are respectively coupled to the power line and the ground line; at the first node, the gates of the second transistor are respectively connected. Electrode, and the drain of the first transistor and the third transistor; at the second node, the gate of the first transistor, and the drain of the second transistor and the fourth transistor are respectively connected; The gates of the third and fourth transistors printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economics are coupled to the word lines; and the sources of the third and fourth transistors are respectively coupled to the bit lines and Complementary bit lines. Among them, the transistor is a reinforced OFF-type transistor. In addition, the first transistor and the second transistor system are coupled to the above-mentioned ground line through their sources. The ground wires are shared by four memory cells through a ground contact window. 7 This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention (B) Another object of the present invention is to provide a static random memory array , Which is composed of a plurality of memory cells, and the manufacturing method of the memory cells includes: defining a first transistor, a second transistor, a third transistor, and a first of a fourth transistor in a base region, respectively. Active area, second active area, third active area, and fourth active area, and set the positions of the source, drain, and gate in each active area; define the drain in the first and second transistors First and second buried contact windows; selectively forming a first polycrystalline silicon layer on the active region in an insulating manner, which respectively form the gate structure of each transistor, and communicate with the first and second buried contact windows through the above-mentioned buried contact windows; The drain of the second transistor; a ground contact window is provided at the source of the second transistor, and a contact window is provided at the source of the third, fourth, and fourth transistors, and a complementary Bit contact window Department of Central Standards Bureau ’s consumer cooperation Du printed t, please read the notes on the back before filling out this page) to form a first metal layer, which is based on the above ground contact window, bit contact window, and complementary bit contact window A ground line connected to the source of the second transistor, a bit line connected to the source of the third transistor, and a complementary bit line connected to the source of the fourth transistor are respectively formed; A first layer of polycrystalline silicon and a first metal layer form first, second, third, and fourth interlayer windows, and define first and second impedance element regions; a second polycrystalline silicon layer is deposited, which forms a first An impedance element, and connected to the drain of the third transistor through the above-mentioned first interlayer window to form a second resistance. 8 This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 470965 0650TWF. DOC / CHOU / 002 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of invention (q) anti-element, and connected to the drain of the fourth transistor through the second interlayer window described above; forming a wire , Used to connect the first, The power line of the second impedance element and a portion forming the above-mentioned bit line and the complementary bit line through the third and fourth interlayer windows. Among them, on this substrate, a field oxide region is first formed by a local oxidation isolation process, and an unoxidized flat portion forms an active region. In addition, the third and fourth transistors are located in the lower half, and the third and fourth active regions are slightly I-shaped. The source is located on the bottom side and the drain is located near the first and second transistors. The first and second transistors are located in the upper half, and the first and second active regions are slightly ϋ-shaped and L-shaped, respectively. The source is located on both sides of the substrate, and the drain is located in the middle of the substrate. Diagonally spaced. In addition, the first polycrystalline silicon layer is also formed as the first and second parts, and they are inverted L-shaped each other, and the first and second transistors are connected by the above-mentioned buried contact windows at a predetermined position. The drain electrode; and a word line, which is used as the gate of the third and fourth transistors, and it is approximately a word. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: FIG. 1A shows a conventional method by Circuit diagram of memory cells made of 4 metal-oxide semi-electric crystals; Figure 1B shows the equivalent structure of the conventional memory cell circuit shown in Figure 1A; Figure 1C shows the SRAM memory cell designed conventionally corresponding to Figure 1B 9 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) — (Please read the precautions on the back before filling this page) _ f 47ϋ96ΰ 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention (?) Basic layer layout diagram; Figure 2A shows a part of a memory cell circuit composed of memory cells according to Figure 1C; Figure 2B shows a conventional memory circuit composed of 8 memory cells corresponding to the circuit of Figure 2A SRAM array structure layout; 'Figures 3A to 3K are layout diagrams showing layers of a memory cell structure; Figure 3L is a complete layout diagram of a memory cell structure in a preferred embodiment of the present invention; and Figure 4 is Show Preferred embodiment of the present invention in accordance with FIG. 3L remember the memory array of the memory cell structure. Example Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, please refer to Figures 3A-3K. Figures 3A-3K are layout diagrams of the layers of a memory cell structure in the preferred embodiment of the present invention. Figure 3L is A complete layout of a memory cell structure in a preferred embodiment of the present invention. In this embodiment, a P-type silicon substrate with a direction of 100 or an N-type silicon substrate 18 with a P-shaped well is used. Each layer layout corresponds to a photomask Each process step is to define the required pattern according to the mask plate making. These process steps are used to achieve the structure of the circuit of FIG. 1A described above, including the connection relationship of each node represented by a plus sign in the following formula. Figure 3A-3L and each process step are explained. + Vcc · (Please read the precautions on the back before filling this page) (1) Node ίο The paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 __B7 V. Invention description (θ)
(2)源極S3+位元線BL(2) Source S3 + bit line BL
(3) 源極S4+互補位元線BL (4) 源極接地線Vss (ro\(3) Source S4 + complementary bit line BL (4) Source ground line Vss (ro \
(5) 閘極=+字元線WL 經濟部中央標準局員工消費合作社印製 ί請先閲讀背面之注意事項再填寫本頁) 其中源極s ;汲極D ;閘極G ;電晶體代號1-4。 首先請參閱第3A圖，該步驟係用來定義各電晶體T1、 T2、T3、T4之主動區21、22、23、24(陰影區），及場 氧化區30(白色區域），例如可先在該基底18上以局部氧化 隔離製程（LOCOS)形成場氧化物區30，而未被氧化的平坦 部份即形成主動區域，其中電晶體T3、T4位在下半區，其 主動區23、24略呈I型，源極S3、S4位在底側，汲極D3、 D4位在接近電晶體ΤΙ、T2之側；電晶體ΤΙ、T2位在上半 區，.其主動區21、22分別略呈U型及L型，源極SI、S2 位在基底18兩側邊，汲極Dl、D2位在該基底中間，並且 彼此以對角線之方式隔開。 其次請參閱第3B圖，該步驟係用來定義電晶體T1、 T2之主動區中汲極Dl 、D2之掩埋接觸窗（Buried(5) Gate = + character line WL Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Please read the precautions on the back before filling out this page) where source s; drain D; gate G; transistor code 1-4. First, please refer to FIG. 3A. This step is used to define the active regions 21, 22, 23, 24 (shaded regions) and field oxidation regions 30 (white regions) of the transistors T1, T2, T3, and T4. A field oxide region 30 is first formed on the substrate 18 by a local oxidation isolation process (LOCOS), and the unoxidized flat portion forms an active region. The transistors T3 and T4 are located in the lower half region, and the active regions 23, 24 is slightly I-shaped, the sources S3 and S4 are located on the bottom side, and the drains D3 and D4 are located near the transistors T1 and T2; the transistors T1 and T2 are located in the upper half, and their active regions 21 and 22 They are slightly U-shaped and L-shaped, respectively. The sources SI and S2 are located on both sides of the substrate 18, and the drains D1 and D2 are located in the middle of the substrate, and are separated from each other diagonally. Next, please refer to FIG. 3B. This step is used to define the buried contact windows of the drain electrodes D1 and D2 in the active regions of the transistors T1 and T2.
Contact)Cl 、 C2 〇 請參閱第3C圖，完成上述步驟後，即進行第一層多晶 矽P0LY1之製版，其於該圖3A之主動區21、22、23、24， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（h) 及場氧化區30上以絕緣方式選擇性形成字元線WL，及複晶 矽PI、P2,其以上述掩埋接觸窗Cl、C2連通電晶體T1、 T2之汲極D1、⑽，並分別形成閘極結構Gl、G2。 如先在該基底18上適度植入離子以調整起始電壓 (Threshold Voltage Adjustment)，隨後於該砂基底 18 表 面形成一閘極氧化層（未顯示）’接著沈積一導體層’如第 一複晶矽層P0LY1，其次以微影製程（lithography)定義閘 極圖案，經蝕刻程序形成目前用來作爲電晶體ΤΙ、T2之閘 極（Gl、G2)的多晶矽PI、P2，且其互呈倒L型，另該多 晶矽PI、P2之既定位置Pla、P2a係藉上述掩埋接觸窗 Cl、C2來連通電晶體ΤΙ、T2之汲極Dl、D2 ;以及形成 用來作爲電晶體T3、T4之閘極（G3、G4)的字元線WL ’且 其係約略呈一字型，隨後沈積一層絕緣層31如硼磷矽玻璃 (BPSG)，而電晶體ΤΙ、T2、T3、T4通道所在區域即爲第 一多晶矽P0LY1構成之閘極所橫過圖3A主動區21、22、 23、24之位置，如此由源/汲極、通道、及該通道上方之 閘極可構成上述複數個M0S電晶體結構。 經濟部中央標準局員工消費合作社印製 ·(請先閱讀背面之注意事項再填寫本頁) 請參閱第3D、3E圖，接下來之製程步驟是形成部份 主動區、第一層多晶矽與後續連接層如第一金屬層METAL1 間的接觸窗，例如先在電晶體T2之源極S2處開設一接地接 觸窗42，及在電晶體T3、T4之源極S3 ' S4處分別開設 一接觸窗43、44(見圖3A之主動區）。其次，如第3E圖， 沈積一第一金屬層METAL1，其藉上述之接觸窗而分別用來 形成連接電晶體T2之源極S2之接地線Vss、連接電晶體T3 12 本紙張尺度適^用^^^準（（：奶）以規格（210父297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（丨ί ) 之源極S3之位元線BL與連接電晶體T4之源極S4之互補位 元線i，然後再沈積一層絕緣層32，其中電晶體T1之源 極S1之接地線係與鄰接記憶細胞共用，在此並未顯示。 請參閱第3F、3G、3H圖，接下來之製程步驟是形成 部份主動區、第一層多晶矽、第一層金屬層與後續連接層’ 如第二層複晶砂層P0LY2間的介層窗（poly via)，並定義 所需之負載。例如先在圖3A、3C之電晶體Π之閘極G1、 電晶體T4之汲極D4連接處開設一介層窗53a ;電晶體T2 之閘極G2、電晶體T3之汲極D3連接處開設一介層窗54a， 及另外在電晶體T3、T4之源極S3、S4處上方之金屬層 METAL1(即位元線BL和互補位元線ΪΓ)分別開設一介層窗 經濟部中央標隼局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 53b、54b(見圖3A之主動區）。其次，如第3G圖，·沈積一 第二複晶矽層P0LY2，其形成複晶矽層53，並藉上述之介 層窗53a而連接（圖1A之節點A處）該M0S電晶體T3的汲極 D3，隨後依據圖3H之負載（LOAD)光罩定義出一高阻値電阻 R1 ;形成複晶矽層54，並藉上述之介層窗54a而連接（圖 1A之節點B處）該M0S電晶體T4的汲極D4，隨後依據圖3H 之負載（LOAD)光罩定義出一高阻値電阻R2 ;形成複晶矽層 55，在進行上述圖3H之負載（LOAD)光罩製版時，其同時摻 植離子形成一低阻値之導線，用來作爲連接上述電阻R1、 R2之電源線Vcc ;以及形成複晶矽層53’、54’，並藉上述 之介層窗53b、54b而連接上述位元線BL及互補位元線 iT。 請參閱第31、3J、3K圖，接下來之製程爲可視特殊 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 29*7公釐） 47ΰ96ΰ 0650TWF.DOC/CHOU/002 Α7 Β7 五、發明説明（丨λ) 設計需要而予以選擇者，首先定義形成一層靜電放電保護 層（ESD LayeiOSOa、60b，然後再沈積一層絕緣層33，隨 之開設一金屬介層窗65，如此再定義形成一第二金屬層 METAL2，以銜接作爲接地線Vss之第一金屬層METAL1，即 完成上述SRAM結構之佈局。 依據上述之各層佈局可形成如第3L圖之單一 SRAM記 憶細胞結構，其中該記憶細胞2G包括一電阻Rl、R2、一 電晶體ΤΙ、T2、T3與T4。其中電晶體Π的閘極G1、及 電晶體T2和電晶體T4的汲極D2、D4係耦接在一起，並藉 圖3F之介層窗54a連通該電阻R2，圖3B之接觸窗C2係用 來連通電晶體Π的閘極G1、及電晶體T2的汲極D2 ;同理 電晶體T2的閘極G2、及電晶體T1和電晶體T3的汲極D1、 D3係耦接在一起，並藉圖3F之介層窗53a連通該電阻R1， 圖3B之接觸窗C1係用來連通電晶體T2的閘極G2、及電晶 體T1的汲極D1，另依據圖3G，連接電阻Rl、R2之複晶 砍層55係作爲電源線Vcc。 此外，圖3C之電晶體T3與T4的閘極G3、G4皆耦接 至字元線（Word Line)WL，而依據圖3D、3E，該電晶體T3 經濟部中央標準局員工消費合作社印製 ·(請先閱讀背面之注意事項再填寫本頁) 與T4的源極（S3、S4)則分別藉接觸窗43、44耦接至作爲 位元線（Bit Line)BL與互補位元線ΪΓ之第一金屬層 METAL1 。 連接電晶體T2的源極S2之接地線Vss則藉圖3D之接 觸窗42連通第一金屬層METAL1形成。 請參閱第4圖，其顯示本發明之較佳實施例中，依據 本紙張尺度適用中國國家標準（CNS )八4規格（2丨ΟΧ297公釐） A7 B7 l65〇TWF.DOC/CHOU/002 五、發明说明（β) <請先閱讀背面之注意事項再填寫本頁) 圖3L之記憶細胞結構構成之記憶陣列’陣列包括4個記憶 ，細胞20a、2Gb、20c、2Gd，字元線WL1以列的方式連接 言己億細胞2Ga、2Gb ;字元線WL2則以列的方式連接記憶 糸田胞2Gc、2Gd。第一行之位元線（Bi t L ine)BL1與互補位 7元線百ΪΓ分別串接該行之記憶細胞20a、20c;第二行之位’ 元;線（Bit Line)BL2與互補位元線則分別串接該行之記 億細胞20b、20d °其中由於圖3L之單一記憶細胞具有對 稱性，故可利用該單一記憶細胞之上下左右鏡向接合，而 定義出4個記憶細胞2Ga-2Gd構成之SRAM陣列結構之佈 局。 依據本實施例由4個記憶細胞2Ga-2Gd構成之SRAM陣 列結構之佈局（Layout)，其係對應上述之圖1A電路，包括： 字元線WL1、WL2分別以列的方式連接記憶細胞之存取電 晶體如上述T3、T4的閘極。位元線BL1、BL2與互補位 元線分別以行的方式串接該等記憶細胞之存取電 晶體如上述Τ3、Τ4的汲極，電源線Vcc設置於同一列記 億細胞如2Ga、2Gb之上側或2Gc、2Gd底側，接地線Vss 經濟部中央標準局員工消費合作社印製 則設置於2平行列記憶細胞間，如2Ga、20b及其上一列平 行相鄰記憶細胞（未顯示）之間而由該4個記憶細胞共享 (share)—接地接觸窗25,其中字元線WL1、WL2以約略呈 直線之方式連接電晶體如T3、T4之閘極。 縱由上述，本發明提供一種靜態記憶體記憶細胞之結 構，其具有下列優點： (1)利用該SRAM佈局結構可以充分利用晶片空間，並 15 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 470965 0650TWF.DOC/CHOU/002 A7 B7 五、發明説明（丨1f) 在不縮小元件尺寸的條件下提高密度，而於單位面積內製 造更多的記憶單元。 (2) 該SRAM佈局結構之基本層，其圖樣不僅較爲緊 密，主動層19,複晶矽層P0LY1、P0LY2,及金屬層METAL1 等，不僅結構簡潔單純且完全滿足設計準則’因此不需要’ 膨脹記憶細胞的大小，在實際生產過程中’其製程精確度 及各層次的對準控制亦較爲容易，故在光罩製作上可使製 程縮短，降低成本及失誤率。 (3) 此外在電性的改良上，由於字元線十分平直，在 記憶細胞陣列中’過該字元線之信號的開關速度將因此而 縮短。 (4) 另一方面，接地線Vss設置於2平行列記憶細胞 間而僅由該4個記憶細胞共享（share)—接地接觸窗，使電 性品質改善，雜訊免疫力提昇，因而SRAM之操作電壓VCC 的最低値可以降低，有效解決在具較多雜訊的環境下發生 不穩定現象的問題。 經濟部中央標準局員工消費合作社印製 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS) Μ規格（210X297公釐）Contact) Cl, C2 〇 Please refer to Figure 3C. After completing the above steps, the first layer of polycrystalline silicon P0LY1 is plated. It is in the active area 21, 22, 23, 24 of Figure 3A. This paper standard applies Chinese national standards. (CNS) A4 specification (210X297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention (h) The word line WL is selectively formed on the field oxidation region 30 by insulation, and the polycrystalline silicon PI, P2 connects the drain electrodes D1 and T2 of the transistors T1 and T2 with the above-mentioned buried contact windows Cl and C2, and forms the gate structures G1 and G2, respectively. For example, moderately implanting ions on the substrate 18 to adjust the threshold voltage (Threshold Voltage Adjustment), and then forming a gate oxide layer (not shown) on the surface of the sand substrate 18, and then depositing a conductor layer as in the first step. The crystalline silicon layer P0LY1 is followed by a gate pattern defined by a lithography process, and the polycrystalline silicon PI and P2 currently used as the gates (Gl, G2) of the transistors Ti and T2 are formed by an etching process, and they are inverted Type L, and the predetermined positions Pla and P2a of the polycrystalline silicon PI and P2 are connected to the drain electrodes D1 and D2 of the transistors T1 and T2 through the above-mentioned buried contact windows Cl and C2; and the gates for the transistors T3 and T4 are formed The character line WL ′ of the pole (G3, G4) is approximately a letter shape, and then an insulating layer 31 such as borophosphosilicate glass (BPSG) is deposited, and the regions where the transistors T1, T2, T3, and T4 are located are The gate formed by the first polysilicon P0LY1 crosses the positions of the active regions 21, 22, 23, and 24 in FIG. 3A, so that the source / drain, the channel, and the gate above the channel can form the above-mentioned multiple M0S Transistor structure. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the notes on the back before filling out this page) Please refer to Figures 3D and 3E. The next process steps are to form part of the active area, the first layer of polycrystalline silicon and subsequent The connection layer is a contact window between the first metal layer METAL1. For example, a ground contact window 42 is firstly provided at the source S2 of the transistor T2, and a contact window is respectively provided at the source S3'S4 of the transistor T3 and T4. 43, 44 (see the active area of Figure 3A). Secondly, as shown in FIG. 3E, a first metal layer METAL1 is deposited, which is used to form a ground line Vss connected to the source S2 of the transistor T2 and a connection to the transistor T3 through the above-mentioned contact window. ^^^ Standard ((: milk) to specifications (210 father 297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention (丨 ί) bit line BL of source S3 and connection transistor T4 The complementary bit line i of the source S4 is then deposited with an insulating layer 32, wherein the ground line of the source S1 of the transistor T1 is shared with the adjacent memory cells and is not shown here. Please refer to 3F, 3G, Figure 3H, the next process step is to form a part of the active area, the first layer of polycrystalline silicon, the first metal layer and the subsequent connection layer, such as a poly via between the second polycrystalline sand layer P0LY2, and define The required load. For example, a dielectric window 53a is first opened at the junction of the gate G1 of the transistor Π and the drain D4 of the transistor T4 in FIGS. 3A and 3C; the gate G2 of the transistor T2 and the drain of the transistor T3 A dielectric layer window 54a is opened at the D3 connection, and a metal layer above the sources S3 and S4 of the transistors T3 and T4 METAL1 (the bit line BL and the complementary bit line ΪΓ) respectively opened a mezzanine window printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 53b, 54b (see Figure 3A) Active area). Secondly, as shown in Fig. 3G, a second polycrystalline silicon layer P0LY2 is deposited, which forms the polycrystalline silicon layer 53 and is connected (via node A in FIG. 1A) by the above-mentioned interlayer window 53a. The drain D3 of the transistor T3 is then defined as a high-resistance chirp resistor R1 according to the load mask of FIG. 3H; a polycrystalline silicon layer 54 is formed and connected by the above-mentioned interlayer window 54a (node of FIG. 1A B) The drain D4 of the M0S transistor T4, and then a high-resistance chirp resistor R2 is defined according to the load mask of FIG. 3H; a polycrystalline silicon layer 55 is formed, and the above-mentioned load (LOAD) of FIG. 3H is performed When making a photomask, it is doped with ions to form a low-impedance wire, which is used as the power supply line Vcc to connect the resistors R1 and R2; and the polycrystalline silicon layers 53 'and 54' are formed. The windows 53b and 54b connect the above-mentioned bit line BL and the complementary bit line iT. Please refer to Figs. 31, 3J, and 3K. The manufacturing process can be selected according to the Chinese national standard (CNS> A4 size (210 X 29 * 7 mm), 47ΰ96ΰ 0650TWF.DOC / CHOU / 002 Α7 Β7. First define a layer of electrostatic discharge protection (ESD LayeiOSOa, 60b), then deposit a layer of insulation 33, and then open a metal interlayer window 65, so define a second metal layer METAL2, and connect it as the ground line Vss The first metal layer METAL1 completes the layout of the above SRAM structure. According to the layout of the above layers, a single SRAM memory cell structure as shown in FIG. 3L can be formed. The memory cell 2G includes a resistor R1, R2, a transistor T1, T2, T3, and T4. The gate electrode G1 of the transistor Π, and the drain electrodes D2 and D4 of the transistor T2 and the transistor T4 are coupled together, and the resistor R2 is communicated through the interlayer window 54a of FIG. 3F, and the contact window C2 of FIG. 3B is The gate G1 of the transistor Π and the drain D2 of the transistor T2; the gate G2 of the transistor T2 and the drains D1 and D3 of the transistor T1 and the transistor T3 are coupled together, The resistor R1 is connected through the interlayer window 53a of FIG. 3F. The contact window C1 of FIG. 3B is used to connect the gate G2 of the transistor T2 and the drain D1 of the transistor T1. In addition, according to FIG. 3G, the resistors R1, R1, The polycrystalline layer 55 of R2 is used as the power line Vcc. In addition, the gates G3 and G4 of the transistors T3 and T4 of FIG. 3C are coupled to the Word Line WL. According to FIGS. 3D and 3E, the transistor T3 is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. · (Please read the precautions on the back before filling in this page) The source electrodes (S3, S4) of T4 are coupled to the bit lines BL and complementary bit lines 互补 Γ through contact windows 43, 44 respectively. The first metal layer METAL1. The ground line Vss connected to the source S2 of the transistor T2 is formed by connecting the first metal layer METAL1 through the contact window 42 of FIG. 3D. Please refer to FIG. 4, which shows a preferred embodiment of the present invention. According to the paper size, the Chinese National Standard (CNS) 8 4 specifications (2 丨 〇297 mm) A7 B7 1650TWF.DOC / CHOU / 002 5 2. Description of the invention (β) < Please read the notes on the back before filling out this page) Figure 3L The memory array of the memory cell structure 'array includes 4 memories, cells 20a, 2Gb, 20c, 2Gd, word line WL1 Columns are connected to 2Ga and 2Gb cells; word line WL2 is connected to memory cells 2Gc and 2Gd in columns. Bit line BL1 in the first row and the 7-bit line of the complementary bit Hundred Ϊ Γ are connected in series to the memory cells 20a and 20c in the row; bit line BL2 in the second row and complementary The bit lines are connected in series to the memory cells 20b and 20d of the row. Among them, since the single memory cell of FIG. 3L has symmetry, the single memory cell can be used to join the upper and lower mirrors to define four memory cells. 2Ga-2Gd layout of the SRAM array structure. According to this embodiment, the layout of the SRAM array structure composed of 4 memory cells 2Ga-2Gd corresponds to the above-mentioned circuit of FIG. 1A and includes: word lines WL1 and WL2 are connected to the memory cells in columns. Take the transistor like the gate of T3, T4 mentioned above. Bit lines BL1, BL2 and complementary bit lines are connected in series to the access transistors of the memory cells such as the drains of T3 and T4 mentioned above, and the power line Vcc is arranged in the same column of 100 million cells such as 2Ga and 2Gb. The upper side or the bottom side of 2Gc, 2Gd. The ground wire Vss is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. It is set between 2 parallel rows of memory cells, such as 2Ga, 20b and the previous row of parallel adjacent memory cells (not shown). The four memory cells share a ground contact window 25, in which the word lines WL1 and WL2 are connected to the gates of transistors such as T3 and T4 in a substantially straight line. Despite the above, the present invention provides a structure of a static memory memory cell, which has the following advantages: (1) the chip space can be fully utilized by using the SRAM layout structure, and 15 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification ( 210X297 mm) 470965 0650TWF.DOC / CHOU / 002 A7 B7 V. Description of the invention (丨 1f) Increase the density without reducing the size of the component, and make more memory cells per unit area. (2) The basic layer of the SRAM layout structure is not only compact, the active layer 19, the polycrystalline silicon layer P0LY1, P0LY2, and the metal layer METAL1, etc., not only has a simple and simple structure, but also fully meets the design criteria 'so not needed' In the actual production process, the size of the expanded memory cells is also relatively easy to control the process accuracy and alignment at various levels. Therefore, in the production of the photomask, the process can be shortened, and the cost and error rate can be reduced. (3) In addition, in terms of electrical improvement, since the word line is very straight, the switching speed of a signal passing through the word line in the memory cell array will be shortened accordingly. (4) On the other hand, the ground line Vss is set between two parallel memory cells and is shared by the four memory cells only. The ground contact window improves the electrical quality and improves the immunity of noise. The minimum value of the operating voltage VCC can be reduced, which effectively solves the problem of instability in an environment with more noise. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Some modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. This paper size applies to Chinese National Standard (CNS) M specifications (210X297 mm)